JP2009059964A - Method of manufacturing semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor apparatus that improves interfacial characteristics of an insulating film having a metal element. <P>SOLUTION: The method includes a step of forming a structure wherein a lower layer, a Ge layer, a Ge oxide layer, and an upper layer are stacked in order, and a step of removing the Ge oxide layer and Ge layer using a heat treatment to bond the upper layer and the lower layer directly to each other. The upper layer or the lower layer is formed of an insulator having a metal element. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a laminated structure.

  Although high speed and high performance of semiconductor devices have been promoted, it is no longer difficult with a simple scaling method as in the past. For example, in a SiO2 film that is generally used as a gate insulator film, the leakage current is unacceptably large, so it is difficult to reduce the thickness to 1 nm or less. The identity of this leakage current is mainly due to the quantum tunneling effect, and the influence of the film becomes smaller as the physical film thickness is smaller.

  Therefore, a high dielectric film (high dielectric film; high-k film) containing a metal element has come to be expected as a gate insulating film replacing the SiO2 film. This is because if the dielectric constant of the gate insulating film is higher than the dielectric constant 3.9 of the SiO2 film, it can be electrically thinned instead of physically thinned.

  For example, HfO2 is known to have a dielectric constant of about 18, and the same capacitance as the SiO2 film is obtained with a physical thickness that is thicker than that of the SiO2 film. Here, when compared using the electrical film thickness EOT (Equivalent Oxide Thickness) of the high-dielectric film when converted to the SiO2 film thickness, the HfO2 film is about the same as the SiO2 film at the same EOT. 4.6 times (= 18 / 3.9) can be physically thick. When the insulating film becomes thicker, the distance that electrons tunnel through the band gap of the insulating film becomes longer and the tunneling probability becomes lower, so that the leakage current can be kept low.

  However, actually, when an HfO2 film is formed on a Si substrate, a so-called interfacial layer tends to be formed at the interface. This is mainly because oxygen in the atmosphere during film formation passes through the HfO2 film and oxidizes the substrate. The interface layer thus formed is a low dielectric material (low-k material) having a dielectric constant substantially equal to or slightly larger than that of the SiO2 film. First, a high dielectric film is deposited on a pretreated Si substrate. Then, an interface layer is formed on the Si substrate. After that, for example, when heat treatment is performed in an N2 atmosphere, the interface layer may maintain almost the same thickness depending on the conditions, but oxygen in the atmosphere or in the film reaches the Si substrate and oxidizes the substrate. However, the film may be further increased. In addition to the HfO2 film, other layers such as titania film, titania film, zirconia film, Hf silicate film, and Hf aluminate film also have an interface layer. Tend to be formed. This interface layer was a major obstacle to increasing the dielectric constant.

Here, it is known that the interface layer can be removed if specific materials and conditions are satisfied (see Non-Patent Document 1). When ZrO2 is deposited on a Ge substrate without heat treatment, a Ge oxide interface layer that has a composition close to that of GeO2 is formed. When this interface layer is heat-treated
GeO2 + Ge → 2GeO (gas) (1)
And is desorbed from the interface in the state of GeO (gas). Then, the interface layer that was originally present disappears, and a ZrO2 / Ge structure is formed. However, this phenomenon occurs only in ZrO2 on the Ge substrate and is not versatile. In addition, the MIS structure using a Ge substrate has many problems such as interfacial state, and because the melting point of Ge is low, heat treatment causes interdiffusion at the interface, which aims to modify the high dielectric film. There was a problem that high temperature heat treatment (> 700 ° C.) was not possible.

  Therefore, in recent years, attempts have been made to use a high dielectric film such as LaAlO that does not generate an interface layer with the Si substrate. When the composition of La: Al: O is 1: 1: 3, the physical thickness is 2 nm and EOT = 0.31 nm, so the dielectric constant is about 25 (see Non-Patent Document 2).

  However, there is a problem that metals such as LaAlO La and Al diffuse into the Si substrate when directly bonding. When metal diffuses into the substrate, there is a problem that mobility is deteriorated in a metal insulator semiconductor field effect transistor (MISFET), and thus diffusion needs to be suppressed. In addition, when the direct bonding is performed, the strain in the Si substrate near the interface increases, which is not preferable from the viewpoint of increasing the interface state. Furthermore, considering that there is a need to lower the process temperature in the future, the need for a high temperature to bond LaAlO directly to the Si substrate may become a problem in the future. For these reasons, direct bonding between an insulating film and a substrate that has a good interface, does not diffuse metal into the substrate, and relaxes the distortion of the substrate in the vicinity of the interface has not been realized so far.

  Furthermore, there is a problem in that a mixed layer is generated by inter-diffusion of both layers at the interface of the high dielectric film / metal gate electrode. For example, it has been reported that when a TiN electrode is formed on a HfSiON film, a reaction occurs at the interface, and EOT increases when heat treatment at 900 ° C. is performed, and leakage current increases at heat treatment at 1100 ° C. (non-patent document) Reference 3).

Further, even when different types of high dielectric films are laminated, there is a problem that a desired insulating film cannot be formed because both layers are inter-diffusion to form a mixed layer. For example, there is a report that the EOT becomes thicker in the HfTiSiO / SiO2 laminated structure than in the TiO2 / HfSiO / SiO2 laminated structure (see Non-Patent Document 4).
Y. Kamata et al., Jpn. J. Appl. Phys. 44, 2323 (2005). M. Suzuki et al., Tech. Dig.- Int. Electron Devices Meet. 2005, 445 (2005). H. Watanabe et al., “Thermal degradation of HfSiON dielectrics caused by TiN gate electrodes and its impact on electrical properties”, Jpn. J. Appl. Phys. 45, 2933 (2006). Arimura et al. "High performance of HfTiSiO high dielectric constant gate insulating film by structural optimization" Proceedings of the 54th Japan Society of Applied Physics related conferences 843 (Aoyama Gakuin University)

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device that improves the interface characteristics of an insulating film containing a metal element.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a structure in which a lower layer, a Ge layer, a Ge oxide layer, and an upper layer are stacked in this order, and a heat treatment to remove the Ge oxide layer and the Ge layer. And a step of directly joining the lower layer, and either the upper layer or the lower layer is formed of an insulator containing a metal element.

  An object of this invention is to provide the manufacturing method of the semiconductor device which improves the interface characteristic of the insulating film which has a metal element.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment, and the overlapping description is abbreviate | omitted. Each figure is a schematic diagram for promoting explanation and understanding of the invention, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, these are in consideration of the following explanation and known techniques. The design can be changed as appropriate.

(First embodiment)
The first embodiment relates to a method for manufacturing a semiconductor device in which a high dielectric film that easily forms an interface layer by reacting with an Si substrate is formed on the Si substrate without an interface layer. FIG. 1 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

  First, the Si substrate 1 is subjected to SC2 (HCl / H2O2 / H2O) cleaning, followed by HF treatment. Subsequently, the substrate is washed with pure water and dried, and then introduced into a film forming apparatus. A Ge layer 2 is deposited thereon by CVD (see FIG. 1 (a)). Subsequently, a high dielectric film having a metal such as Hf, Zr, or Y, for example, an HfO2 film 3 is deposited thereon by CVD (see FIG. 1B). Then, when the HfO2 film 3 is formed on the Ge layer 2, the Ge layer 2 and the HfO2 film 3 react to form the GeO2 layer 4 (see FIG. 1C). When the heat treatment is performed, the reaction shown in the formula (1) occurs, and the GeO2 layer 4 / Ge layer 2 reacts and is desorbed from the interface as GeO (gas), passes through the high dielectric film, and diffuses outward. By continuing the heat treatment, all GeO2 and Ge disappear as GeO (gas) (see FIG. 1 (d)). As a result, an HfO2 film 3 / Si substrate 1 direct junction without an interface layer is formed (see FIG. 1E).

GeO2 + Ge → 2GeO (gas) (1)
In the first embodiment, a two-layer structure of GeO2 layer 4 and Ge layer 2 is inserted on the lower layer (Si substrate 1), and the upper layer (HfO2 film 3) is formed without contacting the lower layer (Si substrate 1). The formation of the interface layer can be suppressed even with a high dielectric film that can be formed and easily reacts with the Si substrate. Thereafter, the inserted two-layer structure of GeO2 layer 4 and Ge layer 2 reacts and disappears using low-temperature heat treatment. With the disappearance of the GeO2 layer 4 and the Ge layer 2, the HfO2 film 3 descends, and an HfO2 film 3 / Si substrate 1 laminated structure having excellent interface characteristics can be formed. As described above, when the HfO2 film is directly deposited on the Si substrate, an interface layer is generated by oxygen in the film formation atmosphere. However, as in the first embodiment, the HfO2 film previously formed is formed. If the film and the Si substrate are bonded, an HfO2 / Si structure can be formed without generating an interface layer. Further, in this embodiment, since the GeO2 layer 4 is formed at the same time as the HfO2 film is deposited, the process is excellent.

  A modification of the first embodiment will be described. After the step shown in FIG. 1A, an Hf layer 6 is deposited by CVD (see FIG. 1F). Then, the Hf layer 6 is thermally oxidized to form the HfO 2 film 3. At that time, the Ge layer 2 is also oxidized to form a two-layer structure of the GeO2 layer 4 and the Ge layer (see FIG. 1G). Subsequent steps are as shown in FIGS. In this modification, since the two-layer structure of the GeO2 layer 4 and the Ge layer is formed at the same time in the process of oxidizing the Hf layer 5, the process is excellent. In this modification, only the Ge layer 2 is deposited on the substrate, but the Ge layer 2 and the GeO2 layer 4 may be sequentially deposited.

(Second Embodiment)
The second embodiment relates to a method of manufacturing a semiconductor device in which a high dielectric film that hardly reacts with an Si substrate to form an interface layer is formed on the Si substrate without an interface layer. FIG. 2 is a view for explaining the method for manufacturing the semiconductor device according to the second embodiment.

  First, the Si substrate 1 is subjected to SC2 (HCl / H2O2 / H2O) cleaning, followed by HF treatment. Subsequently, the substrate is washed with pure water and dried, and then introduced into a film forming apparatus. A Ge layer 2 is deposited thereon by CVD (see FIG. 2A). Then, a GeO2 layer 4 is formed on the Ge layer 2 by CVD (see FIG. 2B). At this time, the upper portion of the Ge layer 2 may be oxidized to form the GeO 2 layer 4. Subsequently, a LaAlO film 3 which is a high dielectric film is deposited thereon by CVD (see FIG. 2C). Then, the metal atoms 5 such as La and Al diffuse from the LaAlO film 3 in the direction of the Si substrate, but are taken into the amorphous GeO2 layer 4 so that the diffusion to the Si substrate 1 can be suppressed (see FIG. 2D). ). When heat treatment is performed, GeO2 reacts with Ge to become GeO (g), passes through the high dielectric film, and diffuses outward (see FIG. 2E). When the heat treatment is continued, all GeO2 and Ge disappear as GeO (g). During the heat treatment, since La and Al are taken into the GeO2 layer 4, they do not diffuse. When all GeO2 and Ge disappear as GeO (g), La and Al are left at the interface of the LaAlO / Si substrate and are eventually taken into the LaAlO film side. In this way, the LaAlO film 3 descends with the disappearance of the GeO2 layer 4 and the Ge layer 2, thereby forming a direct bonding of the LaAlO / Si substrate that suppresses the diffusion of La or Al and has no interface layer (FIG. 2). (Refer to (f)).

  In the second embodiment, since La and Al are not diffused in the Si substrate 1, the deterioration of mobility can be reduced. In addition, since the GeO2 layer 4 which is the lower layer at the time of forming the LaAlO film 3 of the second embodiment disappears and is joined to the Si substrate 1, the strain is relaxed more than that directly formed on the Si substrate 1, Therefore, the interface state can also be reduced.

  In addition, La2O3, CeO2 and the like are other examples of the high dielectric film that hardly reacts with the Si substrate to form the interface layer.

(Third embodiment)
The third embodiment relates to a method for manufacturing a semiconductor device in which a metal electrode is directly formed on an insulating film having metal. FIG. 3 is a view for explaining the method for manufacturing the semiconductor device according to the third embodiment.

  First, an HfSiON film 3 that is a high dielectric film is formed on a Si substrate or the like (not shown). A Ge layer 2 and a GeO 2 layer 4 are sequentially deposited thereon by CVD (see FIG. 3A). Subsequently, a TiN electrode 6 is deposited thereon by CVD (see FIGS. 3B and 3C). When the heat treatment is performed, the reaction shown in the formula (1) occurs, and the GeO2 layer 4 / Ge layer 2 reacts and is desorbed from the interface as GeO (gas), passes through the TiN electrode 6, and diffuses outward. By continuing the heat treatment, all GeO2 and Ge disappear as GeO (gas) (see FIG. 3D). As a result, a TiN / HfSiON direct bond without a reaction layer is formed (see FIG. 3E).

  According to the third embodiment, the TiN / HfSiON structure has no mixed layer, and Ti, N, etc. are diffused in the HfSiON film, and the leakage current is not increased. Therefore, it is possible to reduce mobility degradation due to remote Coulomb scattering. If a TiN electrode is formed on the HfSiON film, a mixed layer is generated by reaction at the time of film formation. However, as in the third embodiment, the TiN electrode and the HfSiON film formed in advance are formed. If it contacts, a mixed layer will not arise.

(Fourth embodiment)
The fourth embodiment relates to a method for manufacturing a semiconductor device in which a laminated structure of insulating films having different metals is formed. FIG. 4 is a view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment.

  First, an HfSiON film 3a that is a high dielectric film is formed on a Si substrate or the like (not shown). A Ge layer 2 is deposited thereon by CVD (see FIG. 4A). Alternatively, the GeO 2 layer 4 may be formed on the Ge layer 2 at this time. Subsequently, a ZrO2 film 3b is deposited thereon by CVD (see FIG. 4B). Then, the Ge layer 2 reacts with the ZrO2 film 3b, and the Ge layer 2 has a two-layer structure of the GeO2 layer 4 and the Ge layer 2 (see FIG. 4C). When the heat treatment is performed, the reaction shown in the formula (1) occurs, and the GeO2 layer 4 / Ge layer 2 reacts and desorbs from the interface as GeO (gas), passes through the ZrO2 film 3b, and diffuses outward. By continuing the heat treatment, all GeO2 and Ge disappear as GeO (gas) (see FIG. 4D). As a result, a ZrO2 / HfSiO laminated structure of different insulating films without a reaction layer is formed (see FIG. 4E).

  The laminated structure of the different kinds of insulating films thus formed did not cause mutual diffusion, and a desired insulating film having a flat interface could be formed. As a result, unexpected problems such as an increase in EOT and an increase in leakage current are unlikely to occur. Therefore, an insulating film structure satisfying both a desirable EOT and a physical film thickness can be easily realized by considering the dielectric constants and physical film thicknesses of the different insulating films. Usually, when different types of insulating films are sequentially formed and stacked, a mixed layer is generated. However, in the fourth embodiment, there is no mixing of films during film formation, and there is no oxidation or the like during film formation. For this reason, even if the insulating films formed in advance are in contact with each other, a mixed layer is not generated, and a change in composition at the insulating film interface can be suppressed. In the future, not only the film thickness direction but also the film area will be scaled. For this reason, if the insulating film is too thick from the viewpoint of aspect ratio, there is a problem in actual fabrication. For this reason, it is preferable that the insulating film is easily adjusted in physical film thickness in order to increase the aspect ratio while ensuring a sufficient thickness to suppress leakage current. The laminated film of the fourth embodiment is preferable in that it can easily provide a desired laminated structure of different kinds of insulating films.

  In the fourth embodiment, only the Ge layer 2 is deposited on the HfSiON film 3a. However, the Ge layer 2 and the GeO2 layer 4 may be sequentially deposited.

(Fifth embodiment)
In the fifth embodiment, the reaction between the GeO2 layer 4 and the Ge layer 2 described in the first to fourth embodiments will be described in more detail. For convenience, the first embodiment will be described as an example, but the same applies to the second to fourth embodiments.

  The physical film thickness T2 of the Ge layer 2 to be deposited is defined by the physical film thickness T4 of the typical GeO2 layer 4 formed when the upper layer (HfO2 film 3) is deposited on the Ge layer 2 and the respective number density. be able to. The GeO2 layer 4 and Ge layer 2 undergo the reaction shown in the formula (1). Therefore, in order to eliminate all of GeO2 layer 4 and Ge layer 2 as GeO (gas), the atomic fraction of O and Ge in the entire structure of GeO2 layer 4 / Ge layer 2 should be close to the relationship of equation (2). Is desirable.

[O] / [Ge] = 1 (2)
Here, [O] and [Ge] are atomic fractions of O (oxygen) and Ge, respectively, and are normalized by the equation (3).

[O] + [Ge] = 100 (at.%) (3)
Further, GeO2 layer 4 and Ge layer 2 are uniform in each layer, and the number of GeO2 and Ge per unit volume in each layer is N4 and N2, respectively.
N2 T2 = N4 T4 (4)
When satisfying the condition, all of the respective layers will react according to the formula (1), so that the interface layer can be removed most ideally. Here, N2 is 4.42x10 ^ 22 (cm ^ -3) when Ge is a single crystal (note that the basic physical properties are mainly SM Sze, Physics of Semiconductor Devices, 2nd Ed. (Wiley- Based on Interscience, New York, 1981. N4 takes various values depending on the reaction conditions, so even if [O] / [Ge] is less than 1, that is, GeO (gas The amount of Ge may be larger than the amount disappeared as) .If [O] is supplied by performing oxidation during thermal oxidation, the equation (2) can be easily satisfied. As the ratio of atomic fraction of O and Ge,
[O] / [Ge] ≤ 1 (5)
It is a condition to satisfy. However, it is desirable that [O] / [Ge] is close to 1. The required Ge layer thickness T2 can be obtained from Equations (3)-(5) if the typical interface layer thickness T4 determined by the upper layer (HfO2 film 3) and the GeO2 density N4 are known. Desired.

  Next, the heat treatment temperature for causing the reaction of the formula (1) between the GeO2 layer 4 and the Ge layer 2 will be described. First of all, the heat treatment must be performed at a temperature lower than at least the melting point of Ge, 938 ° C. More practically, the upper limit is lower than the temperature at which the upper layer and the lower layer start to react with GeO 2 layer 4, Ge layer 2, heat treatment atmosphere gas, and the like. For example, when heat treatment is performed in an oxygen-containing atmosphere using a Si layer terminated with hydrogen as the lower layer, the temperature needs to be lower than the temperature at which Si starts to oxidize, which is 700 ° C. Further, even materials generally used in semiconductor devices are hardly reacted at about 700 ° C. or lower, and preferably 700 ° C. or lower.

  On the other hand, the lower limit of the heat treatment temperature for causing the reaction of the formula (1) is 350 ° C. The experimental results showing this will be described in detail. First, Au was thermally deposited on a Ge substrate through a metal mask to form a circular pattern. Then, heat treatment was performed at 350 ° C. for 30 minutes in an atmosphere of 5% H2 / N2. FIGS. 5A and 5B are obtained by examining the Au after the heat treatment with an optical microscope. In FIG. 5 (a), the area of the largest circular pattern is 1 mm ^ 2, and FIG. 5 (b) is an enlargement of FIG. 5 (a) 20 times. As shown in FIGS. 5A and 5B, Au was uniformly formed in a circular shape before the heat treatment, but almost disappeared from the Ge substrate after the heat treatment. For comparison, the same experiment was performed on the Si substrate, but in that case, Au did not disappear (see FIGS. 5C and 5D). Therefore, this phenomenon is not caused by the characteristics of Au, but is caused by the difference between Si and Ge. This is presumably because GeO2 present at the interface between Au and the Ge substrate was detached by causing a reaction of the formula (1) with the Ge substrate. Note that since the Au formed at this time had low reactivity with the substrate and was easily peeled off, it is considered that both GeO (g) were detached from the Ge substrate.

  The fact that the Ge reaction layer and Ge layer formed on the lower layer other than Ge can be removed at a low temperature of 350 ° C. is an excellent point of this embodiment. This is because it is difficult to prevent the reaction layer between the upper layer and the lower layer if the lower layer is oxidized to remove the Ge layer. At a temperature of 350 ° C, the lower layer is not oxidized in most cases. For example, when the lower layer is a Si substrate, the heat treatment at 350 ° C. works only to remove the Ge reaction layer and the Ge layer, and does not cause oxidation of the Si substrate.

  From the above, the temperature of the heat treatment can be less than 938 ° C., and is desirably 350 ° C. or a temperature close thereto.

(Sixth embodiment)
In the sixth embodiment, the upper layer and the lower layer described above in the first to fourth embodiments will be described in more detail.

  In the first to fourth embodiments, GeO (gas) has been shown as an example of outward diffusion through a high dielectric film, an electrode, and a substrate. However, if the Ge oxide layer 4 and the Ge layer 2 are removed, all of GeO (gas) may be taken into these films without passing through. Even if incorporated, the semiconductor property is maintained in the substrate, and the conductivity is not deteriorated in the electrode.

  In the case of a high dielectric film, it can be classified into a film that does not have an electrical influence even if Ge enters the film, and a film that cannot be kept insulating as it is.

  As a simple example, the case where HfO2 is deposited on Si and Ge will be described. In the case of Ge over H over Si, HfO2 causes significant electrical characteristics degradation such as increased leakage current and CV hysteresis. According to our calculation by the first-principles spin-polarized nonlocal approximate density functional theory (SP-GGA-DFT method: Spin-Polarized Generalized Gradient Approximation Density Functional Theory), the cause is that Si or Ge occupies the Hf substitution site This is to cause such defects. In the case of Si, no defect level occurs in the gap, as expected from replacing tetravalent Hf with the same tetravalent Si. However, in the case of Ge with the same tetravalence, an unoccupied “shallow” defect level appears near the conduction band in the gap. As a result of investigating the wave function of this defect level in the case of Ge and the corresponding wave function in the case of Si, in Si, the level stuck to the bottom of the conduction band and the defect in the gap of Ge It was found that the levels corresponded. Since Si sticks to the bottom of the conduction band, it is mixed with the expanded orbit caused by the Hf 5d orbit that forms the vicinity of the bottom of the conduction band. However, in Ge, this mixing does not occur, so it falls in the gap. As a result of examining the electron density distribution around Ge and Si in detail, it was found that this level is an antibonding orbital caused by sp orbits extending from Ge or Si in the direction of oxygen.

  Therefore, the upper layer composed of other elements can also be classified as to whether there is an influence when Ge is contained depending on the ease of orbital hybridization with Ge4p orbitals that are Ge valence orbitals. Assuming that the spatial distortion is sufficiently relaxed, the ease of orbital hybridization is considered in terms of atomic orbital energy.

  Yttria (Y2O3) on a Ge substrate as reported in the literature “Chokai, Applied Physics, 1453 (2006)” and the literature “Y. Kamata et al., 2007 MRS Spring Meeting, G4.2 (2007)”. When zirconia (ZrO2) is deposited, significant electrical property degradation such as increased leakage current and CV hysteresis does not occur even if Ge diffuses in the film, but degradation occurs in hafnia (HfO2). Considering these experimental results in yttria, zirconia, and hafnia, when there is no valence level occupied by multiple electrons at a position that is shallower than 1.3eV (ie, closer to the vacuum level) from the Ge4p orbital Has sufficient orbital hybridization and no levels in the gap. Conversely, it was found that when multiple electrons occupy the valence level at that position, the orbital hybridization becomes insufficient and a level in the gap occurs.

  Therefore, we calculated the atomic orbital energy for various atoms by SP-GGA-DFT method. A part thereof is shown in FIG. FIG. 6 shows the atomic orbital energy of O, Si, Ge, Y, Zr, La, and Hf. In Zr, two electrons in 5s and two electrons in 4d are both within 1eV from Ge4p, so orbital hybridization occurs sufficiently and no level in gap is generated. In Y, there is only one 4d electron that is shallower than this range, so orbital hybridization occurs, and the level in gap does not occur. On the other hand, in Hf, two of 6s are deeper than Ge4p, but two electrons of 5d are shallower than this range, so orbital hybridization becomes insufficient and a level in gap occurs. Since La 6s and 1d 5d are distributed around 1eV from Ge4p, orbital hybridization occurs sufficiently, and the level in gap does not occur.

  According to this standard, constituent elements assumed as oxides, oxynitrides, oxyfluorides, or composites thereof are classified as follows. Li, Na, K, Rb, Cs, B, Al, S, Ga as elements that can be put in a class that provides good electrical properties without special post-treatment even if Ge is incorporated into the film , As, Se, In, Sn, Sb, Te, Tl, Pb, Bi, Po, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Nb, Mo, La, Gd , Ta, W, Re, Os, Pt, Ce, Sm, Eu. On the other hand, when Ge is incorporated into the film, the elements that can be put into the classification where an electronic defect occurs in the oxide are Tc, Ru, Rh, Pd, Pt, Lu, Hf, Pr, Nd, Pm, Tb, Cy, Er, Tm, Ho are mentioned.

  In addition, when an oxide, oxynitride, oxyfluoride, or a composite thereof containing an element easily mixed with orbital as a main constituent element is used in the upper layer of Ge, a special post-treatment process is not required. Does not affect the electrical characteristics. As will be described below, in the case of an upper layer made of an element with insufficient orbital hybridization, an electronic defect is generated as it is, but a post-processing step (oxidation / nitridation) for compensating for excess electrons caused by the defect. ) Can be completely inactivated electrically. The post-treatment is preferably oxidation rather than nitriding.

  Hereinafter, in the case of hafnia (HfO2), the results clarified by our SP-GGA-DFT method calculation will be described with reference to FIG.

  Ge has a lower heat of cohesion and interstitial heat than Si, and Ge can be easily generated. The characteristics of Ge diffusing from this Ge source into HfO2 are listed below. The parenthesized numbers listed correspond to the circled numbers in FIG.

FIG. 7A is a diagram showing the Fermi level dependence of the generated energy. Here, the chemical potential μ _Ge of _Ge is assumed to be a value μ _Ge (bulk) in crystalline Ge assuming a Ge substrate / High-k interface. The chemical potential μ _O of oxygen was set to 1/2 μ _{O 2 which} is half the value of oxygen molecules in consideration of an oxygen-rich situation where oxygen is sufficiently supplied. The band gap Eg: 4.48 eV obtained by calculation was adopted as the energy of the conduction band bottom CBM measured from the valence band top VBM of hafnia. This value is about 1.2 eV smaller than the actually measured value of 5.68 eV. However, it is theoretically proved that the band gap is underestimated from the actually measured value within the theoretical framework of the first principle band calculation used in the present embodiment. The correction method is also shown theoretically. However, since correction requires enormous calculation, it is not implemented. Ge alone (interstitial germanium (Ge _i )) has a high heat of formation and is difficult to dissolve in HfO 2 (see number 1). Interstitial GeO ((GeO) _i ) reduces the heat of formation and facilitates diffusion in HfO 2 (see circled numeral 2). In terms of electronic structure, interstitial GeO is not in a state where neutral Gei (0) and Oi (0) are pushed into the HfO2 lattice, but dissociated into Ge _i ²⁺ and O _i ^2- Take a state. The so-called interstitialcy mechanism in which O _i ²⁻ thus produced extrudes lattice oxygen and the extruded oxygen becomes new O _i ²⁻ becomes easy to diffuse. Accordingly, Gei (2+) as an ionic defect pair is also easily diffused. The Fermi level dependence of the charge states of Ge _i and (GeO) _i both exhibit “negative U” behavior, and both are extremely active against hole trapping as they are (see circled number 3). Originally, when two electrons enter a certain level (injection of electrons), energy loss should occur due to Coulomb repulsion (Charging Energy) between the electrons. However, if the gain of Coulomb energy due to the large lattice relaxation caused by electron injection exceeds the repulsive force between electrons, it is advantageous to have two electrons in a certain level. This is called “negative U” behavior.

  Therefore, we compared the electronic state of hafnia containing Ge with that of nitrogen or oxygen. FIG. 7B is a diagram showing electronic states in hafnia for atoms in various states, with the electron energy on the horizontal axis and the state density on the vertical axis. VB (HfO2) is the valence band of hafnia, CB (HfO2) is the conduction band of hafnia, VBM (Si) is the top of the valence band of silicon, CBM (Si) is the bottom of the conduction band of silicon, and the black arrow is the occupied level A white arrow indicates an unoccupied level. Further, (GeO) i-2No indicates a structure in which interstitial GeO ((GeO) i) and two oxygen-substituted nitrogen (No) form a “pair” and are completely charge compensated. Gei-4No indicates a structure in which interstitial Ge (Gei) and four oxygen-replaced nitrogen (No) form a “pair” and are completely charge compensated. No (3) represents nitrogen substituted for tricoordinate oxygen (O (3)) in monoclinic HfO2. Gei-2Oi shows a structure in which two interstitial Ge (Gei) and two interstitial oxygen (Oi) form a “pair” and are completely charge compensated. Gei-1No, Gei-2No, and Gei-1Oi show structures in which charge compensation is incomplete and occupied levels due to surplus electrons remain in the gap. Perfect shows perfect monoclinic HfO2 without defects.

When Ge _i and (GeO) _i form “pairs” with oxygen-substituted nitrogen (N _O ) (1 to 4), they go to electrical deactivation (see circled numeral 4). However, care must be taken because it causes an unoccupied level immediately above the upper end of the valence band and directly below the lower end of the conduction band. On the other hand, the oxygen (O _i) and the "pair" formed (Ge _i -2O _i), the excess electrons of Ge _i is fully compensated, yet without forming a unoccupied levels just below the conduction band minimum non Can be activated (see number 5). For this reason, it can be understood that the deterioration of the electrical characteristics caused by mixing of Ge can be eliminated by introducing oxygen or nitrogen, and it is more preferable to introduce oxygen.

(Seventh embodiment)
In the seventh embodiment, a method of manufacturing a CMOSFET to which the first to fourth embodiments are applied, particularly a gate first process will be described. Here, for the sake of convenience, description will be made using an example in which the high dielectric film of the first and third embodiments is a gate insulating film, but of course, the second and fourth embodiments can be similarly applied.

  As shown in FIG. 8, an element isolation layer 7 is formed on the silicon substrate 1. The element isolation layer 7 may use a local oxidation method, an STI (Shallow Trench Isolation) method, or may be a mesa type. After the element isolation layer 7 is formed, a p-type well region 8 and an n-type well region 9 are respectively formed by normal ion implantation. Subsequently, the natural oxide film on the surface of the silicon substrate including the element isolation layer 7 and the well regions 8 and 9 is removed by normal wet etching, and then immediately transferred to the film forming apparatus.

  Here, as described in the first embodiment, a high dielectric film such as an amorphous HfO 2 film, a GeO 2 layer, and a Ge layer are formed on the Si substrate 1. Thereafter, the GeO 2 layer and the Ge layer disappear by low-temperature annealing, so that the gate insulating films 10 and 11 can be formed without an interface layer. In addition, if a high dielectric film is deposited after forming a Ge layer only in one of the p-type well 8 or the n-type well 9, the laminated structure of the high dielectric and the substrate 1 may or may not have an interface layer. Can be made.

  Thereafter, by using the method described in the third embodiment, a single-layer or multi-layer conductive film serving as a gate electrode can be formed on the gate insulating films 10 and 11 without an interface layer. Here, for example, a tantalum carbide film for an n-channel MIS transistor and a tungsten film for a p-MISFET are formed to a thickness of 10 nm by CVD, a titanium nitride film is formed to a thickness of 10 nm by CVD, and a polycrystalline silicon film is formed thereon. The layer is deposited to 50 nm by low pressure CVD.

  For the conductive film for n-MISFET, tantalum silicide, tantalum nitride silicide, titanium nitride silicide, tungsten silicide, tungsten nitride silicide, or the like can be used. Further, for the p-MISFET conductive film, ruthenium, titanium nitride, titanium aluminum nitride, platinum, platinum iridium, or the like can be used.

  Subsequently, patterning is performed by a photolithography technique, unnecessary films are removed by anisotropic etching, and gate electrodes 12 and 13 are formed, respectively. Further, shallow extension layers 14 and 15 of high impurity concentration of n- and p-MISFETs are formed by ion implantation of phosphorus and boron in a self-aligning manner using the gate electrodes 12 and 13. For the formation of the extension layers 14 and 15, an elevated source / drain structure that can suppress the short channel effect as a device characteristic using a selective epitaxial growth method may be used. Further, impurities may be introduced simultaneously with the formation of the elevated source / drain structure.

  Next, side walls 16 and 17 for insulating the gate electrodes 12 and 13 and the source / drain regions (extension layers 14 and 15 and deep diffusion layers 18 and 19) are formed. Phosphorus and boron ions are implanted at a higher acceleration voltage than in the case of the extension layers 14 and 15, and the deep diffusion layers 18 and 19 are formed. In the steps so far, the source / drain activation process temperature is, for example, a temperature at which the HfO 2 films 10 and 11 as the gate insulating films are not crystallized, for example, 900 ° C.

  As the activation process conditions for the source / drain regions, flash lamp annealing, laser annealing, or the like can be used. According to these, since the activation of impurities in the semiconductor can be realized in a shorter time, it becomes easy to maintain the heat resistance of the gate electrode / insulating film / semiconductor structure.

Thereafter, a silicon oxide film to be an interlayer insulating film 20 is deposited by low pressure CVD, and the upper end of the gate electrode is exposed by CMP (chemical mechanical planarization), and then a nickel layer is formed to a thickness of 50 nm by a sputtering method or the like. Thereafter, by performing a low-temperature heat treatment at 500 ° C., silicide is formed from the interface region between nickel and polycrystalline Si to form Ni ₂ Si. Here, in this embodiment, all the polycrystalline Si is converted into silicide. Of course, a part of the polycrystalline Si may be silicidized by making the Ni film thinner. Thereafter, unreacted Ni is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution.

  Through the manufacturing process described above, the CMOSFET semiconductor device having the structure shown in FIG. 8 can be manufactured. In the structure of the semiconductor device of the seventh embodiment, the gate insulating film 10 and the p-type well region 8 and the gate insulating film 11 and the n-type well region 9 are in direct contact with no interfacial low dielectric constant layer interposed therebetween. Further, the gate insulating film 10 and the gate electrode 12, and the gate insulating film 11 and the gate electrode 13 are in direct contact with no interfacial low dielectric constant layer interposed therebetween. For this reason, it is possible to set the insulating film capacitance to an extremely high value, and the current driving capability of the transistor is increased.

(Eighth embodiment)
In the eighth embodiment, a method of manufacturing a CMOSFET to which the first to fourth embodiments are applied, particularly a replacement gate process will be described. Here, for the sake of convenience, description will be made using an example in which the high dielectric film of the first and third embodiments is a gate insulating film, but of course, the second and fourth embodiments can be similarly applied.

  In the seventh embodiment described above, the semiconductor device having the structure shown in FIG. 8 is manufactured by using the process of forming the source / drain regions by introducing impurities after processing the gate insulating film and the gate electrode. On the other hand, in the eighth embodiment, source / drain regions are formed in a self-aligned manner using a dummy gate made of polycrystalline silicon or the like. At this time, the source / drain regions are formed at a high temperature of 1000 ° C. or higher. Thereafter, the dummy gate is removed by an existing manufacturing method such as wet etching or dry etching (see FIG. 9).

  Here, as described in the first and third embodiments, the gate insulating film and the gate electrode are formed in the groove 21 formed after the dummy gate is removed without forming a reaction layer at the interface. Form. For example, an HfO 2 film is formed as a high dielectric film, a Ge layer 2 and a GeO 2 layer 4 are sequentially deposited, a gate electrode is deposited, and then the Ge layer 2 and the GeO 2 layer 4 are removed by annealing. The n-MISFET is formed with an n-MISFET gate electrode 12, for example, hafnium silicide to which nitrogen is added, and the p-MISFET is formed with a p-MISFET gate electrode 13, for example, nickel-rich nickel silicide.

  In addition, n-MISFET gate electrodes include rare earth metal silicides (hafnium silicide, erbium, yttrium, etc.), metal silicides (titanium silicide, zirconium, tantalum, etc.), and metal nitrides with nitrogen added to metal silicides. Silicide, tantalum carbide / tantalum nitride, and alloys obtained by adding a rare earth metal such as erbium to these can be used.

  In addition, the gate electrode of the p-MISFET includes a platinum group element (platinum, iridium, ruthenium, palladium, osmium, etc.), an alloy of platinum group elements or silicide, ruthenium, an oxide of iridium, SrRuO, gold, silver, Titanium aluminum nitride, tungsten and its nitride, molybdenum and its nitride or oxide can be used.

  Further, a metal thin film such as tungsten is deposited on the entire surface with good coverage by, for example, the CVD method. Thereafter, the device is planarized by CMP or the like, whereby a CMOSFET can be obtained.

  In the eighth embodiment, after the gate electrode / gate insulating film interface is formed, there is no high-temperature step reaching about 1000 ° C., and only a thermal process of 500 ° C. or lower is required. Therefore, there is less concern about the thermal stability of both structures, and a metal material that can withstand about 500 ° C., such as nitrogen-added hafnium silicide, nickel-rich nickel silicide, or the like can be used. Since these materials have a work function close to the silicon band edge, the threshold voltage of the transistor can be lowered. That is, in the eighth embodiment, it is possible to use these low threshold gate electrode materials without fear of a fundamental heat resistance failure.

(Ninth embodiment)
In the ninth embodiment, a method for manufacturing an FG type nonvolatile memory to which the first to fourth embodiments are applied will be described with reference to FIGS. The left and right drawings in FIGS. 10A to 10E show cross sections orthogonal to each other. Here, for the sake of convenience, description will be made using an example in which the high dielectric film of the first embodiment is a gate insulating film, but of course, the second to fourth embodiments can be similarly applied.

  First, as shown in FIG. 10 (a), as described in the first embodiment, a reaction layer is not formed on the surface of a p-type silicon substrate 1 doped with a desired impurity. A tunnel film 24 can be formed on the Si substrate 1. For example, since the GeO2 layer and the Ge layer disappear by performing low-temperature annealing after forming a stacked structure of a Si substrate, a Ge layer, a GeO2 layer, and an HfO2 film, an HfO2 / Si substrate structure can be formed without an interface layer.

  Subsequently, a floating gate electrode (phosphorus-doped crystalline silicon layer) 23 having a thickness of 60 nm to be a floating gate electrode is deposited by a CVD (chemical vapor deposition) method.

  Thereafter, the mask material 22, the floating gate electrode 23, and the tunnel insulating film 24 are sequentially etched by a reactive ion etching (RIE) method using a resist mask (not shown). The exposed region is etched to form an element isolation trench having a depth of 100 nm.

  Next, as shown in FIG. 10B, a silicon oxide film 26 for element isolation is deposited on the entire surface to completely fill the element isolation trench. Thereafter, the silicon oxide film 26 on the surface portion is removed by a CMP (chemical mechanical polishing) method to planarize the surface. At this time, the upper surface of the silicon nitride film 22 as a mask material is exposed. Next, the exposed mask material 22 is selectively removed by etching, and then the exposed surface of the silicon oxide film 7 is removed by etching with a diluted hydrofluoric acid solution or the like to expose the side wall surface of the floating gate electrode 23.

  Next, as shown in FIG. 10C, a high dielectric film is formed without an interface layer as the interelectrode insulating film 27 by the method described in the first embodiment. For example, a stacked structure of a floating gate electrode (phosphorus-doped crystalline silicon layer) 23, a Ge layer, a GeO2 layer, and an HfAlO film is formed, and the GeO2 layer and the Ge layer are eliminated by low-temperature annealing.

Next, as shown in FIG. 10D, a phosphorus-doped n ⁺ -type polycrystalline silicon layer 28 is deposited by CVD at 620 ° C. as a control gate electrode, and a tungsten silicide (WSi) layer 29 is formed thereon. By forming, a conductive layer having a two-layer structure of WSi layer / polycrystalline Si layer and having a thickness of 100 nm is formed. Here, the WSi layer 29 is formed by depositing W using a CVD method using W (CO) ₆ as a source gas and converting the polycrystalline silicon layer into WSix in a subsequent thermal process.

  Note that the manufacturing method of these films is not limited to the method shown here, and other source gases may be used. In addition to ALD and CVD methods, for example, sputtering, vapor deposition, laser ablation, MBE, and film formation methods combining these methods are also possible.

  Thereafter, the WSi layer 29, the polycrystalline silicon layer 28, the tunnel film 27, the single crystal silicon floating gate electrode 23b, and the tunnel insulating film 24 are sequentially etched by the RIE method using a resist mask (not shown) to form the word A slit portion in the linear direction is formed. Thereby, the shapes of the floating gate electrode and the control gate electrode are determined.

Finally, as shown in FIG. 10E, a silicon oxide film 30 called an electrode side wall oxide film is formed on the exposed surface by a thermal oxidation method, and then an n-type ⁺ source / drain diffusion layer 31 is used by an ion implantation method. Form. Further, an interlayer insulating film 32 such as a silicon oxide film is formed by a CVD method so as to cover the entire surface. Thereafter, a wiring layer or the like is formed by a well-known method to complete the nonvolatile memory cell.

(Tenth embodiment)
In the tenth embodiment, a method of manufacturing a SONOS type nonvolatile memory to which the first to fourth embodiments are applied will be described with reference to FIGS. The left and right drawings in FIGS. 11A to 11E show cross sections orthogonal to each other. Here, for the sake of convenience, description will be made using an example in which the high dielectric film of the first embodiment is a gate insulating film, but of course, the second to fourth embodiments can be similarly applied.

  First, as shown in FIG. 11A, a tunnel insulating film 34 of a high dielectric film is formed on the surface of a p-type Si substrate 1 doped with a desired impurity by using the method described in the first embodiment. Can be formed without an interface layer. In order from the top, a high-dielectric film such as a HfAlO film, a GeO2 layer, a Ge layer, and a Si substrate 1 are formed and annealed at a low temperature to eliminate the GeO2 layer and the Ge layer.

Subsequently, a silicon nitride film 33 having a thickness of 60 nm serving as a charge storage layer is deposited by a CVD (chemical vapor deposition) method. The gas used at this time is, for example, dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ), or hexachlorodisilane (Si ₂ Cl ₆ ) and ammonia (NH ₃ ), and the film formation temperature is about 450 ° C. To 800 ° C.

  Thereafter, the silicon nitride film 33 and the tunnel insulating film 34, which are charge storage layers, are sequentially etched by RIE using a resist mask (not shown), and the exposed region of the Si substrate 1 is further etched to obtain a depth. A 100 nm isolation trench is formed.

  Next, as shown in FIG. 11B, a silicon oxide film 26 for element isolation is deposited on the entire surface to completely fill the element isolation trench. Thereafter, the silicon oxide film 26 on the surface portion is removed by a CMP method to planarize the surface. At this time, the upper surface of the silicon nitride film 33 is exposed.

  Next, as shown in FIG. 11C, the exposed surface of the silicon oxide film 26 is etched away with a dilute hydrofluoric acid solution to expose the side wall surface of the silicon nitride film 33. Thereafter, a 15 nm thick HfAlO film to be the block insulating film 35 is formed on the entire surface by the method described in the first embodiment. In the embodiment, the base is a Si substrate, but a SiN film is also applicable. If the surface is oxidized during film formation, the film becomes a SiON film and the charge retention characteristics deteriorate. However, if the method of the first embodiment is used, an HfAlO film can be formed thereon while maintaining the characteristics of the SiN film. Here, in the present embodiment, the surface of the element isolation silicon oxide film 26 is slightly etched to use a structure in which the block insulating film 35 has a step, but this is not a limitation. The block insulating film 35 may be configured to be flat, and this can be selected according to a desired capacitance ratio between the tunnel insulating film and the charge storage layer.

Next, a phosphorus-doped n ⁺ -type silicon layer 28 is deposited by CVD at 420 ° C. as a control gate electrode, and a WSi layer 29 is formed thereon to form two layers of WSi layer 29 / silicon layer 28. An electrode layer having a structure thickness of 100 nm is formed. Here, the WSi layer 29 is formed by depositing W using a CVD method using W (CO) ₆ as a source gas and converting the polycrystalline silicon layer into WSix in a subsequent thermal process.

  Note that the manufacturing method of these films is not limited to the method shown here, and other source gases may be used. In addition to ALD and CVD methods, for example, sputtering, vapor deposition, laser ablation, MBE, and film formation methods combining these methods are also possible.

  Subsequently, a silicon nitride film 22 serving as a mask material is deposited on the WSi layer serving as the control gate electrode. Thereafter, the silicon nitride film 22, the WSi layer 29, the amorphous silicon layer 28, the HfAlOx film as the block layer 35, and the silicon nitride film layer as the charge storage layer 33 are formed by RIE using a resist mask (not shown). Then, the SiON film as the tunnel insulating film 34 is sequentially etched to form a slit portion in the word line direction as shown in FIG.

Finally, as shown in FIG. 11E, a silicon oxide film 30 called an electrode sidewall oxide film is formed on the exposed surface by a thermal oxidation method, and then an n ⁺ type source / drain diffusion layer 31 is formed by using an ion implantation method. Form. Further, an interlayer insulating film 32 such as a silicon oxide film is formed by a CVD method so as to cover the entire surface. Thereafter, a wiring layer and the like are formed by a well-known method to complete the SONOS type nonvolatile memory cell.

  As described above, in each embodiment, an example of an HfAlO film, an HfSiON film, an HfO2 film, etc. as an insulating film, an TiN, TaC, etc. as an electrode, and an Si substrate as a substrate has been shown, but this embodiment is limited to those materials is not. The present invention can be applied to all cases in which a reaction occurs between the insulating film, the substrate, and the electrode, or an element constituting the insulating film diffuses into the substrate. For example, the substrate may be Si, SixGe1-x (1 ≧ x> 0), a III-V group compound, or the like. For example, the electrodes include metals such as Mo, Al, Ti, Ta, Au, Pt, and W, conductive metal nitrides such as TiN and TaN, conductive metal carbides such as TaC, and conductive metals such as NiSi and PtSi. Binary compounds such as silicide, conductive oxide germanide such as RuO, ternary compounds such as TiAlN and TaAlN, and compounds containing higher elements may be used as long as they have low conductivity. A laminated structure or a multilayer structure thereof may be used.

  Further, the chemical composition of the GeO2 layer 4 and the HfO2 film 3 has been described using the stoichiometric ratio in the present embodiment, but it is of course possible to adopt a non-stoichiometric ratio such as an oxygen deficient type.

  Further, for example, the present invention can be applied to combinations of different types such as an insulating film and an insulating film, an electrode and an electrode, and two or more kinds of combinations such as an electrode, an insulating film, and a substrate are also possible. The insulating film and the electrode may be formed by CVD or sputtering.

  It can also be applied to SOI (silicon on insulator) structures and vertical transistor structures.

  Further, as described in the CMOSFET manufacturing method of the seventh embodiment, the reacted Ge may be deposited on the entire underlying surface or may be selectively deposited. Furthermore, this is not limited to CMOSFETs. In general, if a high dielectric film is deposited after forming a region with and without Ge on a substrate, it is possible to make a layered structure of a high dielectric and a substrate with or without an interface layer.

  As mentioned above, although embodiment of this invention was described, this invention is not restricted to these, In the category of the summary of the invention as described in a claim, it can change variously. In addition, the present invention can be variously modified without departing from the scope of the invention in the implementation stage. Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment.

Cross-sectional schematic diagram for explaining the first embodiment and its modifications Cross-sectional schematic diagram for explaining the second embodiment Cross-sectional schematic diagram for explaining the third embodiment Cross-sectional schematic diagram for explaining a fourth embodiment Optical micrographs of heat-treated (a), (b) Au / Ge structures and (c), (d) Au / Si structures. Energy level diagram of various elements Diagram showing electronic states of Ge, etc. in hafnia Sectional schematic diagram for demonstrating CMOSFET of 7th Embodiment Sectional schematic diagram for demonstrating CMOSFET of 8th Embodiment Sectional schematic diagram for demonstrating FG type memory of 9th Embodiment Sectional schematic diagram for explaining a SONOS type memory according to the tenth embodiment

Explanation of symbols

1 Si substrate
2 Ge layer
3, 3a, 3b High dielectric film
4 GeO2 layer (Ge reaction layer)
5 metal atoms
6 Metal layer
7 element isolation
8 p-type well
9 n-type well
10, 11 Gate insulation film
12, 13 Gate electrode
14, 15 Shallow extension layer
16, 17 sidewall
18, 19 Deep diffusion layer
20 Interlayer insulation film
21 groove
22 Mask material
23 Floating electrode
24 Tunnel insulation film
26 Silicon oxide film
27 Interelectrode insulation film
28 Control electrode
29 WSi layer
30 Interelectrode sidewall oxide film
31 Source / drain diffusion layers
32 Interlayer insulation film
33 Silicon nitride film
34 Tunnel insulation film
35 Block layer (HfAlO film)

Claims (7)

Forming a structure in which a lower layer, a Ge layer, a Ge oxide layer, and an upper layer are stacked in this order;
Removing the Ge oxide layer and the Ge layer using heat treatment, and directly bonding the upper layer and the lower layer,
Either of the upper layer and the lower layer is formed of an insulator containing a metal element. One of the upper layer and the lower layer is formed of an insulator having the metal element, and the other is formed of one of Si, SixGe1-x (1 ≧ x> 0), and a III-V group compound. A method for manufacturing a semiconductor device according to claim 1. One of the upper layer and the lower layer is formed of any one of metal, conductive metal oxide, conductive metal nitride, conductive metal silicide, and conductive metal carbide, and the other is formed of an insulator having the metal element. The method of manufacturing a semiconductor device according to claim 1, wherein: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the upper layer and the lower layer are both formed of an insulator having the metal element, and the metal elements are different from each other. The method of manufacturing a semiconductor device according to claim 1, wherein the following formula (1) is satisfied.
[O] / [Ge] ≦ 1 (1)
However, [Ge] is the atomic fraction of Ge in the Ge oxide layer and the Ge layer, and [O] is the atomic fraction of oxygen in the Ge oxide layer and the Ge layer. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed at 350 ° C. or higher. The insulator having the metal element is selected from insulators having any metal element of Tc, Ru, Rh, Pd, Pt, Lu, Hf, Pr, Nd, Pm, Tb, Cy, Er, Tm, and Ho. And
The method for manufacturing a semiconductor device according to claim 1, wherein an oxidation treatment is performed after the step of directly bonding the upper layer and the lower layer.