JP2017092191A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SiC semiconductor device that has a semiconductor element having a trench gate structure with a high withstanding voltage and a high reliability.SOLUTION: A material that has a higher dielectric constant than a silicon oxide film is used for at least a part of a gate insulating film 8 formed in a trench 7. When a capacity per unit area of the gate insulating film 8 is defined as Cox, and a dielectric breakdown voltage is defined as Vb,ox, the part of the gate insulating film 8 is configured by a material that satisfies a relation of Cox×Vb,ox>7.6×10C/cm. By configuring the gate insulating film 8 by such a material that satisfies that condition, an SiC semiconductor device that has a vertical MOSFET having a trench gate structure with a high withstanding voltage and a high reliability can be obtained.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device having a semiconductor element having a trench gate structure.

  Conventionally, there is a SiC semiconductor device having a semiconductor element having a trench gate structure as a structure in which a channel density is increased so that a large current can flow. In an SiC semiconductor device having such a semiconductor element having a trench gate structure, since the breakdown electric field strength of SiC is high, there is a possibility that a high electric field is applied to the bottom of the trench to cause dielectric breakdown. For this reason, in a MOSFET having a trench gate structure using SiC, for example, a p-type electric field relaxation is provided below a base layer between opposing trench gates in order to reduce an electric field applied to a gate insulating film (hereinafter referred to as a gate electric field). By forming a layer and mitigating the entry of the electric field into the bottom of the trench, dielectric breakdown is prevented.

In addition, by configuring the gate insulating film with Al ₂ O ₃ or AlON having a high dielectric constant, the gate electric field is weakened and the gate reliability is improved. In Patent Document 1, the gate insulating film is made of a film having a higher dielectric constant than that of a silicon oxide film (SiO ₂ ), and the side wall insulating film located on the trench side wall portion of the gate insulating film is located on the trench bottom portion. The condition that the dielectric constant is higher than that of the bottom insulating film is satisfied. Thus, the current drive capability of the MOSFET can be increased by configuring the gate insulating film with a film having a high dielectric constant.

Japanese Patent No. 5638558

  However, even if the dielectric constant of the gate insulating film is simply increased, the breakdown electric field at which the gate insulating film breaks down is low. As a result, a high breakdown voltage cannot be obtained, and the reliability of the elements constituting the SiC semiconductor device can be ensured. There is a problem of difficulty.

  In the MOSFET described in Patent Document 1, the above condition is satisfied. Under this condition, when a high electric field is applied when the MOSFET is turned off, the MOSFET is applied to the gate insulating film at the bottom of the trench. The electric field cannot be relaxed sufficiently. For this reason, a high breakdown voltage cannot be obtained, and it is difficult to ensure the reliability of the semiconductor elements constituting the SiC semiconductor device.

  An object of the present invention is to provide a SiC semiconductor device having a semiconductor element having a trench gate structure with high breakdown voltage and high reliability.

In order to achieve the above object, an SiC semiconductor device having a trench gate structure semiconductor element according to claim 1 is formed on a first or second conductivity type substrate (1) made of silicon carbide, and on the substrate. A drift layer (2) made of silicon carbide of the first conductivity type having a lower impurity concentration than the substrate, a base region (4) made of silicon carbide of the second conductivity type formed on the drift layer, A source region (5) formed on the base region and made of silicon carbide of the first conductivity type having a higher concentration than the drift layer; and deeper than the source region and the base region and reaching the drift layer; A trench (7) formed so that the base region is disposed on both sides, a gate insulating film (8) formed on the surface of the trench, and a gate formed on the gate insulating film in the trench A semiconductor device having a trench gate structure having a pole (9), a source electrode (10) electrically connected to the source region and the base region, and a drain electrode (12) formed on the back side of the substrate is provided. ing. In such a configuration, the gate insulating film is formed of a high dielectric constant film at least at the bottom portion of the trench. The gate insulating film has a capacitance per unit area of Cox and a breakdown voltage of Vb. , ox is Cox × Vb, ox is 7.6 × 10 ⁻⁶ C / cm ² or more.

In this way, a material having a dielectric constant higher than that of the silicon oxide film is used for at least a part of the gate insulating film, and a material satisfying the relationship that Cox × Vb, ox is 7.6 × 10 ⁻⁶ C / cm ² or more is satisfied. It is composed. By configuring the gate insulating film with a high dielectric constant film made of a material that satisfies such conditions, it is possible to obtain a SiC semiconductor device having a vertical MOSFET having a trench gate structure with high breakdown voltage and high reliability.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is a figure which shows the cross-sectional structure of the SiC semiconductor device which has vertical MOSFET of the trench gate structure concerning 1st Embodiment. It is a figure which shows the result of having calculated | required C * Vb, ox [* 10 < ^-6 > C / cm < ² >] by changing each element content rate (atomic%), using hafnium, aluminum, and a lanthanum as a constituent material of a gate insulating film. . It is a figure which shows the cross-sectional structure of the SiC semiconductor device which has vertical MOSFET of the trench gate structure concerning 2nd Embodiment. It is a figure which shows the cross-sectional structure of the SiC semiconductor device which has vertical MOSFET of the trench gate structure concerning 3rd Embodiment. It is a figure which shows the cross-sectional structure of the SiC semiconductor device which has vertical MOSFET of the trench gate structure concerning 4th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described. In the present embodiment, an SiC semiconductor device having a vertical MOSFET having an inverted trench gate structure shown in FIG. 1 will be described as an example of the SiC semiconductor device having a semiconductor element having a trench gate structure. In FIG. 1, only one cell of the vertical MOSFET is shown, but a plurality of cells having the same structure as the vertical MOSFET shown in FIG. 1 are arranged adjacent to each other.

As shown in FIG. 1, the SiC semiconductor device includes an n-type impurity made of SiC single crystal doped with an n-type impurity such as phosphorus or nitrogen at a high concentration, for example, an impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ^−3. It is formed using a ⁺ type semiconductor substrate 1. On the n ⁺ type semiconductor substrate 1, the impurity concentration is lower than that of the n ⁺ type semiconductor substrate 1, and the n type impurity is doped with an impurity concentration of, for example, 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^−3. An n-type drift layer 2 made of SiC having a thickness of about 5 to 15 μm is formed.

  The n-type drift layer 2 has a recessed portion 2a that is partially recessed. The concave portion 2a is formed in a linear shape having a longitudinal direction in one direction, that is, a direction perpendicular to the paper surface of FIG. 1, and extends to a position deeper than a trench 7 constituting a trench gate structure to be described later, and in the same direction as the trench 7 Are formed in the longitudinal direction.

In the recess 2a, an electric field relaxation layer 3 doped with a p-type impurity such as boron or aluminum is formed with the same direction as the longitudinal direction of the recess 2a being the longitudinal direction. The electric field relaxation layer 3 relaxes the gate electric field by suppressing the electric field from entering the bottom of the trench 7. For example, the electric field relaxation layer 3 is about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^−3. It is formed to a deeper position.

  A p-type base region 4 is formed on the surfaces of the n-type drift layer 2 and the electric field relaxation layer 3. The p-type base region 4 is a layer constituting a channel of the vertical MOSFET, and is formed on both sides of a trench 7 constituting a trench gate structure described later so as to be in contact with the side surface of the trench 7.

The n-type impurity is doped at a higher concentration than the n-type drift layer 2 so as to be in contact with the trench gate structure closer to the trench gate structure side than the position corresponding to the electric field relaxation layer 3 in the surface layer portion of the p-type base region 4. An n ⁺ -type source region 5 is formed. In the present embodiment, for example, the n ⁺ -type source region 5 is formed with an impurity concentration of about 1 × 10 ²¹ cm ⁻³ and a thickness of about 0.3 μm. Further, a p-type impurity is heavily doped at a position corresponding to the electric field relaxation layer 3 in the surface layer portion of the p-type base region 4, that is, on the opposite side of the trench gate structure with the n ⁺ -type source region 5 interposed therebetween. A p ⁺ -type contact region 6 is formed. In this embodiment, for example, the p ⁺ -type contact region 6 is formed with an impurity concentration of about 1 × 10 ²¹ cm ⁻³ and a thickness of about 0.3 μm.

Further, in the cross section of FIG. 1, the n-type drift layer 2 is reached through the p-type base region 4 and the n ⁺ -type source region 5 at the center position of the electric field relaxation layers 3 arranged adjacent to each other, and A trench 7 which is shallower than the bottom of the relaxation layer 3 is formed. A p-type base region 4 and an n ⁺ -type source region 5 are arranged in contact with the side surface of the trench 7. The inner wall surface of the trench 7 is covered with a gate insulating film 8 made of a high dielectric constant film or the like. Then, the inside of the trench 7 is filled with the gate electrode 9 made of doped Poly-Si formed on the surface of the gate insulating film 8. Thus, the trench gate structure is configured by the structure in which the gate insulating film 8 and the gate electrode 9 are provided in the trench 7.

  In this embodiment, the gate insulating film 8 has a multilayer structure, and here, the gate insulating film 8 has a two-layer structure of a first layer 8a and a second layer 8b. Specifically, both the first layer 8a and the second layer 8b of the gate insulating film 8 are formed on the bottom and side walls of the trench 7, and the second layer 8b is formed of the first layer 8a. The structure is formed on the surface. The first layer 8a is composed of a silicon oxide film, and the second layer 8b is composed of the high dielectric constant film described in the first embodiment. As described above, the gate insulating film 8 has a multilayer structure, and the second layer 8b made of a high dielectric constant film is provided so as to cover the bottom of the trench 7, that is, at least the bottom of the gate electrode 9. ing.

  The detailed configuration of the second layer 8b in the gate insulating film 8 will be described later. Although not shown in FIG. 1, the trench gate structure has a strip shape, for example, with the vertical direction on the paper as the longitudinal direction, and a plurality of trench gate structures are arranged in stripes at equal intervals in the horizontal direction on the paper. As a result, the structure is provided with a plurality of cells.

A source electrode 10 is formed on the surfaces of the n ⁺ type source region 5 and the p ⁺ type contact region 6. The source electrode 10 is composed of a plurality of metals (for example, nickel (Ni) and aluminum (Al)). Specifically, the portion connected to n ⁺ type source region 5 is made of a metal capable of ohmic contact with n type SiC, and the portion connected to p type base region 4 via p ⁺ type contact region 6 is It is made of a metal capable of ohmic contact with p-type SiC. The source electrode 10 is electrically separated from a gate wiring (not shown) that is electrically connected to the gate electrode 9 via the interlayer insulating film 11. The source electrode 10 is in electrical contact with the n ⁺ type source region 5 and the p ⁺ type contact region 6 through a contact hole formed in the interlayer insulating film 11.

Further, on the back side of the n ⁺ -type semiconductor substrate 1 n ⁺ -type semiconductor substrate 1 and electrically connected to the drain electrode 12 are formed. With such a structure, an n-channel type inverted MOSFET having a trench gate structure is formed.

In the vertical MOSFET having the inverted trench gate structure configured as described above, the second layer 8b formed of the high dielectric constant film in the gate insulating film 8 is formed of the trench 7 on the first layer 8a as described above. It is formed in all regions from the bottom to the side wall. Furthermore, in the case of the present embodiment, the second layer 8b is constituted by an amorphous film having an amorphous structure. The second layer 8b is made of a material having a dielectric constant higher than that of the silicon oxide film (SiO ₂ ). The gate insulating film 8 has a capacitance per unit area as Cox and a dielectric breakdown voltage as Vb and ox. It is made of a material that satisfies the relationship that Cox × Vb, ox is 7.6 × 10 ⁻⁶ C / cm ² or more. By forming the gate insulating film 8 with a material satisfying such conditions, a SiC semiconductor device having a vertical MOSFET having a trench gate structure with high breakdown voltage and high reliability is obtained. Hereinafter, the reason why this effect is obtained will be described.

  When the gate insulating film of the element having the MOS structure is broken, an electric field equal to or higher than the breakdown voltage Vb, ox is applied to the gate insulating film. In the case where the gate insulating film is composed only of a commonly used silicon oxide film, the dielectric breakdown electric field is about 11 MV / cm. For this reason, for example, assuming that 1200 V is applied to the drain electrode when the device is turned off, when the gate insulating film of the device is broken, an electric field of 11 MV / cm or more is applied to the silicon oxide film at the broken portion. It will be.

At this time, when the capacity of the gate insulating film is Cox and the breakdown voltage is Vb, ox, Cox × Vb, ox [C / cm ² ] represents the amount of charge that can be withstood when the insulating film breaks. It can be said that the larger the value, the harder the insulating film is broken. For example, in the case of a silicon oxide film, if the thickness of the gate insulating film is 50 nm, the dielectric breakdown voltage is 60 V at 50 nm × 11 MV / cm. At this time, Cox × Vb, ox becomes a value of about 3.8 × 10 ⁻⁶ C / cm ² .

  The larger the capacity, the higher the current drive capability, and the higher the breakdown voltage, the more difficult the insulation film breaks.Therefore, the larger the Cox x Vb, ox, the more desirable characteristics as a gate insulation film. Therefore, it is difficult to increase this value by using a silicon oxide film.

  On the other hand, when a high dielectric constant film is used for part or all of the gate insulating film 8 and the capacitance is the same as that of the silicon oxide film and C × Vb, ox is doubled, the gate insulating film 8 The voltage that can be applied before breakdown can be doubled, and the margin when the same drain voltage is applied can be greatly increased.

  In the present embodiment, the second layer 8b of the gate insulating film 8 is a high dielectric constant film having the same composition in all regions from the bottom to the side wall of the trench 7. A portion in contact with the corner at the bottom of the substrate may be a high dielectric constant film. In this way, since a high breakdown voltage element can be obtained, it becomes possible to further improve the reliability of the gate insulating film 8 against dielectric breakdown, and even if the electric field relaxation layer 3 is eliminated, the insulating film at the off time Destruction can be suppressed, and a highly reliable element can be realized.

Examples of the high dielectric constant film constituting the second layer 8b include hafnium (Hf), aluminum (Al), lanthanum (La), cerium (Ce), zirconium (Zr), yttrium (Y), tantalum ( An insulating material containing one or more of Ta), strontium (Sr), and the like can be given. For example, hafnium oxide (HfO ₂ ) that is an insulating material containing hafnium, aluminum oxide (Al ₂ O ₃ ) that is an insulating material containing aluminum, lanthanum oxide (La ₂ O ₃ ) that is an insulating material containing lanthanum, and the like A dielectric constant film can be applied as the second layer 8b. Further, a high dielectric constant film such as HfAlO, HfLaO, AlLaO, HfAlLaO containing hafnium and any one of aluminum or lanthanum can be applied as the second layer 8b. Furthermore, a high dielectric constant film containing any one of the above metal materials in addition to hafnium, aluminum and lanthanum can also be applied as the second layer 8b.

For example, experiments were performed using hafnium, aluminum, and lanthanum as the constituent material of the second layer 8b, and Cox × Vb, ox [C / cm ² ] was obtained by changing the element content (atomic%) of each constituent material. . FIG. 2 shows the experimental results. In this experiment, hafnium oxide, aluminum oxide, and lanthanum oxide formed on the silicon oxide film are used as constituent materials, and the contents of the constituent materials are changed. Each vertex of the triangle shown in FIG. 2 represents the case where the content rate of each constituent material is 100%, and indicates that the content rate of the constituent material increases or decreases by 10% every time one vertex is deviated from each vertex. ing. Specifically, the upper vertex of the triangle is 100% lanthanum oxide, the lower left vertex is 100% hafnium oxide, and the lower right vertex is 100% aluminum oxide. For example, when shifting from the lower left vertex to the right by 1 mm, hafnium oxide is 90%. It shows that the content of aluminum oxide is 10%. In addition, the content rate of a constituent material here is represented as follows.

  In the case where the second layer 8b is constituted by a synthetic film in which, for example, aluminum oxide and hafnium oxide are mixed, if the content is x and the content of hafnium oxide is y in aluminum oxide, the synthesis of aluminum oxide and hafnium oxide is performed. The membrane is represented by the following chemical formula: However, for x and y, x + y = 1 is satisfied by ignoring impurities.

(Chemical formula 1)
(Al ₂ O ₃ ) x (HfO ₂ ) y
As shown in FIG. 2, it is possible to satisfy Cox × Vb, ox> 7.6 × 10 ⁻⁶ C / cm ² by including hafnium oxide and aluminum oxide together with other constituent materials. In particular, the value of Cox × Vb, ox increased for the synthetic film containing aluminum oxide and hafnium oxide.

Specifically, as shown in the region (1) in FIG. 2, when the content of aluminum oxide is 0.05 to 0.75 and the content of hafnium oxide is 0.25 to 0.95, Cox × Vb, ox> 7.6 × 10 ⁻⁶ C / cm ² was satisfied. In this case, the chemical formula is represented by (Al ₂ O ₃ ) _0.05 to _0.75 (HfO ₂ ) _0.25 to _0.95 . In particular, when the aluminum oxide content was 0.3 and the hafnium oxide content was 0.7, a high value of Cox × Vb, ox of 9.7 × 10 ⁻⁶ C / cm ² was obtained.

As shown in the region (2) in FIG. 2, when the content of hafnium oxide is 0.45 to 0.75 and the content of lanthanum oxide is 0.25 to 0.55, Cox × Vb, ox > 7.6 × 10 ⁻⁶ C / cm ² was satisfied.

As shown in the region (3) in FIG. 2, the aluminum oxide content is 0.1, the hafnium oxide content is 0.25 to 0.75, and the lanthanum oxide content is 0.15 to 0.65. In this case, Cox × Vb, ox> 7.6 × 10 ⁻⁶ C / cm ² was satisfied. In this case, the chemical formula is represented by (Al ₂ O ₃ ) _0.1 (HfO ₂ ) _0.25 to _0.75 (La ₂ O ₃ ) _0.15 to _0.65 .

As shown in region (4) in FIG. 2, the content of aluminum oxide is 0.2, the content of hafnium oxide is 0.05 to 0.75, and the content of lanthanum oxide is 0.05 to 0.75. In this case, Cox × Vb, ox> 7.6 × 10 ⁻⁶ C / cm ² was satisfied. In this case, the chemical formula is represented by (Al ₂ O ₃ ) _0.2 (HfO ₂ ) _0.05 to _0.75 (La ₂ O ₃ ) _0.05 to _0.75 .

As shown in region (5) in FIG. 2, the aluminum oxide content is 0.3, the hafnium oxide content is 0.35 to 0.55, and the lanthanum oxide content is 0.15 to 0.35. In this case, Cox × Vb, ox> 7.6 × 10 ⁻⁶ C / cm ² was satisfied. In this case, the chemical formula is represented by (Al ₂ O ₃ ) _0.3 (HfO ₂ ) _0.35 to _0.55 (La ₂ O ₃ ) _0.15 to _0.35 .

As shown in region (6) in FIG. 2, the aluminum oxide content is 0.4, the hafnium oxide content is 0.35 to 0.55, and the lanthanum oxide content is 0.05 to 0.25. In this case, Cox × Vb, ox> 7.6 × 10 ⁻⁶ C / cm ² was satisfied. In this case, the chemical formula is represented by (Al ₂ O ₃ ) _0.4 (HfO ₂ ) _0.35 to _0.55 (La ₂ O ₃ ) _0.05 to _0.25 .

As shown in the region (7) in FIG. 2, the content of aluminum oxide is 0.5, the content of hafnium oxide is 0.35 to 0.45, and the content of lanthanum oxide is 0.05 to 0.15. In this case, Cox × Vb, ox> 7.6 × 10 ⁻⁶ C / cm ² was satisfied. In this case, the chemical formula is represented by (Al ₂ O ₃ ) _0.5 (HfO ₂ ) _0.35 to _0.45 (La ₂ O ₃ ) _0.05 to _0.15 .

Thus, in the content ratios of the constituent materials shown in the regions (1) to (7) in FIG. 2, Cox × Vb, ox> 7.6 × 10 ⁻⁶ C / cm ² can be satisfied. Therefore, when the second layer 8b is formed using any two or more of the constituent materials of hafnium oxide, aluminum oxide, and lanthanum oxide, the content shown in at least the regions (1) to (7) is obtained. In some cases, a high breakdown voltage of the vertical MOSFET can be realized.

  In the above description, the contents of hafnium oxide, aluminum oxide, and lanthanum oxide in the case where the second layer 8b is configured using hafnium oxide, aluminum oxide, and lanthanum oxide as constituent materials are shown. This is represented by the following element contents of hafnium, aluminum and lanthanum. In addition, the element content rate here is calculated | required as follows.

  For example, when the second layer 8b is composed of a synthetic film of hafnium oxide and aluminum oxide, as described above, when the content rate is x and the content rate of aluminum oxide is y in hafnium oxide, hafnium oxide and The synthetic film with aluminum oxide is represented by the above chemical formula 1.

  In the synthetic film represented by such a chemical formula, the element content of hafnium is 1 × x, the element content of aluminum is 2 × y, and the element content of oxygen is 2 × x + 3 × y. For example, when the aluminum oxide content shown by (3) in FIG. 2 is 0.1, the hafnium oxide content is 0.4, and the lanthanum oxide content is 0.5, the chemical formula is: It becomes.

(Chemical formula 2)
(Al ₂ O ₃ ) _0.1 (HfO ₂ ) _0.4 (La ₂ O ₃ ) _0.5
In this case, aluminum is 2 × 0.1, hafnium element content is 1 × 0.4, lanthanum element content is 2 × 0.5, and oxygen element content is 3 × 0.1 + 2 × 0. 4 + 3 × 0.5. When this is calculated, the element content of aluminum is 4.8%, the element content of hafnium is 9.5%, the element content of lanthanum is 23.8%, and the element content of oxygen is 61.9%. . Based on such an element content calculation method, each element content described above is derived. In addition, although element content rate was calculated also about oxygen here for easy understanding, the element content rate of oxygen is abbreviate | omitted in the element content rate about following each area | region (1)-(7).

  In the case of the region (1), that is, when the second layer 8b is composed of a high dielectric constant film containing hafnium and aluminum, the element content is 5 to 31% for hafnium and 3 to 34% for aluminum.

  In the case of the region (2), that is, when the second layer 8b is composed of a high dielectric constant film containing hafnium and lanthanum, the element content is 10 to 22% for hafnium and 14 to 27% for lanthanum.

  In the case of the regions (3) to (7), that is, when the second layer 8b is constituted by a high dielectric constant film containing hafnium, aluminum and lanthanum, the element content is 1 to 22% for hafnium and 4 to about aluminum. For 25%, lanthanum is 2-31%.

As described above, the element content in each of the regions (1) to (7) in FIG. 2 is as described above. In such an element content, Cox × Vb, ox> 7.6 × 10 ⁻⁶ C / cm ² can be satisfied, and the high breakdown voltage of the vertical MOSFET can be increased.

  Since lanthanum oxide easily absorbs moisture and stable device characteristics cannot be obtained, the lanthanum content is preferably as small as possible.

  Further, in addition to the above materials, nitrogen (N) or hydrogen (H) may be included as a constituent material of the second layer 8b. When adding nitrogen to the constituent material of the second layer 8b, the elemental content of nitrogen is set to 1 to 30%. By adding nitrogen in this manner, the crystallization temperature of the second layer 8b can be increased, and the temperature applicable during the process can be increased, so that the degree of freedom in the process can be further increased. Further, it becomes possible to repair the defect by nitrogen element entering a defect such as an oxygen vacancy formed in the second layer 8b. When adding hydrogen to the constituent material of the second layer 8b, the elemental content of hydrogen is set to 1 to 10%. By adding hydrogen in this way, defects at the trench interface are repaired by hydrogen, and fluctuations in threshold voltage of the vertical MOSFET due to defects generated when stress is applied can be suppressed. It becomes possible to increase specific stability. Only one of nitrogen and hydrogen may be contained in the second layer 8b, or both may be contained.

As described above, in the SiC semiconductor device having the vertical MOSFET according to the present embodiment, the entire region from the bottom of the trench 7 to the side wall of the second layer 8b of the gate insulating film 8 is a high dielectric constant film. It is composed by. The gate insulating film 8 is made of a material having a dielectric constant higher than that of the silicon oxide film (SiO ₂ ) and satisfying the relationship of Cox × Vb, ox> 7.6 × 10 ⁻⁶ C / cm ² or more. It is composed. By configuring the gate insulating film 8 with a material satisfying such conditions, a SiC semiconductor device having a vertical MOSFET having a trench gate structure with high breakdown voltage and high reliability can be obtained.

  The manufacturing method of the SiC semiconductor device having the vertical MOSFET according to the present embodiment is basically the same as the conventional manufacturing method, and the constituent material for forming the gate insulating film 8 is changed from the conventional one. Or changing the forming method. For example, the gate insulating film 8 can be formed by a CVD (chemical vapor deposition) method, an ALD (atomic layer deposition) method, or the like, for both the first layer 8a and the second layer 8b. The first layer 8a may be formed by a thermal oxidation method or a deposition method. As described above, when nitrogen or hydrogen is contained in the second layer 8b, the atmosphere at the time of forming the second layer 8b is a nitrogen atmosphere or a hydrogen atmosphere, or the second layer 8b is in a state not containing nitrogen or hydrogen. Heat treatment may be performed in a nitrogen atmosphere or a hydrogen atmosphere after the formation of the two layers 8b.

(Second Embodiment)
A second embodiment will be described. In the present embodiment, the structure of the gate insulating film 8 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described.

  As shown in FIG. 3, in this embodiment, the gate insulating film 8 has a single layer structure, and the gate insulating film 8 is formed on the bottom and side walls of the trench 7. The entire gate insulating film 8 is constituted by the high dielectric constant film constituting the second layer 8b described in the first embodiment. The material of the high dielectric constant film used as the gate insulating film 8 of the present embodiment is the same as the constituent material of the second layer 8b described in the first embodiment.

  As described above, even when the gate insulating film 8 has a single layer structure, the second layer 8b formed of a high dielectric constant film so as to cover the bottom of the trench 7, that is, at least the bottom of the gate electrode 9, is formed. Since it is provided, the same effect as the first embodiment can be obtained.

  The manufacturing method of the SiC semiconductor device having the vertical MOSFET having such a structure is basically the same as the conventional method, and only the formation process of the gate insulating film 8 is different. Specifically, the gate insulating film 8 may be manufactured by using the method for forming the second layer 8b composed of the high dielectric constant film described in the first embodiment. In the case of the structure as in the present embodiment, the gate insulating film 8 may be formed of one kind of film over the entire surface of the bottom and side walls of the trench 7, so that the gate insulating film 8 can be easily formed.

(Third embodiment)
A third embodiment will be described. In the present embodiment, the structure of the gate insulating film 8 is changed with respect to the first embodiment, and the others are the same as those in the first embodiment. Therefore, only the parts different from the second embodiment will be described.

  As shown in FIG. 4, in the present embodiment, the first layer 8a is formed only on the side wall of the trench 7 and is not formed on the bottom. The second layer 8 a is in contact with the n-type drift layer 2 at the bottom of the trench 7.

  Even in the case of such a structure, since the second layer 8b made of a high dielectric constant film is provided so as to cover the bottom of the trench 7, that is, at least the bottom of the gate electrode 9, the first layer is provided. The same effect as the embodiment can be obtained. Further, by forming the first layer 8a only on the side wall portion of the trench 7, it becomes possible to reduce the gate capacitance, and it is possible to reduce the switching loss of the vertical MOSFET.

  The manufacturing method of the SiC semiconductor device having the vertical MOSFET having such a structure is basically the same as that of the first embodiment. However, as a step of forming the gate insulating film 8, after the first layer 8a is formed, the second layer 8b is formed after removing the bottom portion of the trench 7 in the first layer 8a by anisotropic etching or the like. Will be performed.

(Fourth embodiment)
A fourth embodiment will be described. This embodiment is also a modification of the structure of the gate insulating film 8 with respect to the first embodiment, and the other parts are the same as those of the first embodiment. Therefore, only the parts different from the first embodiment will be described.

  As shown in FIG. 5, in the present embodiment, the first layer 8a is formed only on the bottom of the trench 7 and not on the side wall. The second layer 8 a is in contact with the n-type drift layer 2 and the p-type base region 4 at the side wall of the trench 7.

  Even in the case of such a structure, since the second layer 8b made of a high dielectric constant film is provided so as to cover the bottom of the trench 7, that is, at least the bottom of the gate electrode 9, the first layer is provided. The same effect as the embodiment can be obtained. In addition, by forming the first layer 8a only at the bottom of the trench 7, it is possible to reduce the gate capacitance, and to reduce the switching loss of the vertical MOSFET.

  The manufacturing method of the SiC semiconductor device having the vertical MOSFET having such a structure is basically the same as that of the first embodiment. However, as the step of forming the gate insulating film 8, after the first layer 8a is formed, the second layer 8b is formed after the first layer 8a is left only at the bottom portion of the trench 7 by etch back. Will do.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in the above embodiment, the structure of the gate insulating film 8 has been described with some examples. However, these are only examples, and a portion of the gate insulating film 8 located at the bottom of the trench 7, in other words, a portion of the gate electrode 9 located at least at the bottom of the trench 7 and The corresponding part should just be comprised with the high dielectric constant film | membrane.

  In addition, although an oxide film is cited as an example of an insulating material containing at least one of hafnium, aluminum, lanthanum, cerium, zirconium, yttrium, tantalum, strontium, and the like constituting the high dielectric constant film constituting the gate insulating film 8, An oxynitride film may be used.

  Further, the gate insulating film 8 can be constituted by an amorphous film having an amorphous structure, but can also be constituted by a crystal film having a crystal structure. In the case of the amorphous structure, since there is no crystal grain boundary, it becomes possible to suppress the leakage current. In the case of a crystalline film, for example, doping with zirconium, yttrium, or the like provides an effect that the crystallinity is changed and the relative dielectric constant can be further increased.

In each of the above-described embodiments, an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. The present invention can also be applied to a channel type MOSFET. Furthermore, in the above description, the trench gate structure MOSFET has been described as an example. However, the present invention can be applied to a similar trench gate structure IGBT. The IGBT only changes the conductivity type of the n ⁺ type substrate 1 from the n-type to the p-type with respect to the above-described embodiments, and the other structures and manufacturing methods are the same as those of the above-described embodiments.

1 n ⁺ type semiconductor substrate 2 n type drift layer 4 p type base region 5 n ⁺ type source region 7 trench 8 gate insulating film 8a first layer 8b second layer 9 gate electrode 10 source electrode 12 drain electrode

Claims (9)

A silicon carbide semiconductor device having a semiconductor element having a trench gate structure,
A first or second conductivity type substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate;
A base region (4) made of silicon carbide of the second conductivity type formed on the drift layer;
A source region (5) formed on the base region and made of silicon carbide of the first conductivity type having a higher concentration than the drift layer;
A trench (7) formed so as to be deeper than the source region and the base region and reach the drift layer, and the source region and the base region are disposed on both sides;
A gate insulating film (8) formed on the surface of the trench;
A gate electrode (9) formed on the gate insulating film in the trench;
A source electrode (10) electrically connected to the source region and the base region;
A drain electrode (12) formed on the back side of the substrate; and the semiconductor element having a trench gate structure,
In the gate insulating film, at least a portion located at the bottom of the trench is formed of a high dielectric constant film, and the gate insulating film has a capacitance per unit area as Cox and a dielectric breakdown voltage as Vb, ox. A silicon carbide semiconductor device in which Cox × Vb, ox is 7.6 × 10 ⁻⁶ C / cm ² or more.   The silicon carbide semiconductor device according to claim 1, wherein the gate insulating film has an amorphous structure. A silicon carbide semiconductor device having a semiconductor element having a trench gate structure,
A first or second conductivity type substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate;
A base region (4) made of silicon carbide of the second conductivity type formed on the drift layer;
A source region (5) formed on the base region and made of silicon carbide of the first conductivity type having a higher concentration than the drift layer;
A trench (7) formed so as to be deeper than the source region and the base region and reach the drift layer, and the source region and the base region are disposed on both sides;
A gate insulating film (8) formed on the surface of the trench;
A gate electrode (9) formed on the gate insulating film in the trench;
A source electrode (11) electrically connected to the source region and the base region;
A drain electrode (12) formed on the back side of the substrate; and the semiconductor element having a trench gate structure,
The gate insulating film is formed of a high dielectric constant film at least at a portion located at the bottom of the trench, and the high dielectric constant film is composed of hafnium, aluminum, lanthanum, cerium, zirconium, yttrium, tantalum, and strontium. A silicon carbide semiconductor device made of an insulating material containing at least one of the above.   The carbonization according to any one of claims 1 to 3, wherein the high dielectric constant film is made of an insulating material containing at least two of hafnium, aluminum, lanthanum, cerium, zirconium, yttrium, tantalum, and strontium. Silicon semiconductor device.   The carbonization according to any one of claims 1 to 3, wherein the high dielectric constant film includes hafnium and aluminum, the element content of hafnium is 5 to 31%, and the element content of aluminum is 3 to 34%. Silicon semiconductor device.   The carbonization according to any one of claims 1 to 3, wherein the high dielectric constant film contains hafnium and lanthanum, the element content of hafnium is 10 to 22%, and the element content of lanthanum is 14 to 27%. Silicon semiconductor device.   The high dielectric constant film includes hafnium, aluminum, and lanthanum, the element content of hafnium is 1 to 22%, the element content of aluminum is 4 to 25%, and the element content of lanthanum is 2 to 31%. Item 4. The silicon carbide semiconductor device according to any one of Items 1 to 3.   The silicon carbide semiconductor device according to claim 3, wherein the high dielectric constant film contains nitrogen, and an element content of nitrogen is 1 to 30%.   The silicon carbide semiconductor device according to any one of claims 3 to 8, wherein the high dielectric constant film contains hydrogen, and an element content of hydrogen is 1 to 10%.

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