JP2007194652A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-k gate insulating layer having a long reliability life. <P>SOLUTION: The high-k gate insulating layer formed between an Si substrate 11 and a gate electrode 17 comprises an interface layer 15 formed on an interface with the Si substrate 11, and the high-k layer 16 which is formed on the interface layer 15 and has a relative dielectric constant higher than that of the interface layer 15. The thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 satisfy a relation of T1/(T1+T2)≤0.3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a gate insulating film made of a high dielectric material.

With the recent progress in technology for higher integration and higher speed in semiconductor devices, MOSFETs have been miniaturized. As the gate insulating film is made thinner with miniaturization, problems such as an increase in gate leakage current due to tunneling current become obvious. In order to suppress this problem, a gate insulating film using a high dielectric constant material such as HfO ₂ , ZrO ₂ , La ₂ O ₃ , TiO ₂ or Ta ₂ O ₅ (hereinafter referred to as a high-k gate insulating film). Therefore, a method of increasing the physical film thickness while realizing a small SiO ₂ equivalent film thickness (hereinafter referred to as EOT (Equivalent Oxide Thickness)) has been studied.

  In recent system LSIs, it is common to integrate an internal circuit that performs arithmetic processing, a peripheral circuit that handles input and output, and a circuit having a plurality of functions such as a DRAM on a single chip. For a MOSFET constituting such a system LSI, high driving force and low leakage current are required.

  As a conventional method for forming a high-k gate insulating film, a method described in JP 2000-058832 A (United States Patent 6,013,553) is known.

  FIG. 5 shows a cross-sectional structure of a conventional semiconductor device disclosed in the above publication, specifically, a MOSFET having a high-k gate insulating film made of zirconium oxynitride or hafnium oxynitride.

  As shown in FIG. 5, an epitaxial Si layer 2 is formed on the Si substrate 1. The upper portion of the epitaxial Si layer 2 is doped with impurities, and the upper portion becomes the channel region 3 when a voltage is applied. A conductive gate electrode 5 is formed on the channel region 3 via a high-k gate insulating film 4.

The formation method of the high-k gate insulating film 4 is as follows. That is, after forming an epitaxial Si layer 2 including a portion that becomes the channel region 3 on the Si substrate 1, the Si substrate 1 is subjected to 600 to 600 to the Si substrate 1 in an oxygen atmosphere at a pressure of about 1.33 × 10 ⁻¹ Pa. By performing heat treatment at about 700 ° C. for about 30 seconds, an oxide layer having a thickness of less than 1 nm is formed. Thereafter, the oxide layer is left as it is, or is removed by dilute HF, and the Si surface is hydrogen-terminated, or an ultra-high vacuum state (about 1.33 × 10 ⁻⁶ Pa) using a cluster tool. Either a sublimation is performed by heating at about 780 ° C. to form an atomically smooth Si surface. Instead of leaving the oxide layer, that is, the silicon oxide film, a protective barrier layer made of an ultrathin silicon oxynitride film may be formed.

After preparing the Si substrate 1 having either a clean Si surface, an oxide layer, or a protective barrier layer as described above, a sputtering method, vapor deposition method, chemical vapor deposition (CVD) is performed on the Si substrate 1. A metal layer made of zirconium or hafnium is deposited by a method or a plasma CVD method. Thereafter, the metal layer is subjected to an oxynitriding treatment using a gas containing oxygen and nitrogen such as NO or N ₂ O, a remote plasma treatment at a low temperature using N ₂ and O ₂ (substrate treatment chamber and plasma). The high-k gate insulating film 4 made of zirconium oxynitride or hafnium oxynitride is formed by performing a remote plasma nitridation process using NH ₃ and subsequent oxidation process or the like. .

Thereafter, the high-k gate insulating film 4 is densified by annealing the high-k gate insulating film 4 at about 750 ° C. for 20 seconds in an inert gas atmosphere such as Ar or a reducing gas atmosphere. To do. The high-k gate insulating film 4 formed in this way is amorphous or polycrystalline, and has a dielectric constant that is significantly higher than that of SiO ₂ .
JP2000-058832 (United States Patent 6,013,553)

  However, the above-described conventional MOSFET has a problem that the reliability life of the high-k gate insulating film is shortened.

  In view of the above, an object of the present invention is to realize a high-k gate insulating film having a long reliability life.

In order to achieve the above object, the present inventor has studied the cause of shortening of the reliability life of the conventional high-k gate insulating film, and as a result, has obtained the following knowledge. That is, when a high-k gate insulating film is formed on a silicon substrate using the above-described conventional method, a silicate (high-k material (metal oxide such as zirconium oxide) close to the composition of SiO ₂ is formed at the silicon substrate interface. And a ternary compound of silicon). In general, silicates have a lower dielectric constant than the original high-k material that does not contain silicon. Further, as a result of the crystallization of the high-k material constituting the gate insulating film being advanced by annealing (PDA (Post Deposition Anneal) for densifying the gate insulating film) after the deposition of the high-k gate insulating film, Oxygen diffuses from the -k material through the grain boundaries to the silicon substrate, thereby forming SiO _{2 at the} silicon substrate interface. That is, the high-k gate insulating film has a low dielectric constant SiO ₂ or an interface layer made of silicate close to the composition of SiO ₂ and a high-k material having a high relative dielectric constant or a silicate close to the composition of the high-k material. It has a laminated structure with a high-k layer. However, in such a laminated structure, when a voltage is applied through the gate electrode, electric field concentration occurs in the interface layer having a low dielectric constant, and as a result, dielectric breakdown is likely to occur, resulting in a high-k gate insulating film. It is considered that the reliability, which is an important characteristic of, deteriorates.

Accordingly, the inventor of the present application has determined that the reliability lifetime of the high-k gate insulating film and the ratio of the interface layer thickness to the total thickness of the high-k gate insulating film are T1 / (T1 + T2) (where T1 is the interface layer thickness). The correlation with the physical thickness (T2 is the physical thickness of the high-k layer) was examined using simulation. The result is shown in FIG. The simulation was performed by applying a trap generation model (JHStathis, Technical Digest of International Electron Device and Material (1998), p167.) To a high-k gate insulating film. Specifically, for the high-k gate insulating film, the leakage current J _g , the leakage current J ₀ immediately after stress application, the defect generation rate P _g per injected charge (= current increase ratio ΔJ _g / J ₀ at the time of dielectric breakdown) ) And the critical defect density N _{bd at} the time of dielectric breakdown, and the dielectric breakdown lifetime T _bd (= N _bd / P _g ) in the high-k gate insulating film is obtained based on these values. It was. In the simulation, the ratio T1 / (T1 + T2) is changed while adjusting the physical thicknesses T1 and T2 so that the EOT of the high-k gate insulating film is always kept at 1.5 nm. The reliability lifetime of the high-k gate insulating film under a stress of 1 V applied voltage (temperature is room temperature) was calculated. However, in the simulation, the relative dielectric constant ε1 of the interface layer is fixed to a constant value of 3.9, whereas the relative dielectric constant ε2 of the high-k layer is 8.0, 12.0, 18.0. And multiple values of 24.0. Here, the relationship EOT = T1 + (ε1 / ε2) × T2 holds.

  As shown in FIG. 1, when the ratio T1 / (T1 + T2), that is, the ratio of the interface layer thickness to the total thickness of the high-k gate insulating film is 0.2 or less, the reliability of the high-k gate insulating film Can be kept high. Further, as the ratio T1 / (T1 + T2) increases, the reliability of the high-k gate insulating film tends to deteriorate. Furthermore, considering that the logarithmic scale is used for the vertical axis in FIG. 1, setting the ratio T1 / (T1 + T2) to 0.2 or less dramatically improves the reliability of the high-k gate insulating film. It turns out that it has the effect to make it. Specifically, by setting the ratio T1 / (T1 + T2) to 0.2 or less, for example, the reliability life is increased by three orders of magnitude or more compared to the case where the ratio T1 / (T1 + T2) is about 0.5. can do.

Further, as shown in FIG. 1, in a gate insulating film having a structure where the ratio T1 / (T1 + T2) is 0.0 to 0.2, the high-k layer has a relative dielectric constant ε2 of 8.0 to 12.2. As the value increases to 0, the length of the reliability life increases, and in the range of ε2 from 12.0 to 18.0, the length of the reliability life is almost saturated and shows the maximum value. On the other hand, when ε2 increases from 18.0 to 24.0, the length of the reliability life decreases. Incidentally, in general, the value of the relative dielectric constant ε2 in the high-k layer changes in the thickness direction. Therefore, when the average value of the dielectric constant .epsilon.2 in high-k layer and .epsilon.2 _av is, .epsilon.2 _av is preferably at and 18.0 or less at 12.0 or higher. When a silicate film containing one metal, silicon, and oxygen is used as the high-k layer, the composition of the high-k layer is M _X Si _Y O (where M represents one metal and X> 0 , Y> 0), the aforementioned condition of 12.0 ≦ ε2 _av ≦ 18.0 is equivalent to the condition of 0.20 ≦ Y / (X + Y) ≦ 0.30. That is, from the viewpoint of the reliability of the high-k gate insulating film, 0.20 ≦ Y / (X + Y) ≦ 0.30 rather than using a complete metal oxide containing no silicon as the material of the high-k layer. It is preferable to use a silicon-containing silicate M _X Si _Y O that satisfies the above relationship. The reason is considered to be that the electric field concentration on the interface layer is reduced by reducing the difference in relative dielectric constant between the high-k layer and the interface layer. The interface layer may also contain a silicate that can be expressed as M _X Si _Y O, but Y / (X + Y) in this silicate is 0.90 or more, and is compositionally equivalent to SiO ₂ .

Further, the inventor of the present application has determined the reliability lifetime of the high-k gate insulating film and the total thickness (T1 + T2) of the high-k gate insulating film having the interface layer thickness T1 (where T2 is the physicality of the high-k layer). The correlation with the ratio to the thickness was determined experimentally. The result is shown in FIG. The interface layer used in the experiment is a SiON film (relative permittivity ε1 = 3.9) having a composition close to that of SiO ₂ , and the high-k layer used in the experiment is formed by a chemical vapor deposition (CVD) method. Si ₃ N ₄ film (relative permittivity ε2 = 7.5). In the experiment, the ratio T1 / (T1 + T2) was changed while adjusting the physical thicknesses T1 and T2 so that the EOT of the high-k gate insulating film always kept 3.0 nm. The total amount of electric charge (dielectric breakdown total charge Q _bd ) injected into the insulating film until dielectric breakdown occurred under stress of an applied voltage of 3.5 V (temperature is 100 ° C.) was measured. Here, the magnitude of the total dielectric breakdown Q _bd corresponds to the reliability lifetime of the high-k gate insulating film.

  As shown in FIG. 2, when the ratio T1 / (T1 + T2) is 0.2 or less, the reliability of the high-k gate insulating film can be maintained high. On the other hand, when the ratio exceeds 0.3, the reliability increases rapidly. It was experimentally proved to deteriorate. In addition, considering that the logarithmic scale is used on the vertical axis in FIG. 2, setting the ratio T1 / (T1 + T2) to 0.2 or less dramatically improves the reliability of the high-k gate insulating film. It turns out that it has the effect to make it.

  As described above, from the results shown in FIGS. 1 and 2, from the viewpoint of the reliability of the high-k gate insulating film, the ratio of the interface layer thickness T1 to the total thickness (T1 + T2) is set to 0.3 or less. It is essential that the ratio T1 / (T1 + T2) is 0.2 or less.

  The present invention has been made based on the above knowledge. Specifically, the semiconductor device according to the present invention is premised on a semiconductor device having a high dielectric constant insulating film formed on a semiconductor substrate. The dielectric constant insulating film has an interface layer formed at the interface with the semiconductor substrate, and a high dielectric constant layer formed on the interface layer and having a higher relative dielectric constant than the interface layer, and the thickness of the interface layer T1 and the thickness T2 of the high dielectric constant layer satisfy the relationship of T1 / (T1 + T2) ≦ 0.3.

  According to the semiconductor device of the present invention, when the ratio of the interface layer thickness T1 to the total thickness (T1 + T2) in the high dielectric constant insulating film is set to 0.3 or less, the voltage is applied to the high dielectric constant insulating film. Also, the electric field concentration on the interface layer can be suppressed. Therefore, a high-k gate insulating film having a long reliability life can be realized by using such a high dielectric constant insulating film. At this time, since the interface layer having a low relative dielectric constant is thin and the high dielectric constant layer having a high relative dielectric constant is thick, the EOT of the high-k gate insulating film can be reduced.

  In the semiconductor device of the present invention, T1 and T2 preferably satisfy the relationship of T1 / (T1 + T2) ≦ 0.2.

  In this way, the reliability of the high dielectric constant insulating film can be further improved.

In the semiconductor device of the present invention, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric layer is larger than 7.0. the ratio average value .epsilon.2 _av dielectric .epsilon.2 is preferably at and 18.0 or less at 12.0 or higher.

  In this way, since the difference in relative dielectric constant between the high dielectric constant layer and the interface layer is limited within a predetermined range, the electric field concentration on the interface layer during voltage application is further relaxed, and the high dielectric constant The reliability of the insulating film can be further improved.

In the semiconductor device of the present invention, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric layer is larger than 7.0. , Which is composed of a silicate containing one metal, silicon, and oxygen, and the composition of the high dielectric constant layer is M _X Si _Y O (where M represents one metal and X> 0, Y> 0). In some cases, X and Y preferably satisfy the relationship of 0.20 ≦ Y / (X + Y) ≦ 0.30.

  In this way, the relative dielectric constant difference between the high dielectric constant layer and the interface layer is reduced compared to the case where a complete metal oxide not containing silicon is used as the material of the high dielectric constant layer. Electric field concentration on the interface layer during voltage application is further relaxed, and as a result, the reliability of the high dielectric constant insulating film can be further improved.

  In the semiconductor device of the present invention, the high dielectric constant layer is preferably made of silicate containing hafnium or zirconium, silicon, and oxygen.

  In this way, a high-k gate insulating film having a long reliability life can be reliably realized.

  According to the present invention, since the ratio of the interfacial layer thickness T1 in the high-k gate insulating film to the total thickness (T1 + T2) is 0.3 or less, electric field concentration on the interfacial layer when a gate voltage is applied can be suppressed. The reliability lifetime of the high-k gate insulating film can be improved.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

  3A to 3E are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the present embodiment.

As shown in FIG. 3A, for example, an element isolation insulating film 12 is formed on a Si (100) substrate 11, thereby defining a device region _RD .

Next, after the standard RCA cleaning and the diluted HF cleaning are sequentially performed on the Si substrate 11, for example, heat treatment is performed on the Si substrate 11 at about 600 to 700 ° C. in NH ₃ gas. Thereby, as shown in FIG. 3B, a silicon nitride film (Si ₃ N ₄ film) 13 is formed on the Si substrate 11 in the device region _RD .

Next, as shown in FIG. 3C, the HfO ₂ film 14 is formed on the Si ₃ N ₄ film 13 by using, for example, a CVD method. Specifically, bubbling is performed by blowing a carrier gas such as N ₂ into Hft-butoxide (C ₁₆ H ₃₆ HfO ₄ ), which is a liquid Hf source. As a result, the liquid Hf source is made into a gaseous state, the source gas is introduced into the reaction furnace together with the carrier gas, and the HfO ₂ film 14 is formed using RT-CVD (Rapid Thermal CVD) processing at a temperature of about 500 ° C. Form. At this time, dry O ₂ gas is introduced into the reaction furnace in order to improve the growth rate or film quality of the HfO ₂ film 14. Was subjected to a composition analysis with respect to the HfO ₂ film 14 thus formed, Hf in Hf source, O, because they contain C and H, the interior of the HfO ₂ film 14 1-2 atomic% A trace amount of C and H of less than or equal to that was contained. Although N ₂ gas is also introduced into the reactor, N ₂ gas is very inert at a temperature of about 500 ° C., so the contribution of N ₂ gas is very small.

Next, a PDA treatment at about 600 to 800 ° C. is performed for about 30 seconds on the HfO ₂ film 14 in N ₂ gas, for example. Thus, oxidation of the Si substrate 11, desorption of hydrogen from the HfO ₂ film 14, densification and crystallite of the HfO ₂ film 14, and a Si substrate 11 or _Si 3 _{N 4} film 13 and the HfO ₂ film 14 Reaction such as interdiffusion of Si and Hf occurs between the two. As a result, in the initial deposition of the HfO ₂ film 14 (see FIG. 3 (c)), the HfO ₂ film 14 is formed on the _Si 3 _{N 4} film 13 is formed and _{the Si} 3 _{N 4} film 13 on the Si substrate 11 Finally, as shown in FIG. 3 (d), the interface layer 15 having a low relative dielectric constant is formed on the Si substrate 11 and the high-k layer 16 having a high relative dielectric constant is formed on the interface layer 15. Changes to the structure formed. Here, the interface layer 15 is made of silicate close to the composition of SiO ₂ or SiO ₂ , and the high-k layer 16 is made of silicate close to the composition of HfO ₂ or HfO ₂ . Further, the interface layer 15 and the high-k layer 16 each contain a small amount of N.

Next, as shown in FIG. 3E, a gate electrode 17 made of, for example, polysilicon is formed on the high-k gate insulating film having a laminated structure of the interface layer 15 and the high-k layer 16. Specifically, after forming a polysilicon film using SiH ₄ at a deposition temperature of about 540 ° C., P ions are implanted into the polysilicon film at a dose of 5 × 10 ¹⁵ cm ^−2, for example. Thereafter, the gate electrode 17 is formed by patterning the ion-implanted polysilicon film. Thereby, the nMOSFET structure is completed. The activation annealing for the impurity implanted into the gate electrode 17 was performed by RTP (Rapid Thermal Process) at 900 ° C. for 30 seconds in dry N ₂ gas.

The feature of this embodiment is that, for example, the Si ₃ N ₄ film 13 is formed on the Si substrate 11 before the HfO ₂ film 14 is formed, or the processing temperature of the PDA for the HfO ₂ film 14 is set lower, for example. Alternatively, the ratio of the thickness of the interface layer 15 to the total thickness of the high-k gate insulating film is set within a predetermined range by setting the PDA processing time short. Specifically, the thickness T1 of the interface layer 15 with respect to the total thickness of the high-k gate insulating film, that is, the total thickness (T1 + T2) of the thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 Is set to 0.3 or less, more preferably 0.2 or less. Thereby, in this embodiment, since electric field concentration on the interface layer 15 can be suppressed even when a gate voltage is applied, a high-k gate insulating film having a long reliability life can be realized. Further, CV (capacitance-voltage) measurement is performed using a LCR (inductance-capacitance-resistance) meter for a MOS capacitor having a gate insulating film in which the interface layer 15 and the high-k layer 16 are laminated, When the EOT of the gate insulating film was calculated by a simulation program in consideration of the depletion of the gate electrode or the quantization effect of the substrate based on the measurement result, a sufficiently small EOT was obtained. That is, in the present embodiment, since the interface layer 15 having a low relative dielectric constant is thin and the high-k layer 16 having a high relative dielectric constant is thick, the EOT of the high-k gate insulating film can be reduced.

FIG. 4A shows a high-resolution cross-sectional TEM (transmission electron microscope) of the semiconductor device of this embodiment, that is, a MOSFET provided with a gate insulating film using a HfO ₂ dielectric formed by using an Hf precursor as a high-k material. ) Shows an image. As shown in FIG. 4A, the total thickness of the high-k gate insulating film in the semiconductor device of this embodiment (the sum of the thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 (T1 + T2 )) Is about 3.0 to 3.3 nm. Further, the thickness T1 of the interface layer 15 is about 0.4 to 0.5 nm. That is, the ratio T1 / (T1 + T2) of the thickness of the interface layer 15 to the total thickness of the high-k gate insulating film is about 0.12 to 0.17, and the relationship recommended in the present invention: T1 / (T1 + T2) ≦ 0.3 (more preferably T1 / (T1 + T2) ≦ 0.2) is sufficiently satisfied.

FIG. 4B shows a high-resolution cross section of a semiconductor device as a comparative example, that is, another MOSFET provided with a gate insulating film made of a HfO ₂ dielectric made of the same method as that of the present embodiment and using a high-k material. A TEM image is shown. As shown in FIG. 4B, in the semiconductor device of the comparative example, the interface layer 25 and the high-layer are formed on the Si substrate 21 so as to correspond to the MOS capacitor structure of this embodiment shown in FIG. A gate electrode 27 made of Poly-Si is formed through a gate insulating film having a laminated structure with the k layer 26. In the semiconductor device of the comparative example, the total thickness of the high-k gate insulating film (the total of the thickness T1 ′ of the interface layer 25 and the thickness T2 ′ of the high-k layer 26 (T1 ′ + T2 ′)) Is about 3.0 to 3.3 nm. Further, the thickness T1 ′ of the interface layer 25 is about 1.0 nm. That is, the ratio T1 ′ / (T1 ′ + T2 ′) of the thickness of the interface layer 25 to the total thickness of the high-k gate insulating film is about 0.30 to 0.33, and the relationship recommended in the present invention described above. Does not meet.

For each of the MOS capacitor structure of the present embodiment shown in FIG. 4A and the comparative example of the MOS capacitor structure shown in FIG. 4B, the gate area is 5000 μm ² and the applied voltage is 3.0 V (the gate electrode side is The reliability lifetime of the gate insulating film under a low potential stress (temperature is room temperature) was calculated. As a result, the reliability life of the gate insulating film of this embodiment having a small relative thickness of the interface layer is about 1 × 10 ⁴ seconds, and the reliability life of the gate insulating film of the comparative example having a large relative thickness of the interface layer. Was about 1 × 10 ² seconds. That is, when the ratio T1 / (T1 + T2) of the interface layer thickness to the total thickness of the high-k gate insulating film is 0.2 or less, the reliability life of the high-k gate insulating film is dramatically improved. . This is presumably because if the low dielectric constant interface layer formed on the surface of the Si substrate can be made thin, it is possible to avoid the occurrence of reliability degradation due to the strong electric field strength concentrated on the interface layer.

Incidentally, as shown in FIGS. 4A and 4B, in the high-resolution cross-sectional TEM image of the high-k gate insulating film, the image of the interface layer is clearly white compared to the image of the high-k layer. Here, when the composition of the high-k gate insulating film is Hf _X Si _Y O (where X> 0, Y> 0), Y / (X + Y) = 0.90 is the boundary between the interface layer and the high-k layer. Corresponding to Note that the composition of the high-k gate insulating film changes so that the Si composition gradually decreases from the Si substrate side, in other words, the value of Y / (X + Y) gradually decreases from 1.0. That is, the range satisfying the relationship of 0.90 ≦ Y / (X + Y) ≦ 1.0 is the interface layer, and the range satisfying the relationship of Y / (X + Y) <0.90 is the high-k layer. At this time, the relative dielectric constant ε1 of the interface layer is not less than 3.9 and not more than 7.0, and the relative dielectric constant ε2 of the high-k layer is larger than 7.0.

In the present embodiment, after forming the HfO ₂ film 14 via _{the Si} 3 _{N 4} film 13 on the Si substrate 11, performs PDA processing on the HfO ₂ film 14, whereby the interfacial layer 15 high A high-k gate insulating film having a laminated structure with the -k layer 16 is formed, but at this time, nitrogen atoms are included in any part of the gate insulating film (the vicinity of the substrate, the vicinity of the electrode, the center of the film, etc.) It may be. PDA processing conditions are not particularly limited, but the PDA processing temperature is preferably about 800 ° C. or lower, and the PDA processing temperature is preferably about 30 seconds or lower.

In the present embodiment, the HfO ₂ film 14 is formed using Hft-butoxide, which is a liquid Hf source, but the method for forming the HfO ₂ film 14 is not particularly limited. Specifically, for example, Hf nitrato (Hf (NO ₃ ) ₄ ), which is a solid raw material, is heated to a liquid state, and a carrier gas such as Ar is blown into the liquid raw material, and then vaporization is performed. The raw material is introduced into a reaction furnace of a CVD apparatus having a substrate heater and a cold wall together with a carrier gas, and then an HfO ₂ film 14 is formed using RT-CVD at a temperature of about 200 ° C. Also good. At this time, dry O ₂ gas is introduced into the reaction furnace in order to improve the growth rate or film quality of the HfO ₂ film 14. Case of performing composition analysis with respect to the HfO ₂ film 14 thus formed, because it contains Hf, O, and N is in the Hf source, internal to about 1-2 atomic percent of the HfO ₂ film 14 The following trace amounts of N are contained. Ar gas is also introduced into the reactor, but Ar gas is very inactive at a temperature of about 200 ° C., so the contribution of Ar gas is very small.

In the present embodiment, HfO ₂ is used as a material for the high-k gate insulating film (that is, the high-k layer 16 therein). However, instead of this, other metal oxides, specifically, Zr oxide (ZrO ₂ ), TiO ₂ , Ta ₂ O ₅ , La ₂ O ₃ or Al ₂ O having the same properties as Hf are used. ₃ or the like, the relationship between the thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 is T1 / (T1 + T2) ≦ 0.3 (more preferably T1 / (T1 + T2) ≦ 0. As long as the relationship (2) is satisfied, a dramatic improvement effect similar to that of the present embodiment occurs in the reliability lifetime of the high-k gate insulating film. In particular, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high-k layer 16 is larger than 7.0. If the average value .epsilon.2 _av dielectric .epsilon.2 is and 18.0 or less at 12.0 or more, special effects such as the following are obtained. That is, since the relative dielectric constant difference between the high-k layer 16 and the interface layer 15 is limited within a predetermined range, the electric field concentration on the interface layer 15 during voltage application is further relaxed, and the high-k layer The reliability of the gate insulating film can be further improved.

In the present embodiment, as a material of the high-k gate insulating film (that is, the high-k layer 16 therein), the composition is M _X Si _Y O (where M represents one metal, X> 0, Y > 0)) (which may contain elements other than metal, silicon and oxygen), such as Hf silicate (Hf _X Si _Y O ₂ ) or Zr silicate (Zr _X Si _Y O ₂ ) As long as the relationship of the ratio T1 / (T1 + T2) ≦ 0.3 (preferably the relationship of T1 / (T1 + T2) ≦ 0.2) is satisfied, the reliability lifetime of the high-k gate insulating film is The dramatic improvement effect similar to this embodiment is produced. In particular, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, the relative dielectric constant ε2 of the high-k layer 16 is larger than 7.0, and the high-k layer 16 is 0. In the case of the metal silicate M _X Si _Y O satisfying the relationship of 20 ≦ Y / (X + Y) ≦ 0.30, the following special effects can be obtained. That is, the relative dielectric constant difference between the high-k layer 16 and the interface layer 15 is smaller than when a complete metal oxide not containing silicon is used. As a result, the reliability of the high-k gate insulating film can be further improved.

By the way, when forming an Hf silicate film, for example, instead of the HfO ₂ film 14 of the present embodiment, the following method can be used. That is, Hft-butoxide (C ₁₆ H ₃₆ HfO ₄ ) which is a liquid Hf source and TDEAS (Tetrakis Diethyl Amino Silicon: Si [N (C ₂ H ₅ ) ₂ ] ₄ ) which is a Si source are vaporized, and the carrier An Hf silicate film can be formed by introducing the N ₂ gas, which is a gas, into the reaction furnace and then performing a CVD process at a temperature of about 300 to 500 ° C. At this time, the composition of the Hf silicate film can be changed by adjusting the mixing ratio of the Hf source and the Si source or the temperature of the CVD process. Further, in order to improve the growth rate or film quality of the Hf silicate film, dry O ₂ gas may be introduced into the reaction furnace.

  In the present embodiment, the Si substrate 11 is used as the substrate, but instead of this, another semiconductor substrate such as a SiGe substrate or a SiC substrate may be used.

  In the present embodiment, a Poly-Si gate electrode is used as the gate electrode 17, but a metal gate electrode may be used instead. Specifically, a metal gate electrode having a laminated structure of a TiN film and an Al film or a single layer structure of a TaN film may be formed by using, for example, PVD (physical vapor deposition) by Ar sputtering.

  The present invention is very useful when applied to a semiconductor device having a gate insulating film made of a high dielectric material.

The reliability lifetime of the high-k gate insulating film and the ratio of the interface layer thickness T1 to the total thickness of the high-k gate insulating film (T1 + T2) (where T2 is the physical thickness of the high-k layer) It is a figure which shows the result of having investigated the correlation of these using simulation. The reliability lifetime of the high-k gate insulating film and the ratio of the interface layer thickness T1 to the total thickness of the high-k gate insulating film (T1 + T2) (where T2 is the physical thickness of the high-k layer) It is a figure which shows the result of having investigated this correlation by experiment. (A)-(e) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. (A) is a figure which shows the high-resolution cross-sectional TEM image of the semiconductor device which concerns on one Embodiment of this invention, (b) is a figure which shows the high-resolution cross-sectional TEM image of the semiconductor device which concerns on a comparative example. It is sectional drawing of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Si substrate 12 Element isolation insulating film 13 Si ₃ N ₄ film 14 HfO ₂ film 15 Interface layer 16 high-k layer 17 Gate electrode 21 Si substrate 25 Interface layer 26 high-k layer 27 Gate electrode _RD device region

Claims (37)

A semiconductor device having a high dielectric constant insulating film formed on a semiconductor substrate,
The high dielectric constant insulating film is
An interface layer formed at the interface with the semiconductor substrate;
A high dielectric constant layer formed on the interface layer and having a higher dielectric constant than the interface layer;
The interface layer thickness T1 and the high dielectric constant layer thickness T2 are:
Satisfies the relationship of T1 / (T1 + T2) ≦ 0.3,
The semiconductor device, wherein the high dielectric constant layer includes a first metal and nitrogen. A semiconductor device having a high dielectric constant insulating film formed on a semiconductor substrate,
The high dielectric constant insulating film is
An interface layer formed at the interface with the semiconductor substrate;
A high dielectric constant layer formed on the interface layer and having a higher dielectric constant than the interface layer;
The interface layer thickness T1 and the high dielectric constant layer thickness T2 are:
Satisfies the relationship of T1 / (T1 + T2) ≦ 0.3,
The high dielectric constant layer includes any one of Hf, Zr, or other first metal, and carbon and hydrogen,
The high dielectric constant layer has a SiO ₂ equivalent film thickness of 3.0 nm or less.   The relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric layer is larger than 7.0. The semiconductor device described.   4. The semiconductor device according to claim 3, wherein a relative dielectric constant ε2 of the high dielectric constant layer is greater than 7.0 and 18.0 or less.   5. The semiconductor device according to claim 4, wherein a relative dielectric constant ε <b> 2 of the high dielectric constant layer is 12.0 or more and 18.0 or less.   The semiconductor device according to claim 1, wherein the high dielectric constant layer includes an oxide of the first metal.   The semiconductor device according to claim 1, wherein the high dielectric constant layer is a silicate further including silicon and oxygen. When the composition of the high dielectric constant layer is M _X Si _Y O (M is the first metal, X> 0, Y> 0), X and Y are 0.20 ≦ Y / (X + Y) ≦ The semiconductor device according to claim 7, wherein a relationship of 0.30 is satisfied.   The semiconductor device according to claim 1, wherein the first metal is Hf or Zr.   The semiconductor device according to claim 1, wherein the first metal is Ti, Ta, La, or Al.   The semiconductor device according to claim 2, wherein the high dielectric constant layer contains nitrogen.   The semiconductor device according to claim 1, wherein the high dielectric constant layer has a nitrogen concentration of 4/7 or less in terms of an atomic ratio.   The semiconductor device according to claim 12, wherein the high dielectric constant layer has a nitrogen concentration of 2 atomic% or less.   The semiconductor device according to claim 1, wherein a nitrogen concentration in the vicinity of the upper surface of the high dielectric constant layer is higher than a nitrogen concentration in the vicinity of the lower surface of the high dielectric constant layer. T1 and T2 are
The semiconductor device according to claim 1, wherein a relationship of T1 / (T1 + T2) ≦ 0.2 is satisfied.   The semiconductor device according to claim 1, wherein the interface layer contains nitrogen.   The semiconductor device according to claim 16, wherein the nitrogen concentration in the interface layer is 4/7 or less in terms of atomic ratio.   The semiconductor device according to claim 1, wherein the high dielectric constant layer contains carbon and hydrogen.   19. The semiconductor device according to claim 2, wherein the concentration of carbon and hydrogen in the high dielectric constant layer is 2 atomic% or less. The semiconductor device according to claim 1, wherein the high dielectric constant layer has a SiO ₂ equivalent film thickness of about 3.0 nm. The semiconductor device according to claim 1, wherein the high dielectric constant layer has a SiO ₂ equivalent film thickness of 3.0 nm or less. The semiconductor device according to claim 2 or 21, wherein the high dielectric constant layer has a SiO ₂ equivalent film thickness of 1.5 nm or more and 3.0 nm or less. The semiconductor device according to claim 2 or 21, wherein the high dielectric constant layer has a SiO ₂ equivalent film thickness of about 1.5 nm. The semiconductor device according to claim 2, wherein the high dielectric constant layer has a SiO ₂ equivalent film thickness of less than 1.5 nm.   25. The semiconductor device according to claim 1, wherein the high dielectric constant insulating film has a thickness of 3.3 nm or less.   26. The semiconductor device according to claim 25, wherein a thickness of the high dielectric constant insulating film is not less than 3.0 nm and not more than 3.3 nm.   26. The semiconductor device according to claim 25, wherein a thickness of the high dielectric constant insulating film is 3.0 nm or less.   28. The semiconductor device according to claim 1, further comprising a gate electrode containing polysilicon on the high dielectric constant insulating film.   The semiconductor device according to claim 1, further comprising a metal gate electrode on the high dielectric constant insulating film.   30. The semiconductor device according to claim 29, wherein the metal gate electrode includes at least one of Ti, Al, or Ta.   30. The semiconductor device according to claim 29, wherein the metal gate electrode includes TiN.   30. The semiconductor device according to claim 29, wherein the metal gate electrode contains TaN.   The semiconductor device according to claim 1, wherein the semiconductor substrate is a Si substrate.   The semiconductor device according to claim 1, wherein the semiconductor substrate is a SiC substrate.   The semiconductor device according to claim 1, wherein the semiconductor substrate contains Ge.   36. The semiconductor device according to claim 35, wherein the semiconductor substrate is a SiGe substrate.   The semiconductor device according to claim 1, wherein the high dielectric constant layer has a crystallized portion and a crystal grain boundary.