JP2008091556A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device using a lanthanum aluminum oxide as an insulation film which has a gate electrode that satisfies characteristics required for an electrode to be stacked on the insulation film and never deteriorates the characteristics of the insulation film over various semiconductor device manufacturing processes and which has a stack structure that ensures semiconductor device miniaturization. <P>SOLUTION: In a CMOS circuit concerning one embodiment of this invention, nMIS comprises a gate insulation film 19 formed of a lanthanum aluminum oxide, a gate electrode 21 formed of a lanthanum aluminum alloy expressed by LaxAl1-x (0.21≤x≤0.33), and a source and drain region 35, while pMIS comprises a gate insulation film 19 formed of a lanthanum aluminum oxide and a gate electrode 21 formed of a lanthanum aluminum alloy expressed by LaxAl1-xNyHz (0.21≤x≤0.33, 0.15≤y≤0.5, and 0≤z≤0.1). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a stack structure of an insulating film and an electrode.

  For example, the operating frequency of a central processing unit of a personal computer is improved year by year, and the degree of integration in an integrated circuit constituting the central processing unit is also increasing year by year. For such progress, technological development for miniaturizing elements used in integrated circuits such as field effect transistors (FETs) is essential.

For example, the gate insulating film of a MIS type FET that is required to have high quality is required to have a thickness of several atomic layers as the circuit is miniaturized, and the disturbance energy to the gate insulating film atoms due to the gate electric field is about 1000 ° C. The situation reaches the level. For example, considering 1400 ° C., which is the melting point of SiO ₂ conventionally used as a gate insulating film, it can be easily understood that the physical limit is clearly approaching the electric field applied to the gate insulating film. .

  As a means to alleviate the electric field applied to the gate insulating film by avoiding such physical limitations, the gate insulating film having a high dielectric constant is used to keep the effective electric field applied inside the gate insulating film small. Techniques for applying a high electric field to the channel have been studied.

As the gate insulating film material having such a high dielectric constant, a gate insulating film made of HfSiON is most promising at present. Furthermore, lanthanum aluminum oxides such as LaAlO ₃ are used as gate insulating film materials having a higher dielectric constant, a larger band gap, and an appropriate value for the band offset energy than silicon. Group 3 elements—aluminum oxides and oxynitrides thereof have begun to be studied as potential gate insulating film candidates in the future (see Patent Document 1).

However, in the stack structure of the gate insulating film using such a Group 3 element-aluminum oxide or its oxynitride and the gate insulating film, these compounds contain highly reactive elements, so that the CMOS After various process steps, for example, a heat treatment step, a chemical treatment step, a vacuum treatment step, etc. (up to about 950 ° C.), it is desirable that the constituent elements of the gate electrode infiltrate into the gate insulating film and lower the dielectric constant of the gate insulating film. There is no concern to have an impact. For example, if polycrystalline silicon is used as the gate electrode and LaAlO ₃ is used as the gate insulating film, Si has a high affinity with La. Therefore, Si is infiltrated into the gate insulating film to lower the dielectric constant. There was a problem of deteriorating.

  On the other hand, in the memory cell stack structure of flash memory, the use of a high dielectric constant insulating film is being studied in order to increase the capacity of the interelectrode insulating film (the insulating film between the floating gate electrode and the control electrode). Group 3 elements-aluminum oxides and oxynitrides thereof are also candidates (see Patent Document 2).

However, similarly to the MIS transistor described above, even in the stack structure of the gate insulating film and the floating gate electrode and / or the control electrode, the electrode constituent element (for example, Si of polycrystalline silicon) is insulated between the electrodes in the manufacturing process of the semiconductor device. There is concern about the problem of infiltration into the membrane.
JP 2005-079390. JP 2006-210518 A (refer to the fourth embodiment)

  The present invention relates to a semiconductor device such as a MISFET having an insulating film and an electrode stack cell structure using a Group 3 element such as lanthanum aluminum oxide-aluminum oxide or oxynitride as an insulating film, and a memory cell of a flash memory. In addition, it is possible to find a gate electrode that satisfies the necessary conductivity and work function as an electrode laminated on the insulating film and does not deteriorate the characteristics of the insulating film even through various semiconductor device manufacturing processes, and can cope with miniaturization. An object is to provide a semiconductor device having a stack structure.

  In the case where polycrystalline Si is used as an electrode for an insulating film using a Group 3 element-aluminum oxide such as lanthanum aluminum oxide, the present inventors have an affinity between La and Si, In order to prevent Si, which is an electrode material, from infiltrating into the insulating film, it is necessary to form the electrode with a material not containing Si, and moreover than a method using a material having low affinity with La and Al. Rather, we focused on using a material that does not adversely affect the infiltration of the insulating film as a useful solution.

  That is, the present invention provides a semiconductor region, a gate insulating film formed on the semiconductor region using a Group 3 element-aluminum oxide or oxynitride, and formed on the gate insulating film, and LaxAl1-xNyHz. (Wherein 0.21 ≦ x ≦ 0.33, 0 ≦ y ≦ 0.5, 0 ≦ z ≦ 0.1) and a gate electrode using a lanthanum aluminum alloy, and the gate insulating film in the semiconductor region A semiconductor device comprising a MIS field effect transistor having source and drain regions formed on both sides thereof.

  The present invention also provides a semiconductor region, a tunnel insulating film formed on the semiconductor region, a floating gate electrode formed on the tunnel insulating film, a group 3 element formed on the floating gate electrode, -An interelectrode insulating film using aluminum oxide or oxynitride, and a control electrode formed on the interelectrode insulating film, wherein at least one of the floating gate electrode and the control electrode is LaxAl1-xNyHz ( Provided that the nonvolatile memory element is an electrode using a lanthanum aluminum alloy represented by 0.21 ≦ x ≦ 0.33, 0 ≦ y ≦ 0.5, and 0 ≦ z ≦ 0.1). This is a semiconductor device.

  The electrode stacked on the insulating film according to the present invention satisfies the electric conductivity and work function necessary for the electrode, and does not deteriorate the insulating film characteristics in contact with the electrode even after various semiconductor device manufacturing processes. It is possible to provide a semiconductor device that has a high relaxation effect, excellent reliability, and is sufficiently compatible with miniaturization of semiconductor devices.

  In the present invention, a lanthanum aluminum alloy having a composition ratio in a specific range as an electrode stacked on an insulating film using a Group 3 element-aluminum oxide or oxynitride, that is, LaxAl1-xNyHz (where 0.21 ≦ x ≦ 0 .33, 0 ≦ y ≦ 0.5, 0 ≦ z ≦ 0.1) is basically used to avoid the problem of infiltration of the electrode material into the insulating film.

A lanthanum aluminum alloy having this composition ratio has a low enthalpy when alloyed, is chemically stable as compared with a simple substance, and has a melting point of 1200 to 1400 which is much higher than 920 ° C. of the simple substance La and 680 ° C. of the simple substance Al. It rises to about ℃. As a result, resistance to heat treatment necessary for the semiconductor manufacturing process is improved, and infiltration of the electrode constituent atoms into the insulating film is less likely to occur. Even if slight infiltration of atoms occurs at the interface with the insulating film, the constituent elements of the electrode are elements of the same family as the constituent elements of the insulating film, so that fluctuations in the structure, composition, and characteristics of the insulating film are kept low. Insulating film characteristics such as dielectric constant of the insulating film are not deteriorated. In addition, in terms of conductivity (resistivity: 10 ⁻³ to 10 ⁻⁵ Ωcm) and work function (4.0 to 5.0 eV), there is no inferiority as an electrode material compared to conventional materials.

  The lanthanum aluminum alloy according to the present invention may be added with an element other than lanthanum and aluminum for the purpose of adjusting the work function.

  In particular, the use of an alloy containing nitrogen increases the work function (4.8 ± 0.2 eV) and is suitable for the gate electrode of a pMIS transistor, and the alloy is known to be chemically known by Hume-Rosery's law. Since it is stabilized by the effect of affinity, resistance to heat treatment is sufficient and desirable. Further, even when nitrogen is infiltrated into the gate insulating film, an effect of suppressing crystallization of the gate insulating film can be expected.

  Note that a lanthanum aluminum alloy to which nitrogen is not added has a work function (4.2 ± 0.2 eV) and is suitable for a gate electrode of an nMIS transistor.

Furthermore, the lanthanum aluminum alloy according to the present invention may contain hydrogen in addition to nitrogen. Further, both nitrogen and hydrogen may be contained.
The present invention relates to a semiconductor having a stack structure of an insulating film and an electrode such as a stack structure of a gate insulating film and a gate electrode of a MISFET, a floating gate electrode of a memory cell of a flash memory, an interelectrode insulating film, and a stack structure with a control electrode. Applicable to the device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
Next, as a first example of this embodiment, a MISFET including a gate insulating film and a gate electrode according to this embodiment will be described with reference to FIG.

  FIG. 1 is a cross-sectional view showing the main part of the CMOS circuit according to the first embodiment.

  As shown in FIG. 1, the nMISFET is formed on a p-well 15 formed in an element region surrounded by an element isolation region 13 on the substrate 11, and n-type source / drain formed on the surface of the substrate 11. The region 35, the gate insulating film 19, and the gate electrode 21 are included. Sidewall insulating films 33 are formed on the side walls of the gate insulating film 19 and the gate electrode 21. The gate insulating film 19 is provided on the channel region formed between the source / drain regions.

  The pMISFET is formed on the n-well 17 formed in the element region surrounded by the element isolation region 13 on the same substrate 11, and a p-type source / drain region 37 formed on the surface of the substrate 11. A gate insulating film 19 and a gate electrode 23 are included. Sidewall insulating films 33 are formed on the side walls of the gate insulating film 19 and the gate electrode 23. The gate insulating film 19 is provided on the channel region formed between the source / drain regions.

The substrate 11 is made of, for example, silicon. The gate insulating film 19 is made of, for example, LaAlO ₃ . The gate electrode 21 of the nMISFET uses LaAl ₂ alloy. As the gate electrode 23 of the pMISFET, La _0.33 Al _0.66 N _0.4 (a lanthanum aluminum alloy to which nitrogen is added, the nitrogen concentration having a distribution but a rough average value) is used.

Hereinafter, the insulating film according to the present invention will be described. The Group 3 element-aluminum oxide of the present invention may be a complex oxide containing a Group 3 element and aluminum in addition to LaAlO _3. For example, M _p Al _(1-p) O ₃ (where M is a Group 3 element (ie, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y, It is also possible to use any one or more of Sc), 0 ≦ p <1).

When a composite oxide with aluminum such as M _p Al _(1-p) O ₃ is formed, when aluminum composite oxides having the same p but different M are compared, the higher element as the element constituting M To La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y, and Sc, a high dielectric constant is obtained. Accordingly, lanthanum aluminum oxide is particularly desirable. On the other hand, since chemical stability increases in the reverse order to the order described above as M, it is also useful to use an element in the order after La in view of heat resistance.

When the Group 3 element is lanthanum, in addition to LaAlO ₃ , a stable phase such as LaAl ₁₁ O ₁₈ and a quasi-static phase diagram such as La _x Al _1-x O ₃ (where 0 <x <1) There is an unstable phase that does not exist above, but may exist in an amorphous insulating film. Especially, using LaAlO ₃ is a stable phase, its relative dielectric constant is not too small, and absorbs moisture and carbon dioxide gas. It is desirable because the composition has no chemical instability.

Also, those oxides which are added with nitrogen to become oxynitrides are also within the scope of the present invention. For example, M _p Al _(1-p) O ₃ N _q (where M is a Group 3 element (ie, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, It is also possible to use one or more of Yb, Lu, Y, Sc), 0 ≦ p <1, 0 ≦ q ≦ 1). In particular, a gate insulating film made of a Group 3 element-aluminum oxynitride has an advantage of improving heat resistance.

  Hereinafter, the lanthanum aluminum alloy of the electrode according to the present invention will be described in detail.

A phase diagram of the lanthanum aluminum alloy system is shown in FIG. The melting point of La single metal is as low as about 918 ° C., and there is a problem that the reactivity with oxygen and moisture is intense. Even though Al single metal reacts with oxygen or moisture, it does not proceed easily by forming a passive film like Al ₂ O ₃ , but the melting point is even lower at about 680 ° C., so the heat treatment required in the subsequent CMOS process. There is a problem that it is difficult to endure.

On the other hand, as shown in FIG. 2, the lanthanum aluminum alloy according to the present invention, typically, a LaAl ₂ alloy (ie, x = 0.33), a LaAl ₃ alloy (ie, x = 0.25), La ₃ Al ₁₁ There is an alloy (that is, x = 0.21), but the melting point of LaAl ₂ alloy is 1405 ° C., LaAl ₃ alloy is 1170 ° C. or more and phase separation into La ₃ Al ₁₁ and LaAlx, and melting point of La ₃ Al ₁₁ alloy is 1240 Since the temperature rises by being alloyed at about 0 ° C., it is possible to withstand heat treatment necessary for the CMOS process.

Moreover, in the case of a lanthanum aluminum alloy, there is an advantage that the reaction with the insulating film does not easily proceed by forming a LaAlO ₃ -like passivation with respect to oxygen and moisture. At this time, the oxygen is mainly supplied from the lanthanum aluminum oxide gate insulating film during the heat treatment, but the passivation formed by oxidizing the lanthanum aluminum alloy is also LaAlO ₃ , so the gate insulating film is slightly However, the resistance to heat treatment necessary for the CMOS process is sufficient.

  Even if the gate insulating film supplies oxygen enough to slightly oxidize the interface of the lanthanum aluminum alloy, the defect site is slightly increased on the gate electrode side, and the defect site is farthest from the channel region. Therefore, it is possible to make almost no influence on remote Coulomb scattering. Although it is technically possible to form the gate insulating film in an oxygen-rich manner in order to prevent the slight influence of the slight oxygen desorption from the gate insulating film, the gate insulating film As a result, oxygen desorption from the gate insulating film is increased, and it is difficult to obtain a preferable result.

  It is more preferable to use in combination with a technique for suppressing the heat treatment used in the CMOS process up to about 800 ° C.

  Moreover, the enthalpy of a lanthanum aluminum alloy system is shown in FIG. It can be seen that since La and Al become an alloy, the enthalpy is lowered, so that it becomes chemically stable and the reactivity is lowered. Such a decrease in enthalpy due to alloying has an advantage that a chemical reaction with a peripheral material is unlikely to occur in the subsequent CMOS process.

In the lanthanum aluminum alloy according to the present invention, if x is within the composition range of 0.21 ≦ x ≦ 0.33, LaAl ₂ alloy, LaAl ₃ alloy, La ₃ Al ₁₁ alloy, and other intermediates It is also possible to use a simple composition.

  Further, as described above, for the purpose of increasing the work function, these lanthanum aluminum alloys may contain nitrogen or nitrogen and hydrogen.

In lanthanum aluminum alloy according to the present invention, if x is less than 0.21, that is, when La is less than _La 3 _{Al 11 alloy,} since the mixture of La 3 _{Al 11} alloy and Al, alone in the gate electrode Al exists in phase separation. Therefore, there is a problem that the Al portion phase-separated by heat treatment exceeding 680 ° C. melts. When the value of x exceeds 0.33 and is 0.50 or less, that is, when La is greater than LaAl ₂ alloy and La is less than or equal to LaAl alloy, a mixture of LaAl alloy and LaAl ₂ alloy is obtained. Since the LaAl alloy decomposes into a mixture of La simple substance and LaAl ₂ alloy at about 870 ° C., the high reactivity of La simple substance becomes a problem. That is, when x is less than 0.21 or exceeds 0.33, the melting point is lowered, the enthalpy is increased and the chemical becomes unstable. Furthermore, as shown in FIG. 2, the high reactivity of La alone becomes a problem when the value of x exceeds 0.50.

  When introducing nitrogen into the lanthanum aluminum alloy, it is desirable that y indicating the amount of nitrogen introduced be in the range of 0.15 ≦ y ≦ 0.5. Within this value, the electrical conductivity is kept at an appropriate level, so that the operation speed as a CMOS does not decrease, and the work function falls within an appropriate range as pMIS.

  Further, when hydrogen is introduced into the lanthanum aluminum alloy in addition to nitrogen, z indicating the amount of hydrogen introduced is preferably in the range of z ≦ 0.1. This is because if the amount is too large, hydrogen may diffuse and reduce the gate insulating film or the like.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 4 to 8 are manufacturing process cross-sectional views illustrating the method of manufacturing the semiconductor device according to the present embodiment.

  First, as shown in FIG. 4, an element isolation region 13 for separating a pMISFET formation region and an nMISFET formation region is formed in a semiconductor substrate, for example, a silicon substrate 11. The element isolation region 13 is formed by, for example, STI (Shallow Trench Isolation) technology. The element isolation region 13 can also be formed by a LOCOS (Local Oxidation of Silicon) technique.

Thereafter, a p-well 15 is formed in the nMISFET formation region, and an n-well 17 is formed in the pMISFET formation region. Next, impurities are introduced into the p well 15 and the n well 17 in order to adjust the threshold voltage. The p well 15 and the n well 17 can be formed by, for example, an ion implantation method using a mask in which an opening is provided only on each region.
Next, a gate insulating film 19 having a composition of LaAlO _{3 and} a thickness of 3.0 nm is formed on the silicon substrate 11. As a film forming method, a PLD (Plasma Laser Deposition) method using a LaAlO ₃ target was used.

After the LaAlO ₃ gate insulating film 19 was formed, heat treatment was performed at 600 ° C. in an oxygen atmosphere.

Thereafter, an electrode film 21 having a composition of LaAl _{2 to} be a gate electrode was formed to 200 nm on the gate insulating film 19 by a CVD method.

Next, a photoresist was applied on the electrode film 21, and a resist pattern 25 having an opening on the pMISFET formation region was formed by a lithography technique (see FIG. 5). Using this resist pattern 25 as a mask, nitrogen is introduced into the electrode film 21 on the pMISFET formation region by ion implantation, and nitrided to form a gate of nitrogen-containing lanthanum aluminum alloy La _0.33 Al _0.66 N _0.4 An electrode 23 was obtained.

When a La ₃ Al ₁₁ alloy is used for the nMISFET, the La / Al ratio is the same, such as using a nitrogen-containing lanthanum aluminum alloy in which nitrogen is introduced into the La ₃ Al ₁₁ alloy and nitrided as the pMIS gate electrode. A material is desirable because it is simple in the manufacturing process.

In addition to the resist pattern, a hard mask such as Al ₂ O _3, AlN, AlON, SiO _2, SiN, or SiON can be used as the mask. It is more preferable to use a hard mask containing Al.

  As a mechanism for introducing nitrogen, for example, a method of accelerating ionized nitrogen with an electromagnetic field is possible, and for example, a method of reacting with nitrogen excited or activated by ionized plasma or ultraviolet light, or ionized is also possible. It is also possible to use a method in which both mechanisms are used together. There is also a method that uses particles neutralized by stripping electrons from non-ions, but the neutralized particles are in an excited state at a certain rate, and the movement of the neutralized particles themselves Since many particles exhibit high energy, they are essentially included in the same principle as described above. A technique such as ion implantation is also a technique for implanting atoms accelerated by an electric field into a film, and is essentially included in the scope of the above technique.

  When the nitrogen introduction method as in the present embodiment is used, the nitrogen concentration in the electrode has a distribution in the film thickness direction.

  The most typical nitrogen concentration distribution is such that the nitrogen concentration on the side implanted with nitrogen increases, and a peak of the nitrogen concentration occurs near the interface far from the lanthanum aluminum oxide layer in contact with the lanthanum aluminum alloy film. Distribution.

  Alternatively, in order to change the distribution state of the nitrogen concentration, for example, heat treatment at 800 ° C. may be performed after introducing nitrogen, or nitriding may be performed by an apparatus that uses, for example, reactivated nitrogen after the heat treatment. By combining the nitriding treatment and the heat treatment in this way, it is possible to form a concentration distribution in which the nitrogen concentration is highest near the center in the film thickness direction. It is also possible to form a nitrogen concentration peak at the gate insulating film interface due to a nitrogen pile-up phenomenon. It is also possible to form a plurality of nitrogen concentration peaks. It is also possible to obtain a nitrogen concentration distribution in the film thickness direction that does not have a nitrogen concentration peak.

  Note that nitrogen that reaches the oxide of the insulating film and becomes oxynitride is also within the scope of the present invention. A gate insulating film made of lanthanum aluminum oxynitride has an advantage that heat resistance is improved.

  Next, a photoresist is applied on the electrode films 21 and 23, and the photoresist is patterned by a normal lithography technique to form a resist pattern 27 for forming a gate electrode (see FIG. 6).

  The electrode films 21 and 23 are patterned by etching using the resist pattern 27 as a mask to obtain the respective gate electrodes 21 and 23 (see FIG. 7).

  Subsequently, after removing the resist pattern, a resist pattern (not shown) that covers only the formation region of the pMISFET is formed, and impurities are implanted into the formation region of the nMISFET using the gate electrode 21 as a mask. A mold diffusion layer 29 is formed (see FIG. 7). Also, after removing the resist pattern, a resist pattern (not shown) that covers only the nMISFET formation region is formed, and impurities are implanted into the pMISFET formation region using the gate electrode 23 as a mask, thereby reducing the concentration of p A mold diffusion layer 29 is formed (see FIG. 7). Thereafter, the resist pattern is removed.

  Next, sidewalls 33 made of an insulator are formed on the sides of the gate electrodes 21 and 23 using a known technique, as shown in FIG. Then, a resist pattern (not shown) covering the pMISFET formation region is formed, and impurities are implanted into the nMISFET transistor formation region using the gate electrode 21 and the side wall 33 as a mask, whereby the n-type source / drain diffusion layer 35 is formed. (See FIG. 8).

  Further, after removing the resist pattern, a resist pattern (not shown) covering the nMISFET formation region is formed, and impurities are implanted into the pMISFET formation region using the gate electrode 23 and the sidewall 33 as a mask. A source / drain diffusion layer 37 is formed (see FIG. 8).

  Thereafter, by removing the resist pattern, an nMISFET and a pMISFET are completed as shown in FIG.

  In the manufacturing method of the present embodiment, the formation of the gate electrode 21 of the nMISFET and the gate electrode 23 of the pMISFET includes a single film formation process of the electrode film 21, a formation process of the resist pattern 25 for using a mask, and a gate electrode. A resist pattern 27 forming process for cutting out the portion and a gate electrode patterning process are sufficient. For this reason, the number of steps is small and simple as compared with the case where the gate electrode 21 of the nMISFET and the gate electrode 23 of the pMISFET are formed separately.

  Further, regarding the structure of the semiconductor device of the present embodiment, when the state of the interface between the gate electrode and the gate insulating film of each transistor after the CMOS process is evaluated, it is a problem with the conventional polycrystalline silicon electrode, for example, by a cross-sectional TEM Structural changes that cause unevenness reaching several nanometers at the interface due to observed infiltration, for example, a gate insulating film whose dielectric constant estimated by CV measurement is originally about 21 is reduced to 10 or less, leakage current From the increase of several orders of magnitude, the increase of defect levels indicated by hysteresis of several hundred millivolts or more, the displacement of flat band voltage, etc., the drop in channel mobility to less than half as indicated by transistor characteristics, the Weibull plot, etc. The problem of the extreme deterioration of reliability obtained is improved.

  This means that the process window in production on the line is wide and robust. On the other hand, there is also an effect that the effort for optimizing detailed process conditions, that is, a huge development cost can be reduced due to the many common points with the conventional CMOS process.

(Modification)
(1) In the first embodiment, a method using activated nitrogen is adopted in nitriding an alloy having a composition of LaxAl1-x. On the other hand, for example, a nitriding method using ammonia is also applicable. . However, ammonia contains hydrogen atoms, and especially La in the LaAl ₂ electrode reacts with hydrogen, so that the pMIS gate electrode formed in this case contains hydrogen in addition to nitrogen. The work function of a lanthanum aluminum alloy containing nitrogen and hydrogen is also estimated to be about 4.8 eV, and can be used as a gate electrode of a PMISFET.

When nitrogen and hydrogen are introduced, the amount introduced is LaxAl1-xNyHz (where 0.21 ≦ x ≦ 0.33), and 0.15 ≦ y ≦ 0.5 and 0 ≦ z ≦ 0.1. It is desirable that the range is expressed. This is because if there is too much hydrogen, hydrogen diffuses in the subsequent CMOS process, and there is a problem that the insulating film is reduced, for example.

  A concentration distribution in the film thickness direction may be generated in the nitrogen concentration and the hydrogen concentration. Both nitrogen and hydrogen may have the highest concentration in the vicinity of the interface opposite to the gate insulating film, or the nitrogen concentration profile may be steeper than the hydrogen concentration profile.

  Nitrogen may reach the oxide of the insulating film and become oxynitride by a nitriding method using ammonia. Further, even when hydrogen reaches the oxide insulating film of the insulating film, an effect of terminating the dangling bond in the insulating film with hydrogen is generated, which is not a problem.

  (2) In the first embodiment, an alloy having a composition of LaxAl1-x, which is an nMISFET gate electrode composition, is formed in both the nMIS region and the pMIS region, and then the region serving as the pMISFET gate electrode is nitrided to form nitrogen and Although hydrogen is introduced, LaAlN or LaAlHN can be formed directly in the pMIS region.

  (3) In the first embodiment, a lanthanum aluminum alloy is used as the gate electrode in both the pMISFET and nMISFET of the CMOS circuit. Actually, it is desirable to use the lanthanum aluminum alloy according to the present invention to which nitrogen is added as the gate electrode for both pMIS and nMIS. However, in the nMISFET, the insulating film and the lanthanum aluminum alloy according to the present invention may be used as the gate insulating film and the gate electrode. For example, as the pMISFET gate electrode, it is within the scope of the present invention to use an electrode of another material without using this lanthanum aluminum alloy.

  In that case, a noble metal or a noble metal oxide containing at least one of Ru, Rh, Pd, Ag, Re, Os, Ir, Pt, Au, and O, or Ti, Zr, Hf, V, Metal borides, carbides, nitrides, carbonitrides, borocarbides, carbonitride oxides containing at least two of Nb, Ta, Cr, Mo, W, B, C, N, O Etc. Precious metals, precious metal oxides, borides, carbides, nitrides, carbonitrides, borocarbides, carbonitride oxides, etc. listed above have a high work function and many metals with high melting points. Because of its low nature, it can be used as a gate electrode for pMISFET.

  (4) Although the silicon substrate is used in the first embodiment, it is also preferable to use a germanium substrate. In the case of germanium, activation annealing at about 600 ° C., which requires the highest heat treatment, is sufficient. An InAs substrate, InSb substrate, AlInSb substrate, GaN substrate, GaAs substrate, GaP substrate, or the like can also be used. Since these substrates have the advantage of higher carrier mobility than silicon, they are useful for increasing the transistor operation speed. Alternatively, an SiC substrate can be used. Since the SiC substrate has a high withstand voltage, it is useful as a high-power element.

An insulating film and an electrode according to the present invention can also be formed over these substrates, and transistor operation can be performed. Compared to a conventional structure using SiO ₂ as the gate insulating film and polycrystalline silicon as the gate electrode, the gate insulating film can be made thinner, so that a finer device can be manufactured. .

(5) In the first embodiment, PLD was used as a method for forming a lanthanum aluminum oxide, which is an insulating film, but in addition to this, a lanthanum aluminum oxide target such as LaAlO ₃ , La and Al metal A sputtering method using a target can be used, and an MBE (Molecular Beam Epitaxy) method using La and Al metals can also be used. Alternatively _{La [N (SiMe 3) 2} ] as a lanthanum material _{3 (tris (bistrimethylsilylamido) -lanthanum)} , La (thd) 3 (lanthanum beta-diketonate), La {N (SiHMe 2) 2} 3 (THF) 2, [La ((R) -Biphen) {CH (SiMe ₃ ) ₂ }] ₂ is used, a raw material such as Al (CH ₃ ) ₃ is used as an aluminum material, and H ₂ O, ozone, etc. are used as an oxygen source. By adding, it is also possible to produce by CVD (Chemical Vapor Deposition) method or ALD (Atomic Layer Deposition) method.

  In the above lanthanum aluminum oxide film forming method, it is particularly preferable to form the film by sputtering. It is also preferable to use a PLD apparatus that is devised so as to maintain the in-plane uniformity of the substrate. However, in the PLD method, sufficient countermeasures are taken for the safety and health of workers taking into account the danger of infrared lasers. It is essential.

(6) In the first embodiment, the CVD method is used as the film formation method of the lanthanum aluminum alloy, but the PLD method, the sputtering method, the MBE method, and the ALD method can also be used. A method of forming a film under the condition that oxygen is not mixed using the same target or raw material used for forming the LaAlO ₃ film is desirable.

  The same film formation chamber as the apparatus used for the film formation of the insulating film can be used as the apparatus used for the film formation of the electrode, and a different film formation chamber of the apparatus used for the film formation of the gate insulation film can be used. It is also possible to use an apparatus different from the apparatus used for forming the gate insulating film. One of the great advantages is that there are a wide range of film forming methods.

(Second Embodiment)
Next, the capacitor structure will be described with reference to FIG. This structure corresponds to a floating gate and a control gate of a cell transistor of a flash memory, an insulating film therebetween (so-called interelectrode insulating film), and a peripheral portion thereof.

  FIG. 9 is a cross-sectional view showing the main part of the capacitor according to the second embodiment.

As shown in FIG. 9, the capacitor structure includes a substrate 41, a tunnel insulating film 42, a floating electrode 43, an interelectrode insulating film 44, and a control electrode 45 sequentially deposited on the substrate 41.
The substrate 41 is made of, for example, silicon or the like, but is not limited to this, and the substrate described in the first embodiment and the modified example can be used. The tunnel insulating film 42 is made of, for example, amorphous SiON having a thickness of 5 nm, but other materials may be used. Further, as the interelectrode insulating film 44, LaAlO ₃ having a thickness of 21 nm is used in this embodiment, but the Group 3 element-aluminum oxide or oxynitride mentioned in the first embodiment can be used.

The electrodes 43 and 45 are made of La ₃ Al ₁₁ in this embodiment. The material of the electrode composition is selected in consideration of the characteristics required for each electrode. However, if at least one of them is a lanthanum aluminum alloy according to the present invention, the effect of suppressing the deterioration of the insulating film 44 is exhibited.

Next, a manufacturing process of the capacitor according to the second embodiment will be described. First, the substrate 41 is prepared by the same process as in the first embodiment, and then the insulating film 42 is formed by, for example, a CVD method using an organic metal compound in a vapor state, and then oxidized, renitrided, The electrode 43 is formed by, for example, a CVD method using an organic metal compound in a gas phase, and a LaAlO ₃ film as the insulating film 44 is formed by a sputtering method using a plurality of targets. did. The film thickness of LaAlO ₃ was 21 nm. Next, as the electrode 45, La ₃ Al ₁₁ was formed by a CVD method.

  Thereafter, if the source region S and the drain region D are formed on the surface of the substrate 41 so as to sandwich the channel region below the electrode 43 by ion implantation or the like, a cell transistor of the flash memory is formed.

  According to the structure of this embodiment, when the state of the electrode and the interelectrode insulating film interface after the manufacturing process is evaluated, the structure does not change due to infiltration, and the dielectric constant of the interelectrode insulating film is decreased and the defect level is increased. In addition, there is almost no increase in leakage current or leakage current, and there is no deterioration that the retention characteristics of the cell become several days or less, or deterioration to a state in which window characteristics such as writing voltage and reading voltage are hardly obtained. .

Sectional drawing which shows the CMOS structure which concerns on 1st Embodiment. La-Al alloy phase diagram. The figure which shows the enthalpy of La-Al alloy type. Sectional drawing which shows the manufacturing process of the CMOS structure which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the CMOS structure which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the CMOS structure which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the CMOS structure which concerns on 1st Embodiment. Sectional drawing which shows the manufacturing process of the CMOS structure which concerns on 1st Embodiment. Sectional drawing which shows the memory cell structure which concerns on 2nd Embodiment.

Explanation of symbols

11 Silicon substrate 13 Element isolation region (STI)
15 p-well 17 n-well 19 gate insulating film 20 dummy gate insulating film 21 gate electrode 22 dummy gate electrode 23 gate electrode 25 resist pattern 27 resist pattern 29 n-type low-concentration diffusion layer 31 p-type low-concentration diffusion layer 33 sidewall 35 n-type Source / drain diffusion layer 37 p-type source / drain diffusion layer 41 Substrate 42 Tunnel insulating film 43 Floating electrode 44 Interelectrode insulating film 45 Control electrode

Claims (7)

A semiconductor region;
A gate insulating film formed on the semiconductor region and using Group 3 element-aluminum oxide or oxynitride;
Formed on the gate insulating film;
LaxAl1-xNyHz
(However, 0.21 ≦ x ≦ 0.33, 0 ≦ y ≦ 0.5, 0 ≦ z ≦ 0.1)
A gate electrode using a lanthanum aluminum alloy represented by:
A semiconductor device comprising: a MIS type field effect transistor comprising source and drain regions formed on both sides of the gate insulating film in the semiconductor region. a p-type semiconductor region;
A first gate insulating film formed on the p-type semiconductor region and using a Group 3 element-aluminum oxide or oxynitride;
Formed on the first gate insulating film;
LaxAl1-x
(However, 0.21 ≦ x ≦ 0.33)
A first gate electrode using a lanthanum aluminum alloy represented by:
A semiconductor device comprising: an nMIS field effect transistor having an n-type source and an n-type drain region formed on both sides of the first gate insulating film in the semiconductor region. an n-type semiconductor region;
A second gate insulating film formed on the n-type semiconductor region and using Group 3 element-aluminum oxide or oxynitride;
Formed on the second gate insulating film;
LaxAl1-xNyHz
(However, 0.21 ≦ x ≦ 0.33, 0.15 ≦ y ≦ 0.5, 0 ≦ z ≦ 0.1)
A second gate electrode using a lanthanum aluminum alloy represented by:
A semiconductor device comprising a pMIS field effect transistor having a p-type source and a p-type drain region formed on both sides of the gate electrode of the semiconductor region. a p-type semiconductor region;
A first gate insulating film formed on the p-type semiconductor region and using a Group 3 element-aluminum oxide or oxynitride;
Formed on the first gate insulating film;
LaxAl1-x
(However, 0.21 ≦ x ≦ 0.33)
A first gate electrode using a lanthanum aluminum alloy represented by:
An nMIS field effect transistor comprising an n-type source and an n-type drain region formed on both sides of the first gate insulating film of the p-type semiconductor region;
an n-type semiconductor region;
A second gate insulating film formed on the n-type semiconductor region and using Group 3 element-aluminum oxide or oxynitride;
Formed on the second gate insulating film;
LaxAl1-xNyHz
(However, 0.21 ≦ x ≦ 0.33, 0.15 ≦ y ≦ 0.5, 0 ≦ z ≦ 0.1)
A second gate electrode using a lanthanum aluminum alloy represented by:
A semiconductor device comprising: a CMOS circuit including a pMIS field effect transistor including a p-type source and a p-type drain region formed on both sides of the second gate insulating film in the n-type semiconductor region. A semiconductor region;
A tunnel insulating film formed on the semiconductor region;
A floating gate electrode formed on the tunnel insulating film;
An interelectrode insulating film formed on the floating gate electrode and using a Group 3 element-aluminum oxide or oxynitride;
A control electrode formed on the interelectrode insulating film,
At least one of the floating gate electrode and the control electrode is
LaxAl1-xNyHz
(However, 0.21 ≦ x ≦ 0.33, 0 ≦ y ≦ 0.5, 0 ≦ z ≦ 0.1)
A non-volatile memory element that is an electrode using a lanthanum aluminum alloy represented by the formula:   5. The semiconductor device according to claim 3, wherein the second gate electrode uses a film obtained by nitriding nitrogen activated with respect to a lanthanum aluminum alloy.   5. The semiconductor device according to claim 3, wherein the second gate electrode is a film obtained by nitriding a lanthanum aluminum alloy with ammonia.

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