WO2017009738A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2017009738A1
WO2017009738A1 PCT/IB2016/054012 IB2016054012W WO2017009738A1 WO 2017009738 A1 WO2017009738 A1 WO 2017009738A1 IB 2016054012 W IB2016054012 W IB 2016054012W WO 2017009738 A1 WO2017009738 A1 WO 2017009738A1
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insulator
transistor
conductor
semiconductor
region
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PCT/IB2016/054012
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French (fr)
Japanese (ja)
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岡崎豊
下村明久
山出直人
竹下智也
田中哲弘
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株式会社半導体エネルギー研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present invention relates to a transistor, a semiconductor device, and a manufacturing method thereof, for example.
  • the present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, a processor, and an electronic device.
  • the present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, an imaging device, or an electronic device.
  • the present invention relates to a driving method of a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.
  • transistors using an oxide semiconductor have attracted attention.
  • a transistor using an oxide semiconductor is known to have extremely small leakage current in a non-conduction state.
  • a low power consumption CPU using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).
  • an impurity may be added using the gate electrode as a mask.
  • the impurity can be added by, for example, ion implantation.
  • the transistor is miniaturized, the height of the gate electrode is reduced, and thus the gate electrode is easily penetrated during ion implantation.
  • an object of one embodiment of the present invention is to provide a transistor having favorable electric characteristics by suppressing ion penetration of a conductor used for a gate electrode.
  • Another object is to provide a transistor having stable electrical characteristics. Another object is to provide a transistor with low leakage current during non-conduction. Another object is to provide a transistor having high frequency characteristics. Another object is to provide a transistor having normally-off electrical characteristics. Another object is to provide a transistor with a small subthreshold swing value. Another object is to provide a highly reliable transistor.
  • Another object is to provide a semiconductor device including the transistor. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. Another object is to provide a new module. Another object is to provide a novel electronic device.
  • One embodiment of the present invention includes a semiconductor including first to third portions, a first insulator over the semiconductor, and a first conductor over the first insulator.
  • the conductor has a region overlapping with the first portion.
  • the first conductor includes tungsten (W), silicon (Si), carbon (C), germanium (Ge), tin (Sn), aluminum ( A region having one or more elements selected from Al) or nickel (Ni),
  • the second portion includes one or more of phosphorus, boron, nitrogen, argon, or xenon, and
  • the portion includes at least one of phosphorus, boron, nitrogen, argon, and xenon, and the first conductor is a semiconductor device having a region that is amorphous.
  • One embodiment of the present invention is a semiconductor device in which the first conductor has a region in which a silicon concentration obtained by Rutherford Backscattering Spectroscopy (RBS) is 5 atomic% or more and 70 atomic% or less.
  • RBS Rutherford Backscattering Spectroscopy
  • One embodiment of the present invention is a semiconductor device in which the first conductor has a region containing silicon and oxygen on the surface, and the thickness of the region is 0.2 nm to 20 nm.
  • One embodiment of the present invention is a semiconductor device in which the semiconductor includes an oxide semiconductor.
  • a semiconductor is formed, a first insulator is formed over the semiconductor, a first conductor is formed over the first insulator, and the first conductor is used as a mask.
  • One or more of phosphorus (P), boron (B), nitrogen (N), argon (Ar), or xenon (Xe) is added to the semiconductor, and the first conductor is tungsten, silicon, carbon, germanium , One or more elements selected from tin or nickel, and the first conductor is a method for manufacturing a semiconductor device having a region that is amorphous.
  • One embodiment of the present invention is a method for manufacturing a semiconductor device, in which the addition is performed by ion implantation.
  • One embodiment of the present invention is a method for manufacturing a semiconductor device in which the first conductor is formed by a sputtering method.
  • Another embodiment of the present invention is a method for manufacturing a semiconductor device in which the first conductor is formed using a metal CVD method.
  • a transistor having favorable electrical characteristics can be provided in which ion penetration of a conductor used for a gate electrode is suppressed.
  • a transistor having stable electrical characteristics can be provided.
  • a transistor with low leakage current when not conducting can be provided.
  • a transistor having high frequency characteristics can be provided.
  • a transistor having normally-off electrical characteristics can be provided.
  • a transistor with a small subthreshold swing value can be provided.
  • a highly reliable transistor can be provided.
  • a semiconductor device including the transistor can be provided.
  • a module including the semiconductor device can be provided.
  • an electronic device including the semiconductor device or the module can be provided.
  • a novel semiconductor device can be provided.
  • a new module can be provided.
  • a novel electronic device can be provided.
  • FIGS. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS.
  • FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation.
  • 6A and 6B are cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a top view illustrating a semiconductor device according to one embodiment of the present invention.
  • 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a perspective view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 4A and 4B are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 11 is a perspective view illustrating an electronic device according to one embodiment of the present invention. The figure explaining the XRD result of a sample.
  • the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential).
  • a voltage can be rephrased as a potential.
  • the potential (voltage) is relative and is determined by a relative magnitude from a reference potential. Therefore, even when “ground potential” is described, the potential is not always 0V.
  • the lowest potential in the circuit may be the “ground potential”.
  • an intermediate potential in the circuit may be a “ground potential”. In that case, a positive potential and a negative potential are defined based on the potential.
  • a semiconductor impurity means, for example, a component other than the main component constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic% is an impurity.
  • impurities for example, DOS (Density of State) may be formed in a semiconductor, carrier mobility may be reduced, and crystallinity may be reduced.
  • examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and components other than main components Examples include transition metals, and in particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like.
  • oxygen vacancies may be formed by mixing impurities such as hydrogen, for example.
  • impurities such as hydrogen, for example.
  • examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
  • the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed
  • the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different).
  • the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible.
  • the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.
  • an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is expressed as “enclosed channel width ( SCW: Surrounded Channel Width).
  • SCW Surrounded Channel Width
  • channel width in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width.
  • channel width in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.
  • the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.
  • A when A is described as having a shape protruding from B, in a top view or a cross-sectional view, it indicates that at least one end of A has a shape that is outside of at least one end of B. There is a case. Therefore, when it is described that A has a shape protruding from B, for example, in a top view, it can be read that one end of A has a shape outside of one end of B.
  • semiconductor in the case where the term “semiconductor” is simply used, it may be replaced with various kinds of semiconductors.
  • a group 14 semiconductor such as silicon and germanium, an oxide semiconductor, silicon carbide, germanium silicide, gallium arsenide, indium phosphide, zinc selenide, cadmium sulfide, and other compound semiconductors and organic semiconductors can be used. .
  • parallel refers to a state in which two straight lines are arranged at an angle of ⁇ 10 ° to 10 °. Therefore, the case of ⁇ 5 ° to 5 ° is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° to 30 °.
  • Vertical refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.
  • substantially vertical means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
  • FIG. 1A is a top view of the transistor 10.
  • FIG. 1B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG.
  • FIG. 1C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG.
  • FIG. 1B illustrates the structure of the transistor 10 in the channel length direction
  • FIG. 1C illustrates the structure of the transistor 10 in the channel width direction.
  • the channel length direction of a transistor means a direction in which carriers move between a source (source region or source electrode) and a drain (drain region or drain electrode), and the channel width direction is in a plane parallel to the substrate.
  • FIG. 1A Means a direction perpendicular to the channel length direction.
  • FIG. 1A omits some components (such as an insulating film functioning as a protective insulating film) of the transistor 10 in order to avoid complexity.
  • the top view of the transistor may be illustrated with some components omitted in the following drawings as in FIG.
  • the transistor 10 includes a semiconductor 106b, a conductor 114, an insulator 106a, an insulator 106c, an insulator 112, and an insulator 116.
  • the semiconductor 106b is disposed on the insulator 106a
  • the insulator 106c is disposed on the semiconductor 106b
  • the insulator 112 is disposed on the insulator 106c
  • the conductor 114 is disposed on the insulator 112.
  • the insulator 116 is provided over the conductor 114.
  • the insulator 116 has a region in contact with the top surface of the insulator 106c.
  • the semiconductor 106b overlaps with the conductor 114 with the insulator 106c and the insulator 112 interposed therebetween.
  • the outer periphery of the insulator 106a substantially matches the outer periphery of the semiconductor 106b, and the outer periphery of the insulator 106c is located outside the outer periphery of the insulator 106a and the semiconductor 106b. It is preferable.
  • the transistor 10 includes an insulator 101, a conductor 102, an insulator 103, and an insulator 104 which are formed over a substrate 100, and the insulator 104.
  • Insulator 106a, semiconductor 106b and insulator 106c formed, insulator 112 and conductor 114 formed on insulator 106c, insulator 116, insulator 118 formed on conductor 114, conductor 108a, a conductor 108b, a conductor 109a, and a conductor 109b.
  • the insulator 101, the insulator 103, the insulator 104, the insulator 106a, the insulator 106c, the insulator 112, the insulator 116, and the insulator 118 can also be referred to as insulating films or insulating layers.
  • the conductor 102, the conductor 108a, the conductor 108b, the conductor 109a, the conductor 109b, and the conductor 114 can also be referred to as conductive films or conductive layers.
  • the semiconductor 106b can also be referred to as a semiconductor film or a semiconductor layer.
  • An insulator 103 is formed over an insulator 101 formed over the substrate 100, and a conductor 102 is formed so as to be embedded in the insulator 103.
  • An insulator 104 is formed over the insulator 103 and the conductor 102.
  • the insulator 101 is preferably an insulator having a blocking effect against oxygen, hydrogen, water, or the like.
  • the insulator 104 is preferably an insulator containing oxygen.
  • An insulator 106a is formed over the insulator 104, a semiconductor 106b is formed in contact with the upper surface of the insulator 106a, and an insulator 106c is formed in contact with the upper surface of the insulator 106a and the upper surface of the semiconductor 106b.
  • the side end of the insulator 106a, particularly the side end in the channel width direction, and the side end of the semiconductor 106b, particularly the side end in the channel width direction, are approximately matched. Further, a side surface end of the semiconductor 106b, particularly a side surface end in the channel width direction, is provided in contact with the insulator 106c.
  • the transistor 10 described in this embodiment is provided so that the semiconductor 106b is surrounded by the insulator 106a and the insulator 106c.
  • the insulator 106a, the semiconductor 106b, and the insulator 106c are preferably formed using an oxide semiconductor. Note that the transistor 10 may not be provided with the insulator 106a or the insulator 106c.
  • the insulator 106a and the insulator 106c may be formed using a material that can function as a conductor or a semiconductor when used alone. However, in the case of forming a transistor by stacking with the semiconductor 106b, carriers flow in the vicinity of the semiconductor 106b, the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106c, and the insulator 106a and the insulator 106c The transistor does not function as a channel of the transistor. Therefore, in this specification and the like, the insulator 106a and the insulator 106c are not described as conductors and semiconductors but as insulators.
  • the outer periphery of the insulator 106c is located outside the outer periphery of the insulator 106a; however, the transistor described in this embodiment is not limited to this. Absent.
  • the outer periphery of the insulator 106a may be positioned outside the outer periphery of the insulator 106c, or the side surface end portion of the insulator 106a and the side surface end portion of the insulator 106c may be approximately matched.
  • a region 126a, a region 126b, and a region 126c are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c.
  • the region 126b and the region 126c have a higher dopant concentration than the region 126a and have low resistance.
  • a dopant may be paraphrased as a donor, an acceptor, an impurity, or an element.
  • the region 126b and the region 127c can function as either one or the other of the source region or the drain region of the transistor 10, respectively.
  • FIG. 1D is an enlarged view of the vicinity of the conductor 114 of the transistor 10 illustrated in FIG.
  • the region 126a is a region that substantially overlaps with the conductor 114. Note that part of the regions 126b and 126c may overlap with part of a region overlapping with the conductor 114 of the semiconductor 106b (also referred to as a channel formation region).
  • region 126b and the region 126c can be formed by ion implantation, ion doping, or the like.
  • the region 126b and the region 126c preferably include one or more of phosphorus, boron, nitrogen, argon, and xenon. Thereby, the resistance values of the region 126b and the region 126c can be reduced.
  • the low resistance region 107a and the low resistance region 107b may be formed in the vicinity of the interface of the insulator 106a, the semiconductor 106b, and the insulator 106c with the insulator 116 (indicated by a dotted line in FIG. 1B).
  • the low resistance region 107a and the low resistance region 107b may include at least one element included in the insulator 116.
  • the conductor 108a and the conductor 108b and the semiconductor 106b, or the conductor 108a and the conductor 108b and the insulator 106c are in contact with each other.
  • the resistance can be reduced. Accordingly, the on-state current of the transistor 10 can be increased.
  • the transistor 10 illustrated in FIGS. 1A to 1D has a structure in which the low-resistance region 107a and the low-resistance region 107b are formed; however, the semiconductor device described in this embodiment is not limited to this. is not. For example, when the resistance of the region 126b and the region 126c is sufficiently low, the low resistance region 107a and the low resistance region 107b may not be formed.
  • the insulator 112 and the conductor 114 are provided so that at least a part thereof overlaps with the conductor 102 and the semiconductor 106b. It is preferable that the side surface end portion of the conductor 114 in the channel length direction and the side surface end portion of the insulator 112 in the channel length direction substantially coincide.
  • the insulator 112 functions as a gate insulating film of the transistor 10
  • the conductor 114 functions as a gate electrode of the transistor 10.
  • the insulator 116 can function as a protective insulating film of the transistor 10, and the insulator 118 can function as an interlayer insulating film of the transistor 10.
  • an insulator having a blocking effect on oxygen is preferably used.
  • the oxygen diffusion coefficient of the insulator 116 be smaller than that of the insulator 118.
  • the semiconductor 106b can be electrically surrounded by an electric field generated by the conductor 102 and the conductor 114 (note that the structure of the transistor that electrically surrounds the semiconductor by the electric field generated from the conductor) Is called a surround channel (s-channel) structure.). Therefore, a channel is formed in the entire semiconductor 106b (upper surface, lower surface, and side surface). In the s-channel structure, a large current can flow between the source and the drain of the transistor, and a current (on-state current) at the time of conduction can be increased.
  • the s-channel structure can be said to be a structure suitable for a miniaturized transistor.
  • a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration.
  • the transistor has a channel length of preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less, and the transistor preferably has a channel width of 40 nm or less, more preferably 30 nm or less, and further Preferably, it has a region of 20 nm or less.
  • a conductor 108a and a conductor 108b are formed in openings provided in the insulator 118, the insulator 116, and the insulator 106c, and the conductor 108a and the conductor 108b are formed in the low resistance region 107a and the low resistance region 107b, respectively. It touches. Further, a conductor 109a is formed over the insulator 118 in contact with the upper surface of the conductor 108a, and a conductor 109b is formed in contact with the upper surface of the conductor 108b.
  • the conductor 108a and the conductor 108b are formed apart from each other, and are preferably formed to face each other with the conductor 114 interposed therebetween as shown in FIG.
  • the conductor 108a functions as one of a source electrode and a drain electrode of the transistor 10
  • the conductor 108b functions as the other of the source electrode and the drain electrode of the transistor 10.
  • the conductor 109a functions as a wiring connected to one of the source electrode and the drain electrode of the transistor 10
  • the conductor 109b functions as a wiring connected to the other of the source electrode and the drain electrode of the transistor 10.
  • the conductor 108a and the conductor 108b are provided in contact with the semiconductor 106b; however, this embodiment is not limited thereto. If the contact resistance between the low resistance region 107a and the low resistance region 107b is sufficiently low, the insulator 106c may have no opening, and the conductor 108a and the conductor 108b may be in contact with the insulator 106c.
  • the conductor 114 preferably includes a region having tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, or nickel. Thereby, an amorphous conductor 114 can be formed.
  • the conductor 114 is preferably a conductor having a region containing tungsten and silicon.
  • the conductor preferably has a region where the silicon concentration obtained by RBS is 5 atomic% or more and 70 atomic% or less.
  • tungsten when tungsten is formed over the surface to be formed by, for example, a sputtering method, a conductor having crystallinity may be obtained. Therefore, the surface flatness of the conductor may be deteriorated.
  • an amorphous conductor can be formed in the transistor 10 by using a conductor having a region including tungsten and silicon as shown in the present invention. Thereby, it is easy to form a conductor having good surface flatness. Further, since the conductor has an amorphous region, penetration of ions due to ion implantation or the like can be suppressed.
  • the size of an insulator, a semiconductor, a conductor, and the like included in the transistor is reduced, and the film thickness is also reduced. Therefore, even when a conductor is used as a mask, ions implanted in ion implantation are likely to penetrate the conductor. However, an amorphous region such as the conductor 114 described in one embodiment of the present invention can be used. By using a conductor having the above, a transistor in which ions are prevented from penetrating through the conductor can be formed.
  • a conductor having a region containing tungsten and silicon preferably has a region containing silicon and oxygen on the surface of the conductor, and the thickness of the region is preferably 0.2 nm to 20 nm.
  • the region can be a region containing a large amount of silicon and oxygen, in which case the region can function as an insulator.
  • the region functions as a barrier layer that suppresses intrusion of oxygen, the entire conductor can be prevented from being oxidized.
  • the conductor 114 by using a conductor as described above for the conductor 114, for example, in the process of manufacturing the transistor 10, when the conductor 114 is exposed to an oxidizing atmosphere by heat treatment, the entire conductor 114 is made. Oxidation can be suppressed. Accordingly, an increase in the resistance value of the conductor can be suppressed, so that a transistor with favorable electrical characteristics (such as on-state current) can be manufactured.
  • the semiconductor 106b is an oxide semiconductor containing indium, for example.
  • the semiconductor 106b preferably contains an element M.
  • the element M preferably represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf. However, the element M may be a combination of a plurality of the aforementioned elements.
  • the element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example.
  • the semiconductor 106b preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.
  • the semiconductor 106b is not limited to the oxide semiconductor containing indium.
  • the semiconductor 106b may be an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like that does not contain indium, such as zinc tin oxide and gallium tin oxide.
  • the insulator 106a and the insulator 106c are oxide semiconductors including one or more elements other than oxygen included in the semiconductor 106b, or two or more elements. Since the insulator 106a and the insulator 106c are composed of one or more elements other than oxygen constituting the semiconductor 106b, or two or more elements, the interface between the insulator 106a and the semiconductor 106b and the interface between the semiconductor 106b and the insulator 106c , Defect levels are difficult to form.
  • the insulator 106a, the semiconductor 106b, and the insulator 106c preferably contain at least indium.
  • the insulator 106a is an In—M—Zn oxide
  • In is preferably less than 50 atomic%
  • M is higher than 50 atomic%
  • more preferably In is 25 atomic%
  • M is higher than 75 atomic%.
  • the semiconductor 106b is an In-M-Zn oxide
  • the In when the sum of In and M is 100 atomic%, the In is preferably higher than 25 atomic%, the M is less than 75 atomic%, and more preferably, In is more than 34 atomic%.
  • High, and M is less than 66 atomic%.
  • the insulator 106c is an In-M-Zn oxide
  • In is preferably less than 50 atomic%
  • M is higher than 50 atomic%, and more preferably In is 25 atomic%. Less than, M is higher than 75 atomic%.
  • the insulator 106c may be formed using the same kind of oxide as the insulator 106a.
  • the insulator 106a and / or the insulator 106c may not contain indium in some cases.
  • the insulator 106a and / or the insulator 106c may be gallium oxide.
  • the number of atoms of each element included in the insulator 106a, the semiconductor 106b, and the insulator 106c may not be a simple integer ratio.
  • the insulator 106c preferably contains indium gallium oxide.
  • the gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.
  • the energy gap of the semiconductor 106b is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.
  • the energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b.
  • the energy gap of the insulator 106c is larger than the energy gap of the semiconductor 106b.
  • the semiconductor 106b an oxide having an electron affinity higher than that of the insulator 106a or the insulator 106c is used.
  • the semiconductor 106b has an electron affinity of 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.15 eV to 0.4 eV, compared to the insulator 106a and the insulator 106c.
  • An oxide is used.
  • the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band. In other words, the energy level at the lower end of the conduction band of the insulator 106a or the insulator 106c is closer to the vacuum level than the energy level at the lower end of the conduction band of the semiconductor 106b.
  • a gate voltage when a gate voltage is applied, a channel is formed in the semiconductor 106b having a high electron affinity among the insulator 106a, the semiconductor 106b, and the insulator 106c. Note that when a high gate voltage is applied, current may flow also in the vicinity of the interface between the insulator 106a and the semiconductor 106b and in the vicinity of the interface between the insulator 106c and the semiconductor 106b.
  • the insulator 106a and the insulator 106c are made of a substance that can function as a conductor, a semiconductor, or an insulator when used alone.
  • a transistor is formed by stacking with the semiconductor 106b, electrons flow in the vicinity of the semiconductor 106b, the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106c, and the insulator 106a and the insulator 106c
  • the transistor does not function as a channel of the transistor. Therefore, in this specification and the like, the insulator 106a and the insulator 106c are not described as semiconductors but are described as insulators.
  • the insulator 106a and the insulator 106c are described as insulators because they have a function similar to that of an insulator compared to the semiconductor 106b. Therefore, the insulator 106a or the insulator 106c is referred to as the semiconductor 106b. In some cases, a substance that can be used in the process is used.
  • the stacked body of the insulator 106a, the semiconductor 106b, and the insulator 106c has a band diagram in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface. Note that the interface between the insulator 106a and the semiconductor 106b or between the insulator 106c and the semiconductor 106b may not be clearly distinguished.
  • the on-state current of the transistor can be increased as the factor that hinders the movement of electrons is reduced. For example, when there is no factor that hinders the movement of electrons, it is estimated that electrons move efficiently. Electron movement is inhibited, for example, even when the physical unevenness of the channel formation region is large.
  • the root mean square (RMS) of the upper surface or the lower surface of the semiconductor 106b formation surface, here, the upper surface of the insulator 106a
  • the roughness may be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, more preferably less than 0.4 nm.
  • the average surface roughness (also referred to as Ra) in the range of 1 ⁇ m ⁇ 1 ⁇ m is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm.
  • the maximum height difference (also referred to as PV) in the range of 1 ⁇ m ⁇ 1 ⁇ m is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and more preferably less than 7 nm.
  • the RMS roughness, Ra, and PV can be measured using a scanning probe microscope system SPA-500 manufactured by SII Nano Technology.
  • the thickness of the insulator 106c is preferably as small as possible.
  • the thickness of the insulator 106c is preferably smaller than the thickness of the insulator 106a and smaller than the thickness of the semiconductor 106b.
  • the insulator 106c having a region of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less may be used.
  • the insulator 106c has a function of blocking elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator from entering the semiconductor 106b in which a channel is formed. Therefore, the insulator 106c preferably has a certain thickness.
  • the insulator 106c having a region with a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more may be used.
  • the insulator 106a is preferably thick.
  • the insulator 106a may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more.
  • the thickness of the insulator 106a By increasing the thickness of the insulator 106a, the distance from the interface between the adjacent insulator 106a to the semiconductor 106b where a channel is formed can be increased.
  • the insulator 106a having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less may be used.
  • Silicon in the oxide semiconductor may serve as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 106b, the better.
  • the semiconductor 106b and the insulator 106a for example, in secondary ion mass spectrometry (SIMS), 1 ⁇ 10 16 atoms / cm 3 or more and 1 ⁇ 10 19 atoms / cm 3 or less, Preferably, it has a region having a silicon concentration of 1 ⁇ 10 16 atoms / cm 3 or more and 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 16 atoms / cm 3 or more and 2 ⁇ 10 18 atoms / cm 3 or less. .
  • SIMS 106b and the insulator 106c in SIMS, 1 ⁇ 10 16 atoms / cm 3 or more and 1 ⁇ 10 19 atoms / cm 3 or less, preferably 1 ⁇ 10 16 atoms / cm 3 or more and 5 ⁇ 10 18
  • the region has a silicon concentration of atoms / cm 3 or less, more preferably 1 ⁇ 10 16 atoms / cm 3 or more and 2 ⁇ 10 18 atoms / cm 3 or less.
  • the insulator 106a and the insulator 106c are 1 ⁇ 10 16 atoms / cm 3 or more and 2 ⁇ 10 20 atoms / cm 3 or less, preferably 1 ⁇ 10 16 atoms / cm 3 or more and 5 ⁇ 10 19 atoms / cm 3 in SIMS.
  • the hydrogen concentration is more preferably 1 ⁇ 10 16 atoms / cm 3 or more and 1 ⁇ 10 19 atoms / cm 3 or less, and further preferably 1 ⁇ 10 16 atoms / cm 3 or more and 5 ⁇ 10 18 atoms / cm 3 or less.
  • the insulator 106a and the insulator 106c are 1 ⁇ 10 15 atoms / cm 3 or more and 5 ⁇ 10 19 atoms / cm 3 or less, preferably 1 ⁇ 10 15 atoms / cm 3 or more and 5 ⁇ 10 18 atoms / cm 3. Or less, more preferably 1 ⁇ 10 15 atoms / cm 3 or more and 1 ⁇ 10 18 atoms / cm 3 or less, and even more preferably 1 ⁇ 10 15 atoms / cm 3 or more and 5 ⁇ 10 17 atoms / cm 3 or less.
  • the insulator 106a, the semiconductor 106b, and the insulator 106c, particularly the semiconductor 106b described in this embodiment are oxide semiconductors with a low impurity concentration and a low density of defect states (the number of oxygen vacancies) is low.
  • it can be called a highly pure intrinsic oxide semiconductor.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states, and thus may have a low density of trap states.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has an extremely small off-state current, an element having a channel width W of 1 ⁇ 10 6 ⁇ m and a channel length L of 10 ⁇ m.
  • the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, it is possible to obtain a characteristic that the off-current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1 ⁇ 10 ⁇ 13 A or less.
  • a transistor in which a channel region is formed in the above-described high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor can be a highly reliable transistor with little variation in electrical characteristics.
  • the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.
  • impurities include hydrogen, nitrogen, alkali metals, and alkaline earth metals.
  • Hydrogen contained in the insulator 106a, the semiconductor 106b, and the insulator 106c reacts with oxygen bonded to a metal atom to be water, and oxygen vacancies are generated in a lattice from which oxygen is released (or a portion from which oxygen is released). Form.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated.
  • a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers.
  • hydrogen trapped in oxygen vacancies may form a shallow donor level with respect to a semiconductor band structure. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on.
  • the insulator 106a, the semiconductor 106b, and the insulator 106c are preferably reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is 2 ⁇ 10 20 atoms / cm 3 or less, preferably 5 ⁇ 10 19 atoms / cm 3 or less, more preferably 1 ⁇ 10 19 atoms / cm 3 or less, 5 ⁇ 10 18 atoms / cm 3 or less, preferably 1 ⁇ 10 18 atoms / cm 3 or less, more preferably 5 ⁇ 10 17 atoms / cm 3 or less, more preferably 1 ⁇ 10 16 atoms / cm 3 or less.
  • the silicon and carbon concentrations in the insulator 106a, the semiconductor 106b, and the insulator 106c, and the silicon and carbon concentrations (concentration obtained by SIMS) in the vicinity of the interface between the insulator 106a, the semiconductor 106b, and the insulator 106c 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the concentration of alkali metal or alkaline earth metal obtained by SIMS is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • concentration of alkali metal or alkaline earth metal in the insulator 106a, the semiconductor 106b, and the insulator 106c is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the insulator 106a, the semiconductor 106b, and the insulator 106c contain nitrogen, electrons serving as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to be normally on. Therefore, nitrogen in the oxide semiconductor film is preferably reduced as much as possible.
  • the nitrogen concentration obtained by SIMS is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
  • the insulator 106a, the semiconductor 106b, and the insulator 106c described in this embodiment are oxides with low impurity concentration, low density of defect states (low oxygen vacancies), and low carrier density. Therefore, contact resistance tends to increase between the conductor 108a and the conductor 108b functioning as a source electrode or a drain electrode.
  • the conductor 108a or the conductor 108b and the insulator 106a, the semiconductor 106b, or the insulator 106c are connected to each other in the region 126b or the region 126c having a low resistance value. The contact resistance can be prevented from increasing.
  • the insulator 106a, the semiconductor 106b, and the insulator 106c are formed with a region 126a, a region 126b, and a region 126c.
  • the region 126b and the region 126c have higher dopant concentration and lower resistance than the region 126a.
  • the region 126a is a region that substantially overlaps the conductor 114
  • the region 126b and the region 126c are regions other than the region 126a.
  • a low resistance region 107a and a low resistance region 107b be formed in the vicinity of the interface of the insulator 106a, the semiconductor 106b, and the insulator 106c with the insulator 116.
  • a dopant or an element contained in the insulator 116 is added to the insulator 106a, the semiconductor 106b, or the insulator 106c, and a defect is formed by the element.
  • Such a defect is caused by, for example, oxygen being extracted by an added dopant or an element added from the insulator 116 to form an oxygen vacancy, or an element added from the dopant or the insulator 116 itself is a carrier. Formed by becoming a source. In such a defect, a donor level is formed and the carrier density is increased. Therefore, regions to which a dopant or an element included in the insulator 116 is added are regions 126b, a region 126c, a low-resistance region 107a, and a low-resistance region 107b. Will function as.
  • the region 126b and the region 126c, in particular, the low resistance region 107a and the low resistance region 107b are formed with many oxygen vacancies.
  • the region 126b, the region 126c, in particular, the low resistance region 107a and the low resistance region 107b are formed with many defects, and thus have lower crystallinity than the region 126a.
  • the regions 126b and 126c are formed by adding a dopant. Therefore, the concentration of the dopant obtained by SIMS analysis in the region 126b and the region 126c is higher than that in the region 126a.
  • Examples of the dopant added to the region 126b and the region 126c include hydrogen, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, boron, magnesium, aluminum, silicon, titanium, vanadium, and chromium.
  • ion implantation or ion doping may be used.
  • the above-described three-layer structure of the insulator 106a, the semiconductor 106b, and the insulator 106c is an example.
  • a two-layer structure in which either the insulator 106a or the insulator 106c is not provided may be employed.
  • a single-layer structure in which both the insulator 106a and the insulator 106c are not provided may be employed.
  • an n-layer structure (n is an integer of 4 or more) including any of the insulators, semiconductors, and conductors exemplified as the insulator 106a, the semiconductor 106b, and the insulator 106c may be used.
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • a non-single-crystal oxide semiconductor a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide OS) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
  • oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors.
  • a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
  • Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.
  • a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor.
  • an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor.
  • an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically similar to an amorphous oxide semiconductor.
  • CAAC-OS First, the CAAC-OS will be described.
  • a CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).
  • CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction)
  • XRD X-ray Diffraction
  • CAAC-OS having an InGaZnO 4 crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method
  • a diffraction angle (2 ⁇ ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO 4 crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface.
  • a peak may also appear when 2 ⁇ is around 36 °.
  • the peak where 2 ⁇ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.
  • FIG. 2E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface.
  • a ring-shaped diffraction pattern is confirmed from FIG. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm.
  • the first ring in FIG. 2E is considered to originate from the (010) plane and the (100) plane of InGaZnO 4 crystal. Further, the second ring in FIG. 2E is considered to be due to the (110) plane and the like.
  • FIG. 3A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface.
  • a spherical aberration correction function was used for observation of the high-resolution TEM image.
  • a high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image.
  • the Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
  • a pellet which is a region where metal atoms are arranged in a layered manner can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc).
  • the CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals).
  • CANC C-Axis aligned nanocrystals.
  • the pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.
  • 3B and 3C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface.
  • 3D and 3E are images obtained by performing image processing on FIGS. 3B and 3C, respectively.
  • an image processing method will be described.
  • an FFT image is obtained by performing a fast Fourier transform (FFT) process on FIG.
  • FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image.
  • IFFT inverse fast Fourier transform
  • the image acquired in this way is called an FFT filtered image.
  • the FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.
  • FIG. 3D the portion where the lattice arrangement is disturbed is indicated by a broken line.
  • a region surrounded by a broken line is one pellet.
  • the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape.
  • the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.
  • FIG. 3E a dotted line is shown between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned.
  • a clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line.
  • a distorted hexagon, pentagon, and / or heptagon can be formed. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.
  • the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as an oxide semiconductor having CAAcrystal (c-axis-aligned ab-plane-anchored crystal).
  • the CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).
  • the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element.
  • an element such as silicon which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor.
  • heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
  • an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like.
  • an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source.
  • oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.
  • a CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8 ⁇ 10 11 / cm 3 , preferably less than 1 ⁇ 10 11 / cm 3 , more preferably less than 1 ⁇ 10 10 / cm 3 , and a carrier of 1 ⁇ 10 ⁇ 9 / cm 3 or more.
  • a dense oxide semiconductor can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
  • the CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.
  • nc-OS is analyzed by XRD.
  • XRD X-ray diffraction
  • FIG. 4B shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam having a probe diameter of 1 nm is incident on the same sample. From FIG. 4B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.
  • the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.
  • FIG. 4D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface.
  • the nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image.
  • a crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor.
  • the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image.
  • the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.
  • the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
  • nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.
  • the nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.
  • FIG. 5 shows a high-resolution cross-sectional TEM image of the a-like OS.
  • FIG. 5A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation.
  • FIG. 5B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁇ ) of 4.3 ⁇ 10 8 e ⁇ / nm 2 .
  • electrons (e ⁇ ) of 4.3 ⁇ 10 8 e ⁇ / nm 2 .
  • the a-like OS has a striped bright region extending in the vertical direction from the start of electron irradiation.
  • the shape of the bright region changes after electron irradiation.
  • the bright region is assumed to be a void or a low density region.
  • the a-like OS Since it has a void, the a-like OS has an unstable structure.
  • the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, a change in structure due to electron irradiation is shown.
  • a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.
  • a high-resolution cross-sectional TEM image of each sample is acquired.
  • Each sample has a crystal part by a high-resolution cross-sectional TEM image.
  • a unit cell of an InGaZnO 4 crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction.
  • the spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO 4 .
  • the lattice fringes correspond to the ab plane of the InGaZnO 4 crystal.
  • FIG. 6 is an example in which the average size of crystal parts (22 to 30 locations) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 6, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative dose of electrons related to the acquisition of the TEM image or the like. From FIG. 6, the crystal part (also referred to as the initial nucleus) having a size of about 1.2 nm at the beginning of observation by TEM has an accumulated electron (e ⁇ ) irradiation dose of 4.2 ⁇ 10 8 e ⁇ / nm. In FIG. 2 , it can be seen that the crystal has grown to a size of about 1.9 nm.
  • FIG. 6 indicates that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose.
  • a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation.
  • the electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 ⁇ 10 5 e ⁇ / (nm 2 ⁇ s), and an irradiation region diameter of 230 nm.
  • the crystal part may be grown by electron irradiation.
  • the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
  • the a-like OS has a lower density than the nc-OS and the CAAC-OS.
  • the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition.
  • the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of single crystals having the same composition.
  • An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.
  • the density of single crystal InGaZnO 4 having a rhombohedral structure is 6.357 g / cm 3 .
  • the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3.
  • the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm 3 or more and 6.3 g / less than cm 3 .
  • oxide semiconductors have various structures and various properties.
  • the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
  • an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • there is a semiconductor substrate having an insulator region inside the semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride examples include a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided on an insulator substrate examples include a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.
  • a substrate in which an element is provided may be used.
  • the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
  • a flexible substrate that can withstand heat treatment at the time of manufacturing the transistor may be used as the substrate 100.
  • a method for providing a transistor over a flexible substrate there is a method in which after a transistor is manufactured over a non-flexible substrate, the transistor is peeled off and transferred to the substrate 100 which is a flexible substrate.
  • a separation layer is preferably provided between the non-flexible substrate and the transistor.
  • a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate 100.
  • the substrate 100 may have elasticity. Further, the substrate 100 may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape.
  • the thickness of the substrate 100 is, for example, 5 ⁇ m to 700 ⁇ m, preferably 10 ⁇ m to 500 ⁇ m, more preferably 15 ⁇ m to 300 ⁇ m.
  • the semiconductor device can be reduced in weight. Further, by reducing the thickness of the substrate 100, there are cases where the glass 100 or the like is stretchable or has a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 100 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.
  • the substrate 100 which is a flexible substrate for example, metal, alloy, resin, glass, or fiber thereof can be used.
  • the substrate 100, which is a flexible substrate is preferable because the deformation due to the environment is suppressed as the linear expansion coefficient is lower.
  • a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less is used.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • aramid has a low coefficient of linear expansion, it is suitable as the substrate 100 that is a flexible substrate.
  • an insulator having a function of blocking hydrogen or water is used as the insulator 101.
  • Hydrogen and water in the insulator provided in the vicinity of the insulator 106a, the semiconductor 106b, and the insulator 106c may be one of the factors that generate carriers in the insulator 106a, the semiconductor 106b, and the insulator 106c. This may reduce the reliability of the transistor 10.
  • a substrate provided with a silicon-based semiconductor element such as a switch element
  • hydrogen is used to terminate dangling bonds of the semiconductor element, and the hydrogen may diffuse to the transistor 10.
  • the insulator 101 having a function of blocking hydrogen or water diffusion of hydrogen or water from the lower layer of the transistor 10 can be suppressed, and the reliability of the transistor 10 can be improved.
  • the insulator 101 preferably has a function of blocking oxygen.
  • oxygen can be effectively supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c, for example.
  • the insulator 101 for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. By using these as the insulator 101, it can function as an insulating film which has an effect of blocking diffusion of oxygen, hydrogen, or water.
  • the insulator 101 for example, silicon nitride, silicon nitride oxide, or the like can be used. By using these as the insulator 101, it can function as an insulating film having an effect of blocking diffusion of hydrogen and water.
  • the conductor 102 preferably overlaps with the semiconductor 106b in a region where at least part of the conductor 102 is sandwiched between the conductor 108a and the conductor 108b.
  • the conductor 102 functions as a back gate of the transistor 10.
  • the threshold voltage of the transistor 10 can be controlled.
  • the transistor 10 is prevented from becoming conductive when the voltage applied to the gate (conductor 114) of the transistor 10 is low, for example, when the applied voltage is 0 V or less. be able to. That is, it becomes easier to shift the electrical characteristics of the transistor 10 in a normally-off direction.
  • the conductor 114 and the conductor 102 may be electrically connected to provide the same potential. Alternatively, the conductor 114 and the conductor 102 may not be electrically connected, and may be configured to apply a potential to each.
  • Examples of the conductor 102 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium,
  • a conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or a stacked layer.
  • it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.
  • the conductor 102 may be a conductor having a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, or nickel.
  • a conductor including tungsten and silicon is preferable.
  • the conductor 102 may be an alloy or a compound, for example, and may be formed as a single layer or a stacked layer.
  • the conductor 102 has a region including silicon and oxygen on the surface of the conductor 102, and the thickness of the region is preferably 0.2 nm to 20 nm.
  • the region can be a region containing a large amount of silicon and oxygen, in which case the region can function as an insulator. Further, since the region functions as a barrier layer, the entire conductor can be prevented from being oxidized.
  • the conductor 102 may be formed by a sputtering method.
  • the film may be formed by a metal CVD (Metal Chemical Vapor Deposition) method.
  • the insulator 105 is provided so as to cover the conductor 102.
  • As the insulator 105 an insulator similar to the insulator 104 or the insulator 112 described later can be used.
  • the insulator 103 is provided so as to cover the insulator 105.
  • the insulator 103 preferably has a function of blocking oxygen.
  • the conductor 102 can be prevented from extracting oxygen from the insulator 104. Accordingly, oxygen can be effectively supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c.
  • an oxide or nitride containing boron, aluminum, silicon, scandium, titanium, gallium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, hafnium, or thallium is used as a single layer or a stacked layer. That's fine.
  • silicon oxide or silicon oxynitride may be used.
  • hafnium oxide or aluminum oxide may be used.
  • the upper surfaces of the insulator 103 and the conductor 102 be planarized by a chemical mechanical polishing (CMP) method or the like to improve planarity. Accordingly, even when the conductor 102 functioning as a back gate is provided, the flatness of the surface over which the semiconductor 106b is formed is not impaired, so that carrier mobility can be improved and the on-state current of the transistor 10 can be increased. .
  • CMP chemical mechanical polishing
  • the conductor 102 is provided so as to be embedded in the insulator 103; however, the structure of the semiconductor device described in this embodiment is not limited thereto, and for example, covers the conductor 102.
  • the insulator 103 may be provided.
  • the insulator 103 preferably has a function of blocking oxygen.
  • the insulator 104 preferably contains a small amount of water or hydrogen contained in the film.
  • the insulator 104 includes, for example, an insulating material including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • the body may be used in a single layer or a stack.
  • the insulator 104 aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.
  • silicon oxide or silicon oxynitride is used.
  • the amount of water or hydrogen contained in the insulator 104 is preferably small.
  • the insulator 104 has a desorption amount of water molecules in a surface temperature range of 100 ° C. or higher and 700 ° C. or lower or 100 ° C. or higher and 500 ° C. or lower in a temperature desorption gas analysis (TDS: Thermal Desorption Spectroscopy).
  • TDS Thermal Desorption Spectroscopy
  • the desorption amount of hydrogen molecules is 1.0 ⁇ 10 13 molecules / cm 2 or more and 1.2 ⁇ 10 15 in the range of the surface temperature of 100 ° C. or more and 700 ° C. or less or 100 ° C. or more and 500 ° C. or less.
  • molecules / cm 2 or less preferably further comprising a 1.0 ⁇ 10 13 molecules / cm 2 or more 9.0 ⁇ 10 14 molecules / cm 2 or less. The details of the method for measuring the amount of released molecules using TDS will be described later.
  • Impurities such as water and hydrogen form defect levels in the insulator 106a, the semiconductor 106b, and the insulator 106c, particularly the semiconductor 106b, and cause fluctuation in electric characteristics of the transistor. Therefore, water, hydrogen, or the like is supplied from the insulator 104 to the semiconductor 106b or the like by reducing the amount of water or hydrogen in the insulator 104 provided under the insulator 106a, the semiconductor 106b, and the insulator 106c. Thus, the formation of defect levels can be reduced. In this manner, by using an oxide semiconductor with a reduced density of defect states, a transistor having stable electric characteristics can be provided.
  • the insulator 104 is preferably formed using a plasma enhanced CVD (PECVD) method in which a high-quality film can be obtained at a relatively low temperature.
  • PECVD plasma enhanced CVD
  • silicon oxide film or the like is formed by a PECVD method
  • silicon hydride or the like is often used as a source gas, and hydrogen, water, or the like is introduced into the insulator 104 at the time of film formation. Therefore, the insulator 104 described in this embodiment is preferably formed using silicon halide as a source gas.
  • silicon halide for example, SiF 4 (silicon tetrafluoride), SiCl 4 (silicon tetrachloride), SiHCl 3 (silicon trichloride), SiH 2 Cl 2 (dichlorosilane) or SiBr 4 (tetrabromide). Silicon) or the like can be used, and SiF 4 (silicon tetrafluoride) is particularly preferable.
  • silicon hydride may be added in addition to silicon halide.
  • the content of hydrogen and water in the insulator 104 can be reduced as compared with the case where only silicon hydride is used as the source gas, and the film formation rate can be improved as compared with the case where only silicon halide is used as the source gas.
  • the insulator 104 may be formed using SiF 4 and SiH 4 as source gases. Note that the ratio of the flow rates of SiF 4 and SiH 4 may be set as appropriate in consideration of the water and hydrogen contents in the insulator 104 and the film formation rate.
  • the insulator 104 is preferably an insulator having excess oxygen.
  • oxygen can be supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c.
  • oxygen vacancies that are defects in the insulator 106a, the semiconductor 106b, and the insulator 106c which are oxide semiconductors can be reduced.
  • the insulator 106a, the semiconductor 106b, and the insulator 106c can be oxide semiconductors with low density of defect states and stable characteristics.
  • excess oxygen refers to oxygen contained in excess of the stoichiometric composition, for example.
  • excess oxygen refers to oxygen released from a film or layer containing the excess oxygen by heating, for example.
  • Excess oxygen can move, for example, inside a film or layer. Excess oxygen may be moved between atoms of a film or layer, or may be moved in a rushing manner while replacing oxygen constituting the film or layer.
  • the insulator 104 having excess oxygen has an oxygen molecule desorption amount of 1.0 ⁇ 10 14 molecules / cm 2 in a surface temperature range of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. in TDS. It is 1.0 ⁇ 10 16 molecules / cm 2 or less, more preferably 1.0 ⁇ 10 15 molecules / cm 2 or more and 5.0 ⁇ 10 15 molecules / cm 2 or less.
  • a method for measuring the amount of released molecules using TDS will be described below by taking oxygen released as an example.
  • the total amount of gas released when the measurement sample is analyzed by TDS is proportional to the integral value of the ionic strength of the released gas.
  • the total amount of gas released can be calculated by comparison with a standard sample.
  • the release amount of oxygen molecules (N O2 ) of the measurement sample can be obtained from the TDS result of the silicon substrate containing hydrogen of a predetermined density as a standard sample and the TDS result of the measurement sample by the following equation. .
  • all of the gases detected at the mass to charge ratio of 32 obtained by the TDS analysis are derived from oxygen molecules.
  • the mass to charge ratio of CH 3 OH is 32 but is not considered here as it is unlikely to exist.
  • oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18 which are isotopes of oxygen atoms are not considered because the existence ratio in nature is extremely small.
  • N O2 N H2 / S H2 ⁇ S O2 ⁇ ⁇
  • N H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density.
  • SH2 is an integral value of ionic strength when a standard sample is analyzed by TDS.
  • the reference value of the standard sample is N H2 / SH 2 .
  • S O2 is an integral value of ion intensity when the measurement sample is analyzed by TDS.
  • ⁇ is a coefficient that affects the ionic strength in TDS.
  • the amount of released oxygen is measured using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. and using a silicon substrate containing a certain amount of hydrogen atoms as a standard sample.
  • TDS part of oxygen is detected as oxygen atoms.
  • the ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above ⁇ includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.
  • N 2 O 2 is the amount of released oxygen molecules.
  • the amount of release when converted to oxygen atoms is twice the amount of release of oxygen molecules.
  • the insulator from which oxygen is released by heat treatment may contain a peroxide radical.
  • a peroxide radical means that the spin density resulting from the peroxide radical is 5 ⁇ 10 17 spins / cm 3 or more.
  • an insulator containing a peroxide radical may have an asymmetric signal with a g value near 2.01 by an electron spin resonance (ESR) method.
  • the insulator 104 may have a function of preventing diffusion of impurities from the substrate 100.
  • the upper surface or the lower surface of the semiconductor 106b preferably has high flatness. For this reason, planarity may be improved by performing a planarization process on the upper surface of the insulator 104 by a chemical mechanical polishing (CMP) method or the like.
  • CMP chemical mechanical polishing
  • the conductor 108a and the conductor 108b can function as either a source electrode or a drain electrode of the transistor 10, respectively.
  • the conductor 108a and the conductor 108b may be formed in a manner similar to that of the conductor 102.
  • the conductor 108a and the conductor 108b are formed so as to be embedded in the insulator 118 and connected to the conductor 109a and the conductor 109b on the insulator 118, the insulator 118, the conductor 108a, and the conductor
  • the upper surface of the body 108b is preferably planarized using a CMP method or the like to improve planarity.
  • the conductor 109a and the conductor 109b function as wirings connected to either the source electrode or the drain electrode of the transistor 10, respectively.
  • a conductor that can be used as the conductor 108a and the conductor 108b may be used.
  • the insulator 112 can function as a gate insulating film of the transistor 10.
  • the insulator 112 may be an insulator having excess oxygen like the insulator 104. By providing such an insulator 112, oxygen can be supplied from the insulator 112 to the insulator 106 a, the semiconductor 106 b, and the insulator 106.
  • an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer.
  • aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.
  • the conductor 114 can function as a gate electrode of the transistor 10.
  • the conductor 114 may be formed in a manner similar to that of the conductor 102.
  • the conductor 114 has a region containing silicon and oxygen on the surface of the conductor 114, and the thickness of the region is preferably 0.2 nm to 20 nm.
  • the region can be a region containing a large amount of silicon and oxygen, in which case the region can function as an insulator. Further, since the region functions as an oxygen barrier layer, oxidation of the entire conductor can be suppressed.
  • the region containing silicon and oxygen can be formed naturally only by exposing the conductor 114 to the atmosphere. It can also be formed intentionally. As a method for intentional formation, for example, heat treatment may be performed in an oxidizing atmosphere. Further, plasma treatment may be performed in an atmosphere containing oxygen. For the plasma treatment, for example, high-density plasma treatment using a power source having a frequency of 2.45 GHz is preferably used.
  • the region containing silicon and oxygen when the region containing silicon and oxygen is formed on the surface of the conductor 114, particularly on the side surface, the region can function as a sidewall.
  • the region containing silicon and oxygen when the region containing silicon and oxygen is formed on the surface of the conductor 114, particularly on the side surface, the region can function as a sidewall.
  • an LDD (Lightly Doped Drain) region or an extension region is formed by causing the region formed on the side surface of the conductor 114 to function as a sidewall. can do.
  • the semiconductor 106b can be electrically surrounded by an electric field generated by the conductor 102 and the conductor 114 (note that the semiconductor is electrically surrounded by an electric field generated from the conductor.
  • the structure of the transistor is called a surrounded channel (s-channel) structure.) Therefore, a channel is formed in the entire semiconductor 106b (upper surface, lower surface, and side surface). In the s-channel structure, a large current can flow between the source and the drain of the transistor, and a current (on-state current) at the time of conduction can be increased.
  • the s-channel structure can be said to be a structure suitable for a miniaturized transistor.
  • a transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration.
  • the transistor has a region with a channel length of preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor has a channel width of preferably 40 nm or less, more preferably 30 nm or less, and more.
  • it has a region of 20 nm or less.
  • the insulator 116 can function as a protective insulating film of the transistor 10.
  • the thickness of the insulator 116 can be set to, for example, 1 nm or more, or 20 nm or more.
  • the insulator 116 is preferably formed so that at least a part thereof is in contact with the top surface of the insulator 104 or the insulator 112.
  • an insulator containing carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used.
  • a layer or a stack may be used.
  • the insulator 116 preferably has an effect of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like.
  • a nitride insulating film can be used.
  • nitride insulating film examples include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.
  • the insulator 116 is preferably formed by a sputtering method, and more preferably by a sputtering method in an atmosphere containing oxygen.
  • a sputtering method By depositing the insulator 116 by a sputtering method, near the surface of the insulator 104 or the insulator 112 at the same time as the film formation (the interface between the insulator 104 or the insulator 112 and the insulator 116 after the insulator 116 is formed) Is added with oxygen.
  • the insulator 116 is an insulator that transmits less oxygen than the insulators 104 and 112, and preferably has an effect of blocking oxygen.
  • the insulator 116 when oxygen is supplied from the insulator 104 and the insulator 112 to the insulator 106a, the semiconductor 106b, and the insulator 106c, the oxygen is released to the outside of the insulator 116. Can be prevented.
  • aluminum oxide is preferable for application to the insulator 116 because it has a high blocking effect of preventing permeation of both hydrogen, moisture and other impurities, and oxygen.
  • the insulator 116 can be formed using an oxide that can be used for the insulator 106a or the insulator 106c. Since these oxides can be formed relatively easily by a sputtering method, oxygen can be effectively added to the insulator 104 and the insulator 112.
  • an oxide insulator containing In is preferably used.
  • an In—Al oxide, an In—Ga oxide, or an In—Ga—Zn oxide may be used.
  • An oxide insulator containing In is suitable for use as the insulator 116 because the number of particles generated when a film is formed by a sputtering method is small.
  • the insulator 118 functions as an interlayer insulating film.
  • the insulator 118 may be formed in a manner similar to that of the insulator 105 or the like.
  • a transistor having favorable electrical characteristics can be provided by suppressing ion penetration of the conductor used for the gate electrode.
  • a transistor having stable electrical characteristics can be provided.
  • a transistor with low leakage current when not conducting can be provided.
  • a transistor having high frequency characteristics can be provided.
  • a transistor having normally-off electrical characteristics can be provided.
  • a transistor with a small subthreshold swing value can be provided.
  • a highly reliable transistor can be provided.
  • FIGS. 7 and 8 are a cross-sectional view in the channel length direction of the transistor and a cross-sectional view in the channel width direction of the transistor, as in FIGS. 1B and 1C.
  • a transistor 11 illustrated in FIGS. 7A and 7B is different from the transistor 10 in that the conductor 102 is not provided.
  • a transistor 12 illustrated in FIGS. 7C and 7D is different from the transistor 10 in that an insulator 140 and an insulator 142 are included.
  • An insulator 140 is formed over the conductor 102, an insulator 142 is formed over the insulator 140, and the insulator 104 is formed over the insulator 142.
  • As the insulator 140 an insulator similar to the insulator 104 can be used.
  • the insulator 142 preferably has a function of blocking oxygen.
  • the conductor 102 can be prevented from extracting oxygen from the insulator 104. Accordingly, oxygen can be effectively supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c.
  • the insulator 142 may include an oxide or nitride containing boron, aluminum, silicon, scandium, titanium, gallium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, hafnium, or thallium.
  • hafnium oxide or aluminum oxide is used.
  • the insulator 142 preferably includes an electron-trapping region.
  • the electrons trapped in the insulator 142 may behave like a negative fixed charge. In this manner, the threshold voltage of the transistor can be controlled by controlling the amount of fixed charges captured by the insulator 142.
  • the transistor 13 illustrated in FIGS. 7E and 7F is different from the transistor 10 in the method for forming the conductor 114.
  • the conductor 114 of the transistor 13 is formed so as to fill an opening provided in the insulator 118.
  • a transistor 14 illustrated in FIGS. 8A and 8B is different from the transistor 10 in that an insulator 115 is provided on a side surface of the conductor 114.
  • the insulator 115 can function as a sidewall.
  • the insulator 115 may be formed in a manner similar to that of the insulator 104 or the like.
  • the region formed on the side surface of the conductor 114 functions as a sidewall, thereby allowing LDD (Lightly Doped Drain). Regions and extension regions can be formed. Note that the region 126d and the region 126e can function as LDD regions.
  • FIG. 8C illustrates an enlarged view of the vicinity of the conductor 114 of the transistor 14 illustrated in FIG.
  • the insulator 106a, the semiconductor 106b, and the insulator 106c of the transistor 14 described in this embodiment include a region 126a, a region 126b, a region 126c, a region 126d, and a region 126e.
  • the region 126b, the region 126c, the region 126d, and the region 126e have a higher dopant concentration and lower resistance than the region 126a.
  • the region 126b and the region 126c have a higher dopant concentration and a lower electrical resistance value than the region 126d and the region 126e.
  • the region 126a is a region that substantially overlaps with the conductor 114.
  • the regions 126d and 126e are regions that substantially overlap with the insulator 115.
  • region 126b, the region 126c, the region 126d, and the region 126e may be formed by adding a dopant by ion implantation, ion doping, or the like.
  • the conductor 114 has a region containing silicon and oxygen on the surface of the conductor 114, and the region can be a region containing a large amount of silicon and oxygen.
  • the region 144 having silicon and oxygen can be provided on the surface of the conductor 114. Note that the region 144 including silicon and oxygen can function as an insulator.
  • the region 144 having silicon and oxygen can be formed naturally only by exposing the conductor 114 to the atmosphere. It can also be formed intentionally. As a method for intentional formation, for example, heat treatment may be performed in an oxidizing atmosphere. Further, plasma treatment may be performed in an atmosphere containing oxygen. For the plasma treatment, for example, high-density plasma treatment using a power source having a frequency of 2.45 GHz is preferably used.
  • the region 144 containing silicon and oxygen can function as a sidewall.
  • a structure in which a conductor including a region including tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, or nickel is used for the gate electrode of the transistor is described.
  • a conductor having a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, or nickel is used as an electrode in a capacitor element such as MIM (Metal-Insulator-Metal). It may be used.
  • MIM Metal-Insulator-Metal
  • a transistor having favorable electric characteristics can be provided by suppressing ion penetration of a conductor used for a gate electrode.
  • the substrate 100 is prepared.
  • the above-described substrate may be used.
  • the insulator 101 is formed.
  • the above insulator may be used.
  • the insulator 101 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method or a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, an atomic layer.
  • the deposition can be performed using an ALD (Atomic Layer Deposition) method or the like.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the PECVD method can obtain a high quality film at a relatively low temperature.
  • the TCVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma.
  • a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge.
  • plasma damage during film formation does not occur, so that a film with few defects can be obtained.
  • the ALD method is also a film forming method that can reduce plasma damage to an object to be processed. Therefore, a film with few defects can be obtained by using the ALD method.
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. This also makes it difficult to form pinholes or the like in the formed film.
  • the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gases.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases.
  • a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film.
  • a film forming apparatus using the ALD method at the time of film formation, one or more kinds of source gases for reaction are simultaneously supplied to a chamber.
  • a film forming apparatus using the ALD method alternately introduces a source gas for reaction (also referred to as a precursor) and a gas functioning as a reactant (also referred to as a reactant) into the chamber, and repeatedly introduces these gases. Film formation is performed.
  • the introduction gas can be switched by switching each switching valve (also referred to as a high-speed valve), for example.
  • film formation is performed in the following procedure.
  • a precursor is introduced into the chamber, and the precursor is adsorbed on the substrate surface (first step).
  • a self-stopping mechanism of the surface chemical reaction acts, and the precursor is not further adsorbed on the precursor layer on the substrate.
  • the appropriate range of the substrate temperature at which the surface chemical reaction self-stopping mechanism operates is also referred to as ALD Window.
  • the ALD window is determined by temperature characteristics of the precursor, vapor pressure, decomposition temperature, and the like.
  • an inert gas such as argon or nitrogen
  • second step is introduced into the chamber, and excess precursors and reaction products are discharged from the chamber (second step).
  • surplus precursors and reaction products may be discharged from the chamber by evacuation instead of introducing the inert gas.
  • a reactant for example, an oxidant (H 2 O, O 3, etc.)
  • H 2 O, O 3, etc. oxidant
  • surplus reactants and reaction products are discharged from the chamber by introducing an inert gas or evacuating (fourth step).
  • the first single layer can be formed on the substrate surface, and the second single layer is laminated on the first single layer by performing the first to fourth steps again. Can do.
  • the first to fourth steps a plurality of times while controlling the gas introduction until the film has a desired thickness, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions, precise film thickness adjustment is possible, which is suitable for manufacturing a fine transistor.
  • the ALD method is a film forming method performed by reacting a precursor using thermal energy. Furthermore, in the above-described reactant reaction, the ALD method in which the reactant is treated in a radical state using plasma may be referred to as a plasma ALD method. On the other hand, the ALD method in which the reaction between the precursor and the reactant is performed with thermal energy may be referred to as a thermal ALD method.
  • the ALD method can form a very thin film with a uniform film thickness.
  • the surface coverage is high even on a surface having irregularities.
  • the film formation by the plasma ALD method enables the film formation at a lower temperature than the thermal ALD method.
  • a film can be formed at a temperature of 100 ° C. or lower without reducing the film formation rate.
  • an oxidizing agent but also many reactants such as nitrogen gas can be used, so that not only oxides but also many types of films such as nitrides, fluorides, and metals can be formed. Can do.
  • plasma can be generated in a state separated from the substrate, such as ICP (Inductively Coupled Plasma).
  • ICP Inductively Coupled Plasma
  • the insulator 103 is formed.
  • the insulator described above may be used as the insulator 103.
  • the insulator 103 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a resist or the like is formed over the insulator 103, and an opening is formed in the insulator 103.
  • the case of simply forming a resist includes the case of forming an antireflection layer under the resist.
  • the resist is removed after the object is processed by etching or the like.
  • plasma treatment and / or wet etching is used for the removal of the resist. Note that plasma ashing is preferable as the plasma treatment.
  • the remaining resist or the like may be removed with hydrofluoric acid or / and ozone water having a concentration of 0.001 wt% or more and 1 wt% or less.
  • a conductor to be the conductor 102 is formed.
  • the conductor to be the conductor 102 the above-described conductor can be used.
  • the conductor to be the conductor 102 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a CMP process is performed to remove the conductor to be the conductor 102 on the insulator 103. As a result, the conductor 102 remains only in the opening formed in the insulator 103.
  • the insulator 104 is formed (see FIGS. 9A and 9B).
  • the above insulator may be used.
  • the insulator 104 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the upper surface or the lower surface of the semiconductor 106b to be formed later preferably has high flatness. Therefore, planarity may be improved by performing a planarization process such as a CMP method on the upper surface of the insulator 104.
  • an insulator to be the insulator 106a is formed in a later step.
  • an insulator, a semiconductor, or a conductor that can be used as the above-described insulator 106a may be used.
  • the insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator to be the insulator 106a is preferably formed by a sputtering method, and more preferably by a sputtering method in an atmosphere containing oxygen.
  • a parallel plate type sputtering apparatus may be used, or a counter target type sputtering apparatus may be used.
  • damage to the formation surface can be reduced, so that a film with high crystallinity is easily obtained. Therefore, in some cases, it is preferable to use an opposing target sputtering apparatus for formation of a CAAC-OS to be described later.
  • oxygen is added to the vicinity of the surface of the insulator 104 (the interface between the insulator 106a and the insulator 104 after the insulator 106a is formed) simultaneously with the film formation.
  • oxygen is added to the insulator 104 as oxygen radicals; however, a state where oxygen is added is not limited thereto.
  • the oxygen may be added to the insulator 104 in a state of oxygen atoms or oxygen ions. By adding oxygen to the insulator 104 in this manner, the insulator 104 can contain excess oxygen.
  • a mixed region may be formed in a region near the interface between the insulator 104 and the insulator 106a.
  • a component constituting the insulator 104 and a component constituting the insulator to be the insulator 106a are included.
  • a semiconductor to be the semiconductor 106b is formed in a later step.
  • a semiconductor that can be used as the semiconductor 106b described above may be used.
  • the semiconductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the formation of the insulator to be the insulator 106a and the formation of the semiconductor to be the semiconductor 106b are continuously performed without being exposed to the air, so that contamination of impurities into the film and the interface can be reduced. Can do.
  • a mixed gas of a rare gas such as argon (in addition, helium, neon, krypton, xenon, etc.) and oxygen as the film forming gas.
  • a rare gas such as argon (in addition, helium, neon, krypton, xenon, etc.) and oxygen
  • oxygen as the film forming gas.
  • the proportion of oxygen in the whole may be less than 50% by volume, preferably 33% by volume or less, more preferably 20% by volume or less, more preferably 15% by volume or less.
  • the substrate temperature may be increased. By increasing the substrate temperature, the migration of sputtered particles on the upper surface of the substrate can be promoted. Therefore, an oxide with higher density and higher crystallinity can be formed.
  • the substrate temperature may be, for example, 100 ° C. or higher and 450 ° C. or lower, preferably 150 ° C. or higher and 400 ° C. or lower, more preferably 170 ° C. or higher and 350 ° C. or lower.
  • the hydrogen concentration in the insulator 106a and the semiconductor 106b which are formed in a later step may be reduced in some cases.
  • oxygen vacancies in the insulator 106a and the semiconductor 106b formed in a later step can be reduced.
  • the heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C.
  • the heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere.
  • an oxidizing gas 10 ppm or more, 1% or more, or 10% or more
  • crystallinity of the insulator 106a and the semiconductor 106b formed in a later step can be increased, impurities such as hydrogen and water can be removed, and the like.
  • an RTA apparatus using lamp heating can also be used.
  • oxygen can be supplied from the insulator 104 to the insulator to be the insulator 106a and the semiconductor to be the semiconductor 106b.
  • oxygen can be supplied to the insulator to be the insulator 106a and the semiconductor to be the semiconductor 106b very easily.
  • the insulator 101 functions as a barrier film that blocks oxygen.
  • oxygen diffused in the insulator 104 can be prevented from diffusing below the insulator 104.
  • oxygen is supplied to the insulator to be the insulator 106a and the semiconductor to be the semiconductor 106b to reduce oxygen vacancies, so that high-purity intrinsic or substantially high-purity intrinsic oxidation with a low defect level density is achieved.
  • It can be a physical semiconductor.
  • high-density plasma treatment or the like may be performed.
  • the high density plasma may be generated using microwaves.
  • an oxidizing gas such as oxygen or nitrous oxide may be used.
  • a mixed gas of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe may be used.
  • a bias may be applied to the substrate.
  • oxygen ions or the like in the plasma can be drawn to the substrate side.
  • the high density plasma treatment may be performed while heating the substrate. For example, when high-density plasma treatment is performed instead of the heat treatment, the same effect can be obtained at a temperature lower than the temperature of the heat treatment.
  • the high density plasma treatment may be performed before the formation of the insulator to be the insulator 106a, may be performed after the insulator 112 is formed, or may be performed after the insulator 116 is formed. .
  • a resist or the like is formed over the semiconductor to be the semiconductor 106b and processed using the resist or the like, so that the insulator 106a and the semiconductor 106b are formed. Note that as illustrated in FIGS. 9C and 9D, the exposed surface of the insulator 104 may be removed when the semiconductor 106b is formed.
  • an insulator to be the insulator 106c is formed in a later step.
  • the insulator the above-described insulator, semiconductor, or conductor may be used.
  • the insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a resist or the like is formed over the insulator to be the insulator 106c and processed using the resist or the like, so that the insulator 106c is formed (see FIGS. 9C and 9D). Note that as illustrated in FIGS. 9C and 9D, the exposed surface of the insulator 104 may be partially removed when the insulator 106c is formed.
  • pattern formation is performed so that the side surface end portions are located outside the side surface end portions of the semiconductor 106b.
  • pattern formation is performed so that the side surface end portions of the insulator 106a and the insulator 106c in the channel width direction are located outside the side surface end portions of the semiconductor 106b in the channel width direction. It is preferable.
  • the semiconductor 106b is enclosed in the insulator 106a and the insulator 106c.
  • the side surface end portion of the semiconductor 106b in particular, the side surface end portion in the channel width direction is provided in contact with the insulator 106a and the insulator 106c.
  • a continuous junction is formed between the insulator 106a or the insulator 106c at the side edge of the semiconductor 106b, and the density of defect states is reduced. Therefore, even if the on-state current easily flows by providing the low resistance region 107a and the low resistance region 107b, the side end portion in the channel width direction of the semiconductor 106b does not become a parasitic channel, and stable electrical characteristics can be obtained. .
  • an insulator to be the insulator 112 is formed.
  • an insulator that can be used as the above-described insulator 112 may be used.
  • the insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 112 may be formed using the ALD method with the substrate temperature at the time of film formation being set to 400 ° C. to 520 ° C., preferably 450 ° C. to 500 ° C. By increasing the substrate temperature at the time of film formation, the concentration of impurities contained in the insulator 112 can be reduced.
  • the carbon concentration and / or the hydrogen concentration can be reduced because the deposition gas, the carbon compound, water, and the like contained in the deposition chamber can be reduced.
  • the density of the insulator 112 (also referred to as film density) can be increased by increasing the substrate temperature during film formation. By increasing the density of the insulator 112, the density of defect states of the insulator 112 can be decreased; thus, stable electrical characteristics can be imparted to the transistor to be manufactured.
  • a conductor to be the conductor 114 is formed.
  • a conductor that can be used for the above-described conductor 114 may be used.
  • the conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the film may be formed using a W-Si target or the like.
  • a resist or the like is formed over the conductor that can be used for the conductor 114 and processed using the resist or the like, so that the insulator 112 and the conductor 114 are formed (see FIGS. 9E and 9E). See F).).
  • the conductor 114 is formed by wet etching or the like using the same mask. Only the etching may be selectively performed. By etching in this manner, the width of the conductor 114 in the gate length direction can be smaller than the width of the insulator 112 in the gate length direction.
  • a dopant 119 is added to the insulator 106a, the semiconductor 106b, and the insulator 106c (see FIGS. 9E and 9F). Accordingly, a region 126a, a region 126b, and a region 126c are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c. Therefore, the concentration of the dopant 119 obtained by SIMS analysis is higher in the region 126b and the region 126c than in the region 126a.
  • an ion implantation method in which an ionized source gas is added after mass separation an ion doping method in which an ionized source gas is added without mass separation, or the like can be used.
  • mass separation the ionic species to be added and the concentration thereof can be strictly controlled.
  • mass separation is not performed, high-concentration ions can be added in a short time.
  • an ion doping method in which atomic or molecular clusters are generated and ionized may be used.
  • the dopant may be paraphrased as an ion, a donor, an acceptor, an impurity, or an element.
  • the addition process of the dopant 119 may be controlled by appropriately setting implantation conditions such as an acceleration voltage and a dose.
  • the dose of the dopant 119 is, for example, 1 ⁇ 10 12 ions / cm 2 or more and 1 ⁇ 10 16 ions / cm 2 or less, preferably 1 ⁇ 10 13 ions / cm 2 or more and 1 ⁇ 10 15 ions / cm 2 or less. That's fine.
  • the acceleration voltage at the time of introducing the dopant 119 may be 2 kV or more and 50 kV or less, preferably 5 kV or more and 30 kV or less.
  • Examples of the dopant 119 include hydrogen, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium. Yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum or tungsten.
  • helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, or boron can be added relatively easily using an ion implantation method, an ion doping method, or the like. Is preferable.
  • heat treatment may be performed after the dopant 119 is added.
  • the heat treatment may be, for example, 250 ° C. or more and 650 ° C. or less, preferably 350 ° C. or more and 450 ° C. or less, and the heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in the air (ultra-dry air).
  • the insulator 116 is formed (see FIGS. 10A and 10B).
  • the above insulator may be used.
  • the insulator 116 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 116 the low resistance region 107a and the low resistance region 107b can be formed in the vicinity of the interface of the insulator 106a, the semiconductor 106b, and the insulator 106c with the insulator 116. Further, the low resistance region 107a and the low resistance region 107b may not be formed.
  • the oxygen flow rate is such that the oxygen flow rate at which a film made of an element contained in the metal target is formed and the oxygen flow rate at which an oxide film containing an element contained in the metal target is formed It is preferable that the oxygen flow rate be between.
  • the insulator 116 can be an oxide film made of a suboxide, so that oxygen in the insulator 106a, the semiconductor 106b, and the insulator 106c can be extracted and easily reduced.
  • the resistance region 107a and the low resistance region 107b can be formed.
  • the suboxide is an intermediate in the reaction process for forming an oxide.
  • suboxides are deficient in oxygen than oxides.
  • an oxide whose oxygen concentration is 1 atomic% or more, 2 atomic% or more, 5 atomic% or more, or 10 atomic% or more lower than an oxide is defined as a suboxide.
  • the oxygen concentration contained in the film formation atmosphere is preferably low.
  • the concentration may be lower than the oxygen concentration in the film formation atmosphere of the semiconductor 106b, and the proportion of oxygen in the whole is less than 5% by volume, preferably less than 2% by volume, more preferably less than 1% by volume, more preferably less than 0. What is necessary is just to set it as less than 5 volume%.
  • the insulator 116 may be formed in an atmosphere in which oxygen is not used as a film formation gas.
  • a film may be formed using a rare gas (such as argon, krypton, or xenon) as a film forming gas.
  • the substrate temperature may be increased.
  • the substrate temperature may be, for example, 100 ° C. or higher and 450 ° C. or lower, preferably 150 ° C. or higher and 400 ° C. or lower, more preferably 170 ° C. or higher and 350 ° C. or lower.
  • a film is formed by a sputtering method or the like, it is preferable to form the film in an atmosphere containing nitrogen because nitrogen can be added to the insulator 106a, the semiconductor 106b, and the insulator 106c and the n-type can be obtained. is there.
  • insulator 116 boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium,
  • An oxide, oxynitride, nitride oxide, or nitride containing hafnium, tantalum, or tungsten may be directly formed by a reactive sputtering method or the like, or a film containing the above element is formed.
  • a heat treatment may be performed later to form an oxide or oxynitride containing the above element.
  • the heat treatment temperature may be, for example, 250 ° C. or higher and 650 ° C. or lower, preferably 350 ° C. or higher and 450 ° C. or lower.
  • an insulator containing oxygen and aluminum for example, aluminum oxide (AlOx) is preferably used.
  • Aluminum oxide has a blocking effect against oxygen, hydrogen, water and the like.
  • the insulator 116 can be formed using an oxide that can be used for the insulator 106a or the insulator 106c.
  • an oxide insulator containing In is preferably used.
  • an In—Al oxide, an In—Ga oxide, or an In—Ga—Zn oxide may be used.
  • An oxide insulator containing In is suitable for use as the insulator 118 because the number of particles generated when a film is formed by a sputtering method is small.
  • an element that can be used as the dopant 119 may be added to further reduce the resistance of the region 126a, the region 126b, the low resistance region 107a, and the low resistance region 107b. Further, by adding in this manner, an element contained in the insulator 116 can be pushed into (knocked on) the insulator 106a, the semiconductor 106b, and the insulator 106c.
  • an ion implantation method, an ion doping method, or the like can be used.
  • oxygen can be supplied from the insulator 104 or the like to the insulator 106a, the semiconductor 106b, and the insulator 106c.
  • the heat treatment may be performed at 250 ° C to 650 ° C, preferably 350 ° C to 450 ° C.
  • the heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment may be performed in a reduced pressure state.
  • an RTA apparatus using lamp heating can also be used.
  • the heat treatment is preferably performed at a temperature lower than that of the heat treatment after film formation of the semiconductor to be the semiconductor 106b.
  • the temperature difference from the heat treatment after the formation of the semiconductor to be the semiconductor 106b is 20 ° C to 150 ° C, preferably 40 ° C to 100 ° C.
  • excess oxygen oxygen
  • the heat treatment after the formation of the insulator 116 is performed in the case where the equivalent heat treatment can be combined with the heating during the formation of each layer (for example, when the equivalent heating is performed in the formation of the insulator 116). There may be no need.
  • oxygen can be prevented from diffusing outward. Accordingly, oxygen can be effectively supplied to a region where a channel is formed in the insulator 106a, the semiconductor 106b, and the insulator 106c, particularly the semiconductor 106b. In this manner, oxygen is supplied to the insulator 106a, the semiconductor 106b, and the insulator 106c to reduce oxygen vacancies, whereby a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with low density of defect states is obtained. be able to.
  • the insulator 118 is formed.
  • the above insulator may be used.
  • the insulator 118 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a resist or the like is formed over the insulator 118, and openings are formed in the insulator 118, the insulator 116, and the insulator 106c. Then, a conductor to be the conductor 108a and the conductor 108b is formed.
  • the conductor to be the conductor 108a and the conductor 108b the above-described conductors can be used.
  • the conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • CMP treatment is performed to remove the conductors 108 a and 108 b over the insulator 118.
  • the conductor 108a and the conductor 108b remain only in the openings formed in the insulator 118, the insulator 116, and the insulator 106c.
  • a conductor to be the conductor 109a and the conductor 109b is formed over the insulator 118, the conductor 108a, and the conductor 108b.
  • the conductor to be the conductor 109a and the conductor 109b the above-described conductors can be used.
  • the conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a resist or the like is formed over the conductor to be the conductor 109a and the conductor 109b and processed using the resist or the like, so that the conductor 109a and the conductor 109b are formed (FIGS. 10C and 10B). (See (D)).
  • the transistor 10 according to one embodiment of the present invention can be manufactured.
  • a transistor having favorable electric characteristics can be provided by suppressing ion penetration of a conductor used for a gate electrode.
  • FIG. 11A shows a structure of a so-called CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.
  • FIG. 12 is a cross-sectional view of the semiconductor device corresponding to FIG.
  • the semiconductor device illustrated in FIG. 12 includes a transistor 2200 and a transistor 2100.
  • the transistor 2100 is provided above the transistor 2200. Note that the transistor described in any of the above embodiments can be used as the transistor 2100. Therefore, for the transistor 2100, the above description of the transistor can be referred to as appropriate.
  • a transistor 2200 illustrated in FIG. 12 is a transistor using a semiconductor substrate 450.
  • the transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.
  • the region 472a and the region 472b function as a source region and a drain region.
  • the insulator 462 functions as a gate insulator.
  • the conductor 454 functions as a gate electrode. Therefore, the resistance of the channel formation region can be controlled by the potential applied to the conductor 454. That is, conduction / non-conduction between the region 472a and the region 472b can be controlled by a potential applied to the conductor 454.
  • a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used.
  • a single crystal silicon substrate is preferably used as the semiconductor substrate 450.
  • a semiconductor substrate having an impurity imparting n-type conductivity As the semiconductor substrate 450, a semiconductor substrate having an impurity imparting n-type conductivity is used. However, as the semiconductor substrate 450, a semiconductor substrate having an impurity imparting p-type conductivity may be used. In that case, a well having an impurity imparting n-type conductivity may be provided in a region to be the transistor 2200. Alternatively, the semiconductor substrate 450 may be i-type.
  • the upper surface of the semiconductor substrate 450 preferably has a (110) plane.
  • the on-state characteristics of the transistor 2200 can be improved.
  • the region 472a and the region 472b are regions having an impurity imparting p-type conductivity. In this manner, the transistor 2200 constitutes a p-channel transistor.
  • the transistor 2200 is separated from an adjacent transistor by the region 460 or the like.
  • the region 460 is a region having an insulating property.
  • the semiconductor device illustrated in FIG. 12 includes an insulator 464, an insulator 466, an insulator 468, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, a conductor 478b, and a conductor.
  • the insulator 464 is provided over the transistor 2200.
  • the insulator 466 is provided over the insulator 464.
  • the insulator 468 is provided over the insulator 466.
  • the insulator 489 is disposed over the insulator 468.
  • the transistor 2100 is provided over the insulator 489.
  • the insulator 493 is provided over the transistor 2100.
  • the insulator 494 is provided over the insulator 493.
  • the insulator 464 includes an opening reaching the region 472a, an opening reaching the region 472b, and an opening reaching the conductor 454.
  • a conductor 480a, a conductor 480b, or a conductor 480c is embedded in each opening.
  • the insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c.
  • a conductor 478a, a conductor 478b, or a conductor 478c is embedded in each opening.
  • the insulator 468 includes an opening reaching the conductor 478b and an opening reaching the conductor 478c. In addition, a conductor 476a or a conductor 476b is embedded in each opening.
  • the insulator 489 includes an opening overlapping with a channel formation region of the transistor 2100, an opening reaching the conductor 476a, and an opening reaching the conductor 476b.
  • a conductor 474a, a conductor 474b, or a conductor 474c is embedded in each opening.
  • the conductor 474a may function as the gate electrode of the transistor 2100.
  • electrical characteristics such as a threshold voltage of the transistor 2100 may be controlled by applying a certain potential to the conductor 474a.
  • the conductor 474a and the conductor 504 functioning as a gate electrode of the transistor 2100 may be electrically connected.
  • the on-state current of the transistor 2100 can be increased.
  • the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 2100 can be stabilized.
  • the conductor 474a corresponds to the conductor 102 in the above embodiment, the description of the conductor 102 can be referred to for details.
  • the insulator 490 includes an opening reaching the conductor 474b and an opening reaching the conductor 474c. Note that the insulator used for the insulator 101 described in the above embodiment may be used for the insulator 490.
  • the conductors 474a to 474c can be prevented from extracting oxygen from the insulator 491. Accordingly, oxygen can be effectively supplied from the insulator 491 to the oxide semiconductor of the transistor 2100.
  • the insulator 491 includes an opening reaching the conductor 474b and an opening reaching the conductor 474c. Note that since the insulator 491 corresponds to the insulator 104 in the above embodiment, the description of the insulator 104 can be referred to for details.
  • the insulator 495 includes an opening reaching the conductor 474b through the region 507b that is one of the source and the drain of the transistor 2100, and an opening reaching the region 507a that is the other of the source and the drain of the transistor 2100; An opening reaching the conductor 504 which is a gate electrode of the transistor 2100 and an opening reaching the conductor 474c are provided. Note that since the insulator 495 corresponds to the insulator 116 in the above embodiment, the description of the insulator 116 can be referred to for details.
  • the insulator 493 includes an opening reaching the conductor 474b through the region 507b that is one of the source and the drain of the transistor 2100, and an opening reaching the region 507a that is the other of the source and the drain of the transistor 2100; An opening reaching the conductor 504 which is a gate electrode of the transistor 2100 and an opening reaching the conductor 474c are provided.
  • a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496d is embedded in each opening. Note that each opening may be provided through an opening further included in any of the components such as the transistor 2100. Note that since the insulator 493 corresponds to the insulator 118 in the above embodiment, the description of the insulator 118 can be referred to for details.
  • the insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b and the conductor 496d, and an opening reaching the conductor 496c.
  • a conductor 498a, a conductor 498b, or a conductor 498c is embedded in each opening.
  • insulator 464 for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon
  • insulator containing gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • One or more of the insulator 464, the insulator 466, the insulator 468, the insulator 489, the insulator 493, or the insulator 494 preferably includes an insulator having a function of blocking impurities such as hydrogen and oxygen.
  • an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 2100, the electrical characteristics of the transistor 2100 can be stabilized.
  • Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum.
  • An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, conductor 498a, conductor 498b, and conductor 498c include, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel,
  • a conductor including one or more of copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer.
  • it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.
  • the semiconductor device illustrated in FIG. 13 is different only in the structure of the transistor 2200 of the semiconductor device illustrated in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 12 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 13 illustrates the case where the transistor 2200 is a Fin type.
  • the semiconductor device illustrated in FIG. 13 illustrates the case where the transistor 2200 is a Fin type.
  • an effective channel width can be increased, whereby the on-state characteristics of the transistor 2200 can be improved.
  • the contribution of the electric field of the gate electrode can be increased, off characteristics of the transistor 2200 can be improved.
  • the semiconductor device shown in FIG. 14 is different only in the structure of the transistor 2200 of the semiconductor device shown in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 12 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 14 illustrates the case where the transistor 2200 is provided over a semiconductor substrate 450 which is an SOI substrate.
  • FIG. 14 illustrates a structure in which the region 456 is separated from the semiconductor substrate 450 by an insulator 452.
  • the insulator 452 can be formed by making the semiconductor substrate 450 an insulator. For example, as the insulator 452, silicon oxide can be used.
  • a p-channel transistor is manufactured using a semiconductor substrate and an n-channel transistor is formed thereabove, so that the area occupied by the element can be reduced. That is, the degree of integration of the semiconductor device can be increased. Further, since the process can be simplified as compared with the case where an n-channel transistor and a p-channel transistor are formed using the same semiconductor substrate, the productivity of the semiconductor device can be increased. In addition, the yield of the semiconductor device can be increased. In addition, a p-channel transistor can sometimes omit complicated processes such as an LDD (Lightly Doped Drain) region, a shallow trench structure, and a strain design. Therefore, productivity and yield may be increased as compared with the case where an n-channel transistor is manufactured using a semiconductor substrate.
  • LDD Lightly Doped Drain
  • FIG. 11B illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, it can function as a so-called CMOS analog switch.
  • FIG. 15 illustrates an example of a semiconductor device (memory device) using the transistor according to one embodiment of the present invention, which can hold stored data even in a state where power is not supplied and has no limit on the number of writing times.
  • a semiconductor device illustrated in FIG. 15A includes a transistor 3200 including a first semiconductor, a transistor 3300 including a second semiconductor, and a capacitor 3400. Note that as the transistor 3300, a transistor similar to the above-described transistor 2100 can be used.
  • the transistor 3300 is preferably a transistor with low off-state current.
  • a transistor including an oxide semiconductor can be used. Since the off-state current of the transistor 3300 is small, stored data can be held in a specific node of the semiconductor device for a long time. That is, a refresh operation is not required or the frequency of the refresh operation can be extremely low, so that the semiconductor device with low power consumption is obtained.
  • the first wiring 3001 is electrically connected to the source of the transistor 3200
  • the second wiring 3002 is electrically connected to the drain of the transistor 3200
  • the third wiring 3003 is electrically connected to one of a source and a drain of the transistor 3300
  • the fourth wiring 3004 is electrically connected to the gate of the transistor 3300.
  • the gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one of the electrodes of the capacitor 3400
  • the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 3400.
  • the semiconductor device illustrated in FIG. 15A has a characteristic that the potential of the gate of the transistor 3200 can be held; thus, information can be written, held, and read as described below.
  • the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG electrically connected to one of the gate of the transistor 3200 and the electrode of the capacitor 3400. That is, predetermined charge is supplied to the gate of the transistor 3200 (writing).
  • predetermined charge is supplied to the gate of the transistor 3200 (writing).
  • the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off and the transistor 3300 is turned off, so that charge is held at the node FG (holding).
  • the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 3200 is an n-channel type, the apparent threshold voltage V th_H when a high level charge is applied to the gate of the transistor 3200 is the low level charge applied to the gate of the transistor 3200. This is because it becomes lower than the apparent threshold voltage V th_L in the case of being present.
  • the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 3200 into a “conducting state”.
  • the potential of the fifth wiring 3005 can be set to a potential V 0 between V th_H and V th_L .
  • the transistor 3200 is in a “conducting state” if the potential of the fifth wiring 3005 is V 0 (> V th_H ).
  • the transistor 3200 remains in the “non-conductive state” even when the potential of the fifth wiring 3005 becomes V 0 ( ⁇ V th_L ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.
  • the fifth wiring 3005 is supplied with a potential at which the transistor 3200 is in a “non-conduction state” regardless of the charge applied to the node FG, that is, a potential lower than V th_H.
  • a potential at which the transistor 3200 becomes “conductive” regardless of the charge applied to the node FG, that is, a potential higher than V th_L.
  • the semiconductor device according to the present invention is not limited to this.
  • a structure in which three or more kinds of electric charges can be held in the node FG of the semiconductor device may be employed. With such a structure, the semiconductor device can be multi-valued and the storage capacity can be increased.
  • FIG. 16 is a cross-sectional view of the semiconductor device corresponding to FIG.
  • the semiconductor device illustrated in FIG. 16 includes a transistor 3200, a transistor 3300, and a capacitor 3400.
  • the transistor 3300 and the capacitor 3400 are provided above the transistor 3200.
  • the transistor 3300 the above description of the transistor 2100 is referred to.
  • the transistor 3200 the description of the transistor 2200 illustrated in FIGS. Note that although FIG. 12 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.
  • a transistor 2200 illustrated in FIG. 16 is a transistor including a semiconductor substrate 450.
  • the transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.
  • the semiconductor device illustrated in FIG. 16 includes an insulator 464, an insulator 466, an insulator 468, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, a conductor 478b, and a conductor.
  • the insulator 464 is provided over the transistor 3200.
  • the insulator 466 is provided over the insulator 464.
  • the insulator 468 is provided over the insulator 466.
  • the insulator 489 is disposed over the insulator 468.
  • the transistor 2100 is provided over the insulator 489.
  • the insulator 493 is provided over the transistor 2100.
  • the insulator 494 is provided over the insulator 493.
  • the insulator 464 includes an opening reaching the region 472a, an opening reaching the region 472b, and an opening reaching the conductor 454.
  • a conductor 480a, a conductor 480b, or a conductor 480c is embedded in each opening.
  • the insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c.
  • a conductor 478a, a conductor 478b, or a conductor 478c is embedded in each opening.
  • the insulator 468 includes an opening reaching the conductor 478b and an opening reaching the conductor 478c. In addition, a conductor 476a or a conductor 476b is embedded in each opening.
  • the insulator 489 includes an opening overlapping with a channel formation region of the transistor 3300, an opening reaching the conductor 476a, and an opening reaching the conductor 476b.
  • a conductor 474a, a conductor 474b, or a conductor 474c is embedded in each opening.
  • the conductor 474a may function as the bottom gate electrode of the transistor 3300.
  • electrical characteristics such as a threshold voltage of the transistor 3300 may be controlled by applying a certain potential to the conductor 474a.
  • the conductor 474a and the conductor 504 which is the top gate electrode of the transistor 3300 may be electrically connected.
  • the on-state current of the transistor 3300 can be increased.
  • the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 3300 can be stabilized.
  • the insulator 490 includes an opening reaching the conductor 474b and an opening reaching the conductor 474c. Note that the insulator used for the insulator 101 described in the above embodiment may be used for the insulator 490.
  • the conductors 474a to 474c can be prevented from extracting oxygen from the insulator 491. Accordingly, oxygen can be effectively supplied from the insulator 491 to the oxide semiconductor of the transistor 3300.
  • the insulator 491 includes an opening reaching the conductor 474b and an opening reaching the conductor 474c. Note that since the insulator 491 corresponds to the insulator 104 in the above embodiment, the description of the insulator 104 can be referred to for details.
  • the insulator 495 includes an opening reaching the conductor 474b through the region 507b which is one of the source and the drain of the transistor 3300, and the region 507a which is the other of the source and the drain of the transistor 3300 and the insulator 511.
  • the insulator 495 corresponds to the insulator 116 in the above embodiment, the description of the insulator 116 can be referred to for details.
  • the insulator 493 passes through the region 507b which is one of the source and the drain of the transistor 3300 and reaches the conductor 474b, and the region 507a which is the other of the source and the drain of the transistor 3300 and the insulator 511.
  • a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496d is embedded in each opening. Note that each opening may further pass through an opening included in any of the components such as the transistor 3300. Note that since the insulator 493 corresponds to the insulator 118 in the above embodiment, the description of the insulator 118 can be referred to for details.
  • the insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b, an opening reaching the conductor 496c, and an opening reaching the conductor 496d.
  • a conductor 498a, a conductor 498b, or a conductor 498c is embedded in each opening.
  • One or more of the insulator 464, the insulator 466, the insulator 468, the insulator 489, the insulator 493, or the insulator 494 preferably includes an insulator having a function of blocking impurities such as hydrogen and oxygen.
  • an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 3300, electrical characteristics of the transistor 3300 can be stabilized.
  • the source or the drain of the transistor 3200 is electrically connected to the region 507b which is one of the source and the drain of the transistor 3300 through the conductor 480b, the conductor 478b, the conductor 476a, the conductor 474b, and the conductor 496c.
  • the conductor 454 that is a gate electrode of the transistor 3200 includes the other of the source and the drain of the transistor 3300 through the conductor 480c, the conductor 478c, the conductor 476b, the conductor 474c, and the conductor 496d. Is electrically connected to the region 507a.
  • the capacitor 3400 includes a region 507a which is the other of the source and the drain of the transistor 3300, a conductor 514, and an insulator 511. Note that since the insulator 511 can be formed through the same process as the insulator functioning as the gate insulator of the transistor 3300, productivity may be improved, which may be preferable. In addition, when the layer formed through the same step as the conductor 504 functioning as the gate electrode of the transistor 3300 is used as the conductor 514, productivity may be increased, which may be preferable.
  • FIG. 12 For other structures, the description of FIG. 12 and the like can be referred to as appropriate.
  • the semiconductor device illustrated in FIG. 17 is different only in the structure of the transistor 3200 of the semiconductor device illustrated in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 16 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 17 illustrates the case where the transistor 3200 is a Fin type. For the Fin-type transistor 3200, the description of the transistor 2200 illustrated in FIGS. Note that although FIG. 13 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.
  • the semiconductor device illustrated in FIG. 18 is different only in the structure of the transistor 3200 of the semiconductor device illustrated in FIG. Therefore, for the semiconductor device illustrated in FIG. 18, the description of the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 18 illustrates the case where the transistor 3200 is provided over a semiconductor substrate 450 which is an SOI substrate. For the transistor 3200 provided over the semiconductor substrate 450 which is an SOI substrate, the description of the transistor 2200 illustrated in FIG. 14 is referred to. Note that although FIG. 14 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.
  • the semiconductor device illustrated in FIG. 15B is different from the semiconductor device illustrated in FIG. 15A in that the transistor 3200 is not provided. In this case as well, information writing and holding operations can be performed by operations similar to those of the semiconductor device illustrated in FIG.
  • the potential of one electrode of the capacitor 3400 is V
  • the capacitance of the capacitor 3400 is C
  • the capacitance component of the third wiring 3003 is CB
  • the potential of the third wiring 3003 before the charge is redistributed is (CB ⁇ VB0 + CV) / (CB + C). Therefore, when the potential of one of the electrodes of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held.
  • information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.
  • a transistor to which the first semiconductor is applied is used as a driver circuit for driving the memory cell, and a transistor to which the second semiconductor is applied is stacked over the driver circuit as the transistor 3300. do it.
  • the semiconductor device described above can hold stored data for a long time by using a transistor with an off-state current that includes an oxide semiconductor. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be extremely low, so that a semiconductor device with low power consumption can be realized.
  • stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).
  • the semiconductor device since the semiconductor device does not require a high voltage for writing information, the element hardly deteriorates.
  • the semiconductor device according to one embodiment of the present invention is a semiconductor device in which the number of rewritable times which is a problem in the conventional nonvolatile memory is not limited and the reliability is drastically improved. Further, since data is written depending on the conductive state and non-conductive state of the transistor, high-speed operation is possible.
  • a semiconductor device illustrated in FIG. 19 includes transistors 4100 to 4400, a capacitor 4500, and a capacitor 4600.
  • the transistor 4100 can be a transistor similar to the above-described transistor 3200, and the transistors 4200 to 4400 can be the same transistor as the above-described transistor 3300.
  • a plurality of semiconductor devices illustrated in FIG. 19 are provided in a matrix.
  • the semiconductor device illustrated in FIG. 19 can control writing and reading of a data voltage in accordance with a signal or a potential supplied to the wiring 4001, the wiring 4003, and the wirings 4005 to 4009.
  • One of a source and a drain of the transistor 4100 is connected to the wiring 4003.
  • the other of the source and the drain of the transistor 4100 is connected to the wiring 4001. Note that although the conductivity type of the transistor 4100 is shown as a p-channel type in FIG. 19, it may be an n-channel type.
  • the semiconductor device illustrated in FIG. 19 includes two data holding units.
  • the first data holding portion holds charge between one of a source and a drain of the transistor 4400 connected to the node FG1, one electrode of the capacitor 4600, and one of the source and the drain of the transistor 4200.
  • the second data holding portion is between the gate of the transistor 4100 connected to the node FG2, the other of the source and the drain of the transistor 4200, one of the source and the drain of the transistor 4300, and one electrode of the capacitor 4500. Holds a charge.
  • the other of the source and the drain of the transistor 4300 is connected to the wiring 4003.
  • the other of the source and the drain of the transistor 4400 is connected to the wiring 4001.
  • a gate of the transistor 4400 is connected to the wiring 4005.
  • a gate of the transistor 4200 is connected to the wiring 4006.
  • a gate of the transistor 4300 is connected to the wiring 4007.
  • the other electrode of the capacitor 4600 is connected to the wiring 4008.
  • the other electrode of the capacitor 4500 is connected to the wiring 4009.
  • the transistors 4200 to 4400 function as switches for controlling writing of data voltages and holding of electric charges.
  • transistors with low current (off-state current) flowing between the source and the drain in a non-conduction state are preferably used as the transistors 4200 to 4400.
  • the transistor with low off-state current is preferably a transistor having an oxide semiconductor in a channel formation region (OS transistor).
  • An OS transistor has advantages such as low off-state current and that it can be formed over a transistor including silicon.
  • the conductivity types of the transistors 4200 to 14 are illustrated as n-channel types in FIG. 19, they may be p-channel types.
  • the transistor 4200, the transistor 4300, and the transistor 4400 are preferably provided in different layers even when a transistor including an oxide semiconductor is used. That is, as illustrated in FIG. 19, the semiconductor device illustrated in FIG. 19 includes a first layer 4021 including a transistor 4100, a second layer 4022 including a transistor 4200 and a transistor 4300, and a third layer including a transistor 4400. 4023. By stacking layers including transistors, the circuit area can be reduced and the semiconductor device can be downsized.
  • a data voltage write operation (hereinafter referred to as a write operation 1) to the data holding portion connected to the node FG1 will be described. Note that in the following description, the data voltage written to the data holding portion connected to the node FG1 is V D1, and the threshold voltage of the transistor 4100 is Vth.
  • the wiring 4001 is electrically floated.
  • the wirings 4005 and 4006 are set to a high level.
  • the wirings 4007 to 4009 are set to a low level. Then, the potential of the node FG2 which is in an electrically floating state is increased, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4001 increases. In addition, the transistors 4400 and 4200 are turned on. Therefore, the potentials of the nodes FG1 and FG2 increase as the potential of the wiring 4001 increases.
  • V D1 applied to the wiring 4003 is supplied to the wiring 4001 when current flows through the transistor 4100, so that the potentials of the nodes FG1 and FG2 are increased.
  • Vgs of the transistor 4100 becomes Vth, so that the current stops.
  • writing operation 2 a data voltage writing operation (hereinafter referred to as writing operation 2) to the data holding portion connected to the node FG2 will be described.
  • writing operation 2 illustrating a data voltage to be written to the data holding unit connected to the node FG2 as V D2.
  • the wiring 4001 is electrically floated. Further, the wiring 4007 is set to a high level. In addition, the wirings 4005, 4006, 4008, and 4009 are set to a low level.
  • the transistor 4300 is turned on and the wiring 4003 is set to a low level. Therefore, the potential of the node FG2 also decreases to a low level, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 increases. In addition, the transistor 4300 is turned on. Therefore, the potential of the node FG2 increases as the potential of the wiring 4003 increases.
  • V D2 applied to the wiring 4001 is supplied to the wiring 4003 when a current flows through the transistor 4100, so that the potential of the node FG2 increases.
  • Vgs of the transistor 4100 becomes Vth, so that the current stops.
  • the potential of the node FG1 is non-conductive in the transistors 4200 and 4400, and “V D1 ⁇ Vth” written in the writing operation 1 is held.
  • the wiring 4009 is set to a high level and the potentials of the nodes FG1 and FG2 are increased. Then, each transistor is brought into a non-conducting state to eliminate the movement of electric charges and to hold the written data voltage.
  • V D1 ⁇ Vth and “V D2 ⁇ Vth” have been described as examples of potentials to be written, these are data voltages corresponding to multi-value data. Therefore, when 4-bit data is held in each data holding unit, 16 values of “V D1 ⁇ Vth” and “V D2 ⁇ Vth” can be taken.
  • a data voltage read operation (hereinafter referred to as a read operation 1) to a data holding portion connected to the node FG2 will be described.
  • the wiring 4003 that has been electrically floated after precharging is discharged.
  • the wirings 4005 to 4008 are set to a low level.
  • the wiring 4009 is set to a low level, and the potential of the node FG2 in an electrically floating state is set to “V D2 ⁇ Vth”.
  • a current flows through the transistor 4100 when the potential of the node FG2 is decreased.
  • the potential of the electrically floating wiring 4003 is decreased.
  • Vgs of the transistor 4100 decreases.
  • Vgs of the transistor 4100 becomes Vth of the transistor 4100, a current flowing through the transistor 4100 is reduced.
  • the potential of the wiring 4003 becomes “V D2 ” that is a value larger by Vth than the potential “V D2 ⁇ Vth” of the node FG2.
  • the potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG2.
  • the read data voltage of the analog value is subjected to A / D conversion, and data of a data holding unit connected to the node FG2 is acquired.
  • a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level.
  • the potential of the wiring 4003 in the floating state is decreased to “V D2 ”.
  • Vgs between “V D2 ⁇ Vth” of the node FG2 becomes Vth, so that the current stops.
  • V D2 ” written in the writing operation 2 is read out to the wiring 4003.
  • the transistor 4300 When data in the data holding portion connected to the node FG2 is acquired, the transistor 4300 is turned on to discharge “V D2 ⁇ Vth” of the node FG2.
  • the charge held in the node FG1 is distributed to the node FG2, and the data voltage of the data holding unit connected to the node FG1 is transferred to the data holding unit connected to the node FG2.
  • the wirings 4001 and 4003 are set to a low level.
  • the wiring 4006 is set to a high level.
  • the wiring 4005 and the wirings 4007 to 4009 are set to a low level.
  • the capacitance value of the capacitor 4600 is preferably larger than the capacitance value of the capacitor 4500.
  • the potential “V D1 ⁇ Vth” written to the node FG1 is preferably higher than the potential “V D2 ⁇ Vth” representing the same data. In this way, by changing the ratio of the capacitance values and increasing the potential to be written in advance, it is possible to suppress a decrease in potential after the charge is distributed. The fluctuation of the potential due to the charge distribution will be described later.
  • read operation 2 a data voltage read operation (hereinafter referred to as read operation 2) to the data holding portion connected to the node FG1 will be described.
  • the wiring 4003 that has been electrically floated after precharging is discharged.
  • the wirings 4005 to 4008 are set to a low level.
  • the wiring 4009 is set to a high level at the time of precharging and then set to a low level.
  • the node FG2 in an electrically floating state is set to a potential “V D1 ⁇ Vth”.
  • the potential of the electrically floating wiring 4003 is decreased.
  • Vgs of the transistor 4100 decreases.
  • Vgs of the transistor 4100 becomes Vth of the transistor 4100
  • a current flowing through the transistor 4100 is reduced. That is, the potential of the wiring 4003 becomes “V D1 ” that is a value larger by Vth than the potential “V D1 ⁇ Vth” of the node FG2.
  • the potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG1.
  • the read data voltage of the analog value performs A / D conversion, and acquires data of the data holding unit connected to the node FG1. The above is the data voltage reading operation to the data holding portion connected to the node FG1.
  • a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level.
  • the potential of the wiring 4003 in the floating state is lowered to “V D1 ”.
  • the current stops because Vgs between the node FG2 and “V D1 ⁇ Vth” becomes Vth. Then, “V D1 ” written in the writing operation 1 is read out to the wiring 4003.
  • the data voltage can be read from the plurality of data holding units by the data voltage reading operation from the nodes FG1 and FG2 described above. For example, a total of 8 bits (256 values) of data can be held by holding 4 bits (16 values) of data in the nodes FG1 and FG2, respectively.
  • the first layer 4021 to the third layer 4023 are used. However, by forming further layers, the storage capacity can be increased without increasing the area of the semiconductor device. .
  • the read potential can be read as a voltage higher than the written data voltage by Vth. Therefore, it is possible to adopt a configuration in which Vth of “V D1 ⁇ Vth” or “V D2 ⁇ Vth” written by the write operation is canceled and read. As a result, the storage capacity per memory cell can be improved and the read data can be brought close to the correct data, so that the data reliability can be improved.
  • FIG. 20 is a cross-sectional view of the semiconductor device corresponding to FIG.
  • the semiconductor device illustrated in FIG. 20 includes transistors 4100 to 4400, a capacitor 4500, and a capacitor 4600.
  • the transistor 4100 is formed in the first layer 4021
  • the transistors 4200 and 4300, and the capacitor 4500 are formed in the second layer 4022
  • the transistor 4400 and the capacitor 4600 are formed in the third layer 4023. .
  • the description of the transistor 3300 can be referred to as the transistors 4200 to 4400, and the description of the transistor 3200 can be referred to as the transistor 4100.
  • the description of FIG. 16 can be referred to for other wirings, insulators, and the like as appropriate.
  • the capacitor 3400 in the semiconductor device illustrated in FIG. 16 has a structure in which a conductive layer is provided in parallel to the substrate to form a capacitor.
  • a conductive layer is provided in a trench shape to It is set as the structure which forms. With such a configuration, a large capacitance value can be secured even with the same occupied area.
  • ⁇ FPGA> One embodiment of the present invention can also be applied to an LSI such as an FPGA (Field Programmable Gate Array).
  • FIG. 21A illustrates an example of a block diagram of an FPGA.
  • the FPGA includes a routing switch element 521 and a logic element 522.
  • the logic element 522 can switch the function of the logic circuit such as the function of the combinational circuit or the function of the sequential circuit in accordance with the configuration data stored in the configuration memory.
  • FIG. 21B is a schematic diagram for explaining the role of the routing switch element 521.
  • the routing switch element 521 can switch the connection between the logic elements 522 according to the configuration data stored in the configuration memory 523. Note that FIG. 21B illustrates one switch and illustrates a state where the connection between the terminal IN and the terminal OUT is switched; in practice, a switch is provided between the plurality of logic elements 522.
  • FIG. 21C illustrates an example of a circuit configuration that functions as the configuration memory 523.
  • the configuration memory 523 includes a transistor M11 configured by an OS transistor and M12 configured by a Si transistor.
  • the node FN SW given the configuration data D SW through the transistor M11.
  • the potential of the configuration data DSW can be held by turning off the transistor M11.
  • the conduction state of the transistor M12 is switched by the held potential of the configuration data DSW , and the connection between the terminal IN and the terminal OUT can be switched.
  • FIG. 21D is a schematic diagram for explaining the role of the logic element 522.
  • the logic element 522 can switch the potential of the terminal OUT mem in accordance with configuration data stored in the configuration memory 527.
  • the look-up table 524 can switch the function of the combinational circuit that processes the signal of the terminal IN in accordance with the potential of the terminal OUT mem .
  • the logic element 522 includes a register 525 which is a sequential circuit and a selector 526 for switching a signal of the terminal OUT.
  • the selector 526 can select the output of the signal of the lookup table 524 or the output of the signal of the register 525 in accordance with the potential of the terminal OUT mem output from the configuration memory 527.
  • FIG. 21E illustrates an example of a circuit configuration that functions as the configuration memory 527.
  • the configuration memory 527 includes transistors M13 and M14 configured by OS transistors and M15 and M16 configured by Si transistors.
  • Configuration data D LE is supplied to the node FN LE via the transistor M13.
  • the node FNB LE is supplied with configuration data DB LE via the transistor M14.
  • the configuration data DB LE corresponds to a potential obtained by inverting the logic of the configuration data D LE .
  • the potentials of the configuration data D LE and configuration data DB LE can be held by turning off the transistors M13 and M14.
  • One conduction state of the transistor M15 or the transistor M16 is switched depending on the held configuration data D LE and configuration data DB LE , and the potential VDD or the potential VSS can be applied to the terminal OUT mem .
  • the transistors M12, M15, and M16 are composed of Si transistors
  • the transistors M11, M13, and M14 are composed of OS transistors.
  • the wiring that connects the Si transistors in the lower layer can be made of a low-resistance conductive material. Therefore, a circuit excellent in improving access speed and reducing power consumption can be obtained.
  • FIG. 22A is a plan view illustrating an example of an imaging device 200 according to one embodiment of the present invention.
  • the imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290.
  • the pixel unit 210 includes a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more).
  • the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are connected to the plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211, respectively.
  • peripheral circuit 260 the peripheral circuit 270, the peripheral circuit 280, the peripheral circuit 290, and the like are all referred to as “peripheral circuits” or “driving circuits” in some cases.
  • peripheral circuit 260 can be said to be part of the peripheral circuit.
  • the imaging apparatus 200 preferably includes a light source 291.
  • the light source 291 can emit the detection light P1.
  • the peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. Further, the peripheral circuit may be formed on a substrate over which the pixel portion 210 is formed. Further, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that one or more of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be omitted from the peripheral circuit.
  • the pixel 211 may be inclined. By arranging the pixels 211 at an angle, the pixel interval (pitch) in the row direction and the column direction can be shortened. Thereby, the quality of imaging in the imaging apparatus 200 can be further improved.
  • One pixel 211 included in the imaging apparatus 200 is configured by a plurality of sub-pixels 212, and a color image display is realized by combining each sub-pixel 212 with a filter (color filter) that transmits light in a specific wavelength range. Information can be acquired.
  • FIG. 23A is a plan view illustrating an example of a pixel 211 for acquiring a color image.
  • a pixel 211 illustrated in FIG. 23A includes a sub-pixel 212 (hereinafter, also referred to as “sub-pixel 212R”) provided with a color filter that transmits light in the red (R) wavelength region, and a green (G) wavelength.
  • a sub-pixel 212 (hereinafter also referred to as “sub-pixel 212G”) provided with a color filter that transmits light in the region and a sub-pixel 212 (hereinafter referred to as “color filter” that transmits light in the blue (B) wavelength region. , Also referred to as “sub-pixel 212B”.
  • the sub-pixel 212 can function as a photosensor.
  • the subpixel 212 (subpixel 212R, subpixel 212G, and subpixel 212B) is electrically connected to the wiring 231, the wiring 247, the wiring 248, the wiring 249, and the wiring 250. Further, the sub-pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 253.
  • the wiring 248 and the wiring 249 connected to the pixel 211 in the n-th row are referred to as a wiring 248 [n] and a wiring 249 [n], respectively.
  • the wiring 253 connected to the pixel 211 in the m-th column is referred to as a wiring 253 [m]. Note that in FIG.
  • the wiring 253 connected to the subpixel 212R included in the pixel 211 in the m-th column is the wiring 253 [m] R
  • the wiring 253 connected to the subpixel 212G is the wiring 253 [m] G
  • a wiring 253 connected to the subpixel 212B is described as a wiring 253 [m] B.
  • the subpixel 212 is electrically connected to a peripheral circuit through the wiring.
  • the imaging apparatus 200 has a configuration in which the sub-pixels 212 provided with color filters that transmit light in the same wavelength region of adjacent pixels 211 are electrically connected via a switch.
  • the sub-pixel 212 included in the pixel 211 arranged in n rows (n is an integer of 1 to p) and m columns (m is an integer of 1 to q) is adjacent to the pixel 211.
  • a connection example of the sub-pixel 212 included in the pixel 211 arranged in n + 1 rows and m columns is shown.
  • a subpixel 212R arranged in n rows and m columns and a subpixel 212R arranged in n + 1 rows and m columns are connected via a switch 201.
  • sub-pixel 212G arranged in n rows and m columns and the sub-pixel 212G arranged in n + 1 rows and m columns are connected via a switch 202.
  • sub-pixel 212B arranged in n rows and m columns and the sub-pixel 212B arranged in n + 1 rows and m columns are connected via a switch 203.
  • the color filter used for the sub-pixel 212 is not limited to red (R), green (G), and blue (B), and transmits cyan (C), yellow (Y), and magenta (M) light, respectively.
  • a color filter may be used.
  • a full-color image can be acquired by providing the sub-pixel 212 that detects light of three different wavelength ranges in one pixel 211.
  • a color filter that transmits yellow (Y) light is provided in addition to the sub-pixel 212 provided with a color filter that transmits red (R), green (G), and blue (B) light.
  • a color filter that transmits yellow (Y) light is provided in addition to the sub-pixel 212 provided with a color filter that transmits cyan (C), yellow (Y), and magenta (M) light.
  • a color filter that transmits blue (B) light is provided.
  • a pixel 211 having a sub-pixel 212 may be used.
  • the sub-pixel 212 that detects light in the red wavelength region, the sub-pixel 212 that detects light in the green wavelength region, and the sub-pixel 212 that detects light in the blue wavelength region may not be 1: 1: 1.
  • the number of subpixels 212 provided in the pixel 211 may be one, but two or more are preferable. For example, by providing two or more subpixels 212 that detect light in the same wavelength region, redundancy can be increased and the reliability of the imaging apparatus 200 can be increased.
  • IR Infrared
  • ND Neutral Density filter
  • a lens may be provided in the pixel 211.
  • the photoelectric conversion element can receive incident light efficiently.
  • the light 256 is transmitted to the photoelectric conversion element 220 through the lens 255, the filter 254 (filter 254R, the filter 254G, and the filter 254B) formed in the pixel 211, the pixel circuit 230, and the like. It can be set as the structure made to enter.
  • part of the light 256 indicated by the arrow may be blocked by part of the wiring 257. Therefore, a structure in which a lens 255 and a filter 254 are disposed on the photoelectric conversion element 220 side as illustrated in FIG. 24B so that the photoelectric conversion element 220 receives light 256 efficiently is preferable.
  • a photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used.
  • the photoelectric conversion element 220 may be formed using a substance having a function of generating charges by absorbing radiation.
  • the substance having a function of absorbing radiation and generating a charge include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.
  • the photoelectric conversion element 220 when selenium is used for the photoelectric conversion element 220, the photoelectric conversion element 220 having a light absorption coefficient over a wide wavelength range such as X-rays and gamma rays in addition to visible light, ultraviolet light, and infrared light can be realized.
  • one pixel 211 included in the imaging apparatus 200 may include a sub-pixel 212 including a first filter in addition to the sub-pixel 212 illustrated in FIG.
  • FIG. 25A and 25B are cross-sectional views of elements included in the imaging device.
  • An imaging device illustrated in FIG. 25A includes a transistor 351 using silicon provided over a silicon substrate 300, a transistor 352 and a transistor 353 using oxide semiconductors stacked over the transistor 351, and a silicon substrate. 300 includes a photodiode 360 provided. Each transistor and photodiode 360 has electrical connection with various plugs 370 and wirings 371. Further, the anode 361 of the photodiode 360 is electrically connected to the plug 370 through the low resistance region 363.
  • the imaging device is provided in contact with the layer 310 including the transistor 351 and the photodiode 360 provided over the silicon substrate 300, the layer 320 including the wiring 371, and the layer 320 including the wiring 371.
  • a layer 330 including the transistor 353, and a layer 340 provided in contact with the layer 330 and including a wiring 372 and a wiring 373.
  • the light-receiving surface of the photodiode 360 is provided on the surface opposite to the surface where the transistor 351 is formed in the silicon substrate 300. With this configuration, an optical path can be secured without being affected by various transistors and wirings. Therefore, a pixel with a high aperture ratio can be formed. Note that the light receiving surface of the photodiode 360 may be the same as the surface on which the transistor 351 is formed.
  • the layer 310 may be a layer including a transistor including an oxide semiconductor.
  • the layer 310 may be omitted, and the pixel may be formed using only a transistor including an oxide semiconductor.
  • the layer 330 may be omitted.
  • An example of a cross-sectional view in which the layer 330 is omitted is illustrated in FIG.
  • the silicon substrate 300 may be an SOI substrate.
  • germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor substrate can be used.
  • an insulator 380 is provided between the layer 310 including the transistor 351 and the photodiode 360 and the layer 330 including the transistor 352 and the transistor 353.
  • the position of the insulator 380 is not limited.
  • Hydrogen in the insulator provided in the vicinity of the channel formation region of the transistor 351 has an effect of terminating the dangling bond of silicon and improving the reliability of the transistor 351.
  • hydrogen in the insulator provided in the vicinity of the transistor 352, the transistor 353, and the like is one of the factors that generate carriers in the oxide semiconductor. Therefore, the reliability of the transistor 352, the transistor 353, and the like may be reduced. Therefore, in the case where a transistor including an oxide semiconductor is stacked over a transistor including a silicon-based semiconductor, an insulator 380 having a function of blocking hydrogen is preferably provided therebetween. By confining hydrogen below the insulator 380, the reliability of the transistor 351 can be improved. Further, since diffusion of hydrogen from a lower layer than the insulator 380 to an upper layer than the insulator 380 can be suppressed, reliability of the transistor 352, the transistor 353, and the like can be improved.
  • the insulator 380 for example, an insulator having a function of blocking oxygen or hydrogen is used.
  • the photodiode 360 provided in the layer 310 and the transistor provided in the layer 330 can be formed to overlap with each other. Then, the integration degree of pixels can be increased. That is, the resolution of the imaging device can be increased.
  • FIGS. 26A1 and 26B1 part or all of the imaging device may be curved.
  • FIG. 26A1 illustrates a state where the imaging device is bent in the direction of dashed-dotted line X1-X2 in FIG.
  • FIG. 26A2 is a cross-sectional view illustrating a portion indicated by dashed-dotted line X1-X2 in FIG. 26A3 is a cross-sectional view illustrating a portion indicated by dashed-dotted line Y1-Y2 in FIG.
  • FIG. 26B1 illustrates a state in which the imaging device is curved in the direction of the alternate long and short dash line X3-X4 in the drawing and in the direction of the dashed dotted line Y3-Y4 in the same drawing.
  • FIG. 26B2 is a cross-sectional view illustrating a portion indicated by dashed-dotted line X3-X4 in FIG. 26B3 is a cross-sectional view illustrating a portion indicated by dashed-dotted line Y3-Y4 in FIG.
  • FIG. 27 is a block diagram illustrating a configuration example of a CPU in which some of the above-described transistors are used.
  • ALU 1191 Arithmetic logic unit, arithmetic circuit
  • ALU controller 1192 Arithmetic logic unit, arithmetic circuit
  • instruction decoder 1193 an instruction decoder 1194
  • timing controller 1195 a register 1196
  • register controller 1197 a register controller 1197
  • bus interface 1198 a bus interface 1198.
  • a rewritable ROM 1199 and a ROM interface 1189 As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used.
  • the ROM 1199 and the ROM interface 1189 may be provided in separate chips.
  • the CPU illustrated in FIG. 27 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.
  • the configuration including the CPU or the arithmetic circuit illustrated in FIG. 27 may be a single core, and a plurality of the cores may be included, and each core may operate in parallel.
  • the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.
  • Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.
  • the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191.
  • the interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program.
  • the register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.
  • the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197.
  • the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits.
  • a memory cell is provided in the register 1196.
  • the above-described transistor, memory device, or the like can be used as the memory cell of the register 1196.
  • the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.
  • FIG. 28 is an example of a circuit diagram of a memory element 1200 that can be used as the register 1196.
  • the memory element 1200 includes a circuit 1201 in which stored data is volatilized by power-off, a circuit 1202 in which stored data is not volatilized by power-off, a switch 1203, a switch 1204, a logic element 1206, and a capacitor 1207. Circuit 1220 having.
  • the circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210.
  • the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor, as necessary.
  • the memory device described above can be used for the circuit 1202.
  • GND (0 V) or a potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 of the circuit 1202.
  • the gate of the transistor 1209 is grounded through a load such as a resistor.
  • the switch 1203 is configured using a transistor 1213 of one conductivity type (eg, n-channel type), and the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type.
  • a transistor 1213 of one conductivity type eg, n-channel type
  • the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type.
  • the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213
  • the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213
  • the switch 1203 corresponds to the gate of the transistor 1213.
  • conduction or non-conduction between the first terminal and the second terminal that is, the conduction state or non-conduction state of the transistor 1213 is selected.
  • the first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214
  • the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214
  • the switch 1204 is input to the gate of the transistor 1214.
  • the control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1214).
  • One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210.
  • the connection part is referred to as a node M2.
  • One of a source and a drain of the transistor 1210 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line), and the other is connected to the first terminal of the switch 1203 (the source and the drain of the transistor 1213 On the other hand).
  • a second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to a first terminal of the switch 1204 (one of the source and the drain of the transistor 1214).
  • a second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring that can supply the power supply potential VDD.
  • a second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), a first terminal of the switch 1204 (one of a source and a drain of the transistor 1214), an input terminal of the logic element 1206, and the capacitor 1207
  • One of the pair of electrodes is electrically connected.
  • the connection part is referred to as a node M1.
  • the other of the pair of electrodes of the capacitor 1207 can be configured to receive a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input.
  • the other of the pair of electrodes of the capacitor 1207 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.
  • the other of the pair of electrodes of the capacitor 1208 can have a constant potential.
  • a low power supply potential such as GND
  • a high power supply potential such as VDD
  • the other of the pair of electrodes of the capacitor 1208 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.
  • the capacitor 1207 and the capacitor 1208 can be omitted by positively using a parasitic capacitance of a transistor or a wiring.
  • a control signal WE is input to the gate of the transistor 1209.
  • the switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE.
  • the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.
  • FIG. 28 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209.
  • a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is an inverted signal obtained by inverting the logic value by the logic element 1206 and is input to the circuit 1201 through the circuit 1220. .
  • FIG. 28 illustrates an example in which a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. It is not limited to. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without inversion of the logical value. For example, when there is a node in the circuit 1201 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) An output signal can be input to the node.
  • a transistor other than the transistor 1209 among the transistors used for the memory element 1200 can be a transistor whose channel is formed in a film or a substrate 1190 made of a semiconductor other than an oxide semiconductor.
  • a transistor in which a channel is formed in a silicon film or a silicon substrate can be used.
  • all the transistors used for the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor.
  • the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor in addition to the transistor 1209, and the remaining transistors are formed using a semiconductor layer other than the oxide semiconductor or the substrate 1190. It can also be a transistor.
  • a flip-flop circuit For the circuit 1201 in FIG. 28, for example, a flip-flop circuit can be used.
  • data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.
  • a transistor in which a channel is formed in an oxide semiconductor has extremely low off-state current.
  • the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 is maintained for a long time even when the power supply voltage is not supplied to the memory element 1200. In this manner, the memory element 1200 can hold stored data (data) even while the supply of power supply voltage is stopped.
  • the memory element is characterized by performing a precharge operation; therefore, after the supply of power supply voltage is resumed, the time until the circuit 1201 retains the original data again is shortened. be able to.
  • the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 is converted into the state of the transistor 1210 (a conductive state or a non-conductive state) and read from the circuit 1202 Can do. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates.
  • a storage element 1200 for a storage device such as a register or a cache memory included in the processor, loss of data in the storage device due to stop of supply of power supply voltage can be prevented.
  • the state before the power supply stop can be restored in a short time. Accordingly, power can be stopped in a short time in the entire processor or in one or a plurality of logic circuits constituting the processor, so that power consumption can be suppressed.
  • the memory element 1200 can be applied to a DSP (Digital Signal Processor), an LSI such as a custom LSI, and an RF (Radio Frequency) device. Further, it can also be applied to LSIs such as programmable logic circuits (PLD: Programmable Logic Devices) such as FPGA (Field Programmable Gate Array) and CPLD (Complex PLD), and RF (Radio Frequency) devices.
  • PLD Programmable Logic Devices
  • FPGA Field Programmable Gate Array
  • CPLD Complex PLD
  • RF Radio Frequency
  • a display element used for the display device As a display element used for the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light-emitting element (also referred to as a light-emitting display element), or the like can be used.
  • the light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electroluminescence), organic EL, and the like.
  • a display device using an EL element an EL display device
  • a display device using a liquid crystal element a liquid crystal display device
  • a display device described below includes a panel in which a display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel.
  • the display device described below refers to an image display device or a light source (including a lighting device).
  • the display device includes all connectors, for example, a module to which FPC and TCP are attached, a module having a printed wiring board at the end of TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by a COG method.
  • FIG. 29 illustrates an example of an EL display device according to one embodiment of the present invention.
  • FIG. 29A shows a circuit diagram of a pixel of an EL display device.
  • FIG. 29B is a top view showing the entire EL display device.
  • FIG. 29C is an MN cross section corresponding to part of the dashed-dotted line MN in FIG.
  • FIG. 29A is an example of a circuit diagram of a pixel used in the EL display device.
  • An EL display device illustrated in FIG. 29A includes a switch element 743, a transistor 741, a capacitor 742, and a light-emitting element 719.
  • FIG. 29A is an example of a circuit configuration, and thus transistors can be added. On the other hand, it is also possible not to add a transistor, a switch, a passive element, or the like at each node in FIG.
  • a gate of the transistor 741 is electrically connected to one end of the switch element 743 and one electrode of the capacitor 742.
  • a source of the transistor 741 is electrically connected to the other electrode of the capacitor 742 and electrically connected to one electrode of the light-emitting element 719.
  • the source of the transistor 741 is supplied with the power supply potential VDD.
  • the other end of the switch element 743 is electrically connected to the signal line 744.
  • a constant potential is applied to the other electrode of the light-emitting element 719. Note that the constant potential is set to the ground potential GND or lower.
  • a transistor is preferably used as the switch element 743.
  • the area of a pixel can be reduced and an EL display device with high resolution can be obtained.
  • the productivity of the EL display device can be increased. Note that as the transistor 741 and / or the switch element 743, for example, the above-described transistor can be used.
  • FIG. 29B is a top view of the EL display device.
  • the EL display device includes a substrate 700, a substrate 750, a sealant 734, a driver circuit 735, a driver circuit 736, a pixel 737, and an FPC 732.
  • the sealant 734 is disposed between the substrate 700 and the substrate 750 so as to surround the pixel 737, the drive circuit 735, and the drive circuit 736. Note that the drive circuit 735 and / or the drive circuit 736 may be disposed outside the sealant 734.
  • FIG. 29C is a cross-sectional view of the EL display device corresponding to part of the dashed-dotted line MN in FIG.
  • the transistor 741 includes an insulator 701 over the substrate 700, a conductor 702a over the insulator 701, an insulator 704 over the conductor 702a, and a conductor 702a over the insulator 704. And the insulator 706a over the insulator 706a, the insulator 706c over the semiconductor 706b, the regions 707a and 707b provided in the insulator 706c and the semiconductor 706b, and the insulator 712 over the insulator 706c. And a conductor 714a over the insulator 712 and an insulator 716 over the insulator 706c and the conductor 714a. Note that the structure of the transistor 741 is an example, and a structure different from the structure illustrated in FIG.
  • the conductor 702a functions as a gate electrode
  • the insulators 712a and 712b function as gate insulators
  • the region 707a serves as a source.
  • the region 707b functions as a drain
  • the insulator 712 functions as a gate insulator
  • the conductor 714a functions as a gate electrode.
  • electrical characteristics of the semiconductor 706b may fluctuate when exposed to light. Therefore, it is preferable that one or more of the conductor 702a and the conductor 714a have a light-shielding property.
  • FIG. 29C as the capacitor 742, a conductor 702b over the insulator 701, an insulator 704 over the conductor 702b, a region 707a over the insulator 704 and overlapping the conductor 702b, and a region 707a
  • a structure including an upper insulator 711 and a conductor 714b which is over the insulator 711 and overlaps with a region 707a is illustrated.
  • the conductor 702b and the conductor 714b function as one electrode, and the region 707a functions as the other electrode.
  • the capacitor 742 can be manufactured using a film in common with the transistor 741.
  • the conductors 702a and 702b are preferably the same kind of conductors. In that case, the conductor 702a and the conductor 702b can be formed through the same process.
  • the conductors 714a and 714b are preferably the same kind of conductors. In that case, the conductor 714a and the conductor 714b can be formed through the same process.
  • the insulator 712 and the insulator 711 are preferably the same kind of insulator. In that case, the insulator 712 and the insulator 711 can be formed through the same process.
  • FIG. 29C illustrates an EL display device with high display quality.
  • An insulator 720 is provided over the transistor 741 and the capacitor 742.
  • the insulator 716 and the insulator 720 may have an opening reaching the region 707 a functioning as the source of the transistor 741.
  • a conductor 781 is provided over the insulator 720. The conductor 781 is electrically connected to the transistor 741 through the opening of the insulator 720.
  • a partition 784 having an opening reaching the conductor 781 is provided over the conductor 781.
  • a light-emitting layer 782 that is in contact with the conductor 781 through the opening of the partition 784 is provided over the partition 784.
  • a conductor 783 is provided over the light-emitting layer 782. A region where the conductor 781, the light emitting layer 782, and the conductor 783 overlap with each other serves as the light emitting element 719.
  • FIG. 30A is a circuit diagram illustrating a configuration example of a pixel of a liquid crystal display device.
  • a pixel illustrated in FIG. 30 includes a transistor 751, a capacitor 752, and an element (liquid crystal element) 753 in which liquid crystal is filled between a pair of electrodes.
  • one of a source and a drain is electrically connected to the signal line 755 and a gate is electrically connected to the scanning line 754.
  • one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential.
  • one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential.
  • the common potential applied to the wiring to which the other electrode of the capacitor 752 is electrically connected may be different from the common potential applied to the other electrode of the liquid crystal element 753.
  • the top view of the liquid crystal display device is the same as that of the EL display device.
  • a cross-sectional view of the liquid crystal display device corresponding to the dashed-dotted line MN in FIG. 29B is illustrated in FIG.
  • the FPC 732 is connected to a wiring 733a through a terminal 731.
  • the wiring 733a may be formed using the same kind of conductor or semiconductor as the conductor or semiconductor included in the transistor 751.
  • FIG. 30B illustrates a structure of the capacitor 752 corresponding to the capacitor 742 in FIG. 29C; however, the structure is not limited thereto.
  • An insulator 721 is provided over the transistor 751 and the capacitor 752.
  • the insulator 721 has an opening reaching the transistor 751.
  • a conductor 791 is provided over the insulator 721. The conductor 791 is electrically connected to the transistor 751 through the opening of the insulator 721.
  • An insulator 792 functioning as an alignment film is provided over the conductor 791.
  • a liquid crystal layer 793 is provided over the insulator 792.
  • An insulator 794 functioning as an alignment film is provided over the liquid crystal layer 793.
  • a spacer 795 is provided over the insulator 794.
  • a conductor 796 is provided over the spacer 795 and the insulator 794.
  • a substrate 797 is provided over the conductor 796.
  • Liquid crystal drive methods include TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, and MVA (Multi-Antificent).
  • TN Transmission Nematic
  • STN Super Twisted Nematic
  • IPS In-Plane-Switching
  • FFS Ringe Field Switching
  • MVA Multi-Antificent
  • PVA Power Vertical Alignment
  • ASV Advanced Super View
  • ASM Axial Symmetrical Aligned Micro-cell
  • OCB Optically Comprehensive BEC ly Controlled Birefringence
  • FLC Fluorroelectric Liquid Crystal
  • AFLC AntiFerroelectric Liquid Crystal
  • PDLC Polymer Dispersed Liquid Crystal
  • guest-host mode guest-host mode
  • blue phase blue Phase
  • the present invention is not limited to this, and various driving methods can be used.
  • a display device including a capacitor with a small occupied area can be provided, or a display device with high display quality can be provided.
  • a high-definition display device can be provided.
  • a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. Can do.
  • a display element, a display device, a light emitting element, or a light emitting device is, for example, a light emitting diode (LED: Light Emitting Diode) such as white, red, green, or blue, a transistor (a transistor that emits light in response to current), an electron emitting element, a liquid crystal Element, electronic ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), display element using MEMS (micro electro mechanical system), digital micromirror device (DMD), DMS (digital Micro shutter), IMOD (interferometric modulation) element, MEMS display element of shutter type, MEMS display element of optical interference type, electrowetting element, piezoelectric ceramic display, car It has at least one such display element using nanotubes.
  • a display medium in which contrast, luminance, reflectance, transmittance, or the like is changed by an electric or magnetic action may be included.
  • An example of a display device using an EL element is an EL display.
  • a display device using an electron-emitting device there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like.
  • FED field emission display
  • SED SED type flat display
  • a display device using a liquid crystal element there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like.
  • An example of a display device using electronic ink or an electrophoretic element is electronic paper.
  • part or all of the pixel electrode may have a function as a reflective electrode.
  • part or all of the pixel electrode may have aluminum, silver, or the like.
  • a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.
  • Graphene or graphite may be a multilayer film in which a plurality of layers are stacked.
  • a nitride semiconductor such as an n-type GaN semiconductor having a crystal can be easily formed thereon.
  • a p-type GaN semiconductor having a crystal or the like can be provided thereon to form an LED.
  • an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor having a crystal.
  • the GaN semiconductor included in the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor included in the LED can be formed by a sputtering method.
  • a semiconductor device includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device).
  • a recording medium typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image
  • a mobile phone in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. It is done. Specific examples of these electronic devices are shown in FIGS.
  • FIG. 31A illustrates a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 31A includes two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.
  • FIG. 31B illustrates a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like.
  • the first display unit 913 is provided in the first housing 911
  • the second display unit 914 is provided in the second housing 912.
  • the first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image
  • a display device in which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used.
  • the function as a position input device can be added by providing a touch panel on the display device.
  • the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.
  • FIG. 31C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.
  • FIG. 31D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.
  • FIG. 31E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like.
  • the operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942.
  • the first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. It is good also as a structure which switches the image
  • FIG. 31F illustrates an automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.
  • a channel formation region of the transistor, a source region, a drain region, and the like of the transistor may include various semiconductors.
  • a channel formation region of the transistor, a source region, a drain region, and the like of the transistor can be formed using, for example, silicon, germanium, silicon germanium, or silicon carbide.
  • Gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included.
  • various transistors, channel formation regions of the transistors, source regions and drain regions of the transistors do not include an oxide semiconductor in one embodiment of the present invention. May be.
  • a sample was formed by forming silicon oxide (SiOx) having a thickness of 50 nm on a Si wafer by a thermal oxidation method, and then forming a W-Si film with a thickness of 50 nm by a sputtering apparatus.
  • SiOx silicon oxide
  • the substrate temperature was controlled at room temperature, and an output of 1 kW was applied to the target from a DC power source.
  • FIG. 32A shows the result of measuring the sample manufactured as described above by XRD.
  • FIG. 32B shows the result of XRD measurement of a sample manufactured by forming a W film with a thickness of 50 nm instead of the W—Si film.
  • FIG. 32A shows that the W—Si film is amorphous with no peak indicating a crystal structure by XRD measurement.
  • the W film showed a peak showing crystals due to the ⁇ -W structure in the vicinity of 40 ° by XRD measurement.

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Abstract

To provide a transistor having excellent electrical characteristics. A semiconductor device having a semiconductor, which has first through third portions, a first insulator on the semiconductor, and a first conductor on the first insulator. The first conductor has a region overlapping with the first portion. The first conductor has a region having tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel. The second portion has one or more of phosphorus, boron, nitrogen, argon, and xenon. The third portion has one or more of phosphorus, boron, nitrogen, argon, and xenon. The first conductor has an amorphous region.

Description

半導体装置およびその作製方法Semiconductor device and manufacturing method thereof
本発明は、例えば、トランジスタおよび半導体装置、ならびにそれらの作製方法に関する。または、本発明は、例えば、表示装置、発光装置、照明装置、蓄電装置、記憶装置、撮像装置、プロセッサ、電子機器に関する。または、表示装置、液晶表示装置、発光装置、記憶装置、撮像装置、電子機器の作製方法に関する。または、半導体装置、表示装置、液晶表示装置、発光装置、記憶装置、電子機器の駆動方法に関する。 The present invention relates to a transistor, a semiconductor device, and a manufacturing method thereof, for example. Alternatively, the present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, a processor, and an electronic device. Alternatively, the present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, an imaging device, or an electronic device. Alternatively, the present invention relates to a driving method of a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device.
なお、本発明の一態様は、上記の技術分野に限定されない。本明細書等で開示する発明の一態様の技術分野は、物、方法、または、作製方法に関するものである。または、本発明の一態様は、プロセス、マシン、マニュファクチャ、または、組成物（コンポジション・オブ・マター）に関するものである。 Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
なお、本明細書等において半導体装置とは、半導体特性を利用することで機能しうる装置全般を指す。表示装置、発光装置、照明装置、電気光学装置、半導体回路および電子機器は、半導体装置を有する場合がある。 Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.
近年は、酸化物半導体を用いたトランジスタが注目されている。酸化物半導体を用いたトランジスタは、非導通状態において極めてリーク電流が小さいことが知られている。例えば、酸化物半導体を用いたトランジスタのリーク電流が低いという特性を応用した低消費電力のＣＰＵなどが開示されている（特許文献１参照。）。 In recent years, transistors using an oxide semiconductor have attracted attention. A transistor using an oxide semiconductor is known to have extremely small leakage current in a non-conduction state. For example, a low power consumption CPU using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).
特開２０１２−２５７１８７号公報JP 2012-257187 A
トップゲート型トランジスタにおけるソース領域およびドレイン領域を形成するために、ゲート電極をマスクにして不純物を添加する場合がある。不純物の添加は、例えばイオン注入によって行うことができるが、トランジスタの微細化に伴い、ゲート電極の高さも小さくなるため、イオン注入時にゲート電極を突き抜けやすくなる。 In order to form the source region and the drain region in the top gate transistor, an impurity may be added using the gate electrode as a mask. The impurity can be added by, for example, ion implantation. However, as the transistor is miniaturized, the height of the gate electrode is reduced, and thus the gate electrode is easily penetrated during ion implantation.
そこで、本発明の一態様は、ゲート電極に用いる導電体のイオン突き抜けを抑制し、良好な電気特性を有するトランジスタを提供することを課題の一とする。 In view of the above, an object of one embodiment of the present invention is to provide a transistor having favorable electric characteristics by suppressing ion penetration of a conductor used for a gate electrode.
また、安定した電気特性を有するトランジスタを提供することを課題の一とする。または、非導通時のリーク電流の小さいトランジスタを提供することを課題の一とする。または、高い周波数特性を有するトランジスタを提供することを課題の一とする。または、ノーマリーオフの電気特性を有するトランジスタを提供することを課題の一とする。または、サブスレッショルドスイング値の小さいトランジスタを提供することを課題の一とする。または、信頼性の高いトランジスタを提供することを課題の一とする。 Another object is to provide a transistor having stable electrical characteristics. Another object is to provide a transistor with low leakage current during non-conduction. Another object is to provide a transistor having high frequency characteristics. Another object is to provide a transistor having normally-off electrical characteristics. Another object is to provide a transistor with a small subthreshold swing value. Another object is to provide a highly reliable transistor.
または、該トランジスタを有する半導体装置を提供することを課題の一とする。または、該半導体装置を有するモジュールを提供することを課題の一とする。または、該半導体装置、または該モジュールを有する電子機器を提供することを課題の一とする。または、新規な半導体装置を提供することを課題の一とする。または、新規なモジュールを提供することを課題の一とする。または、新規な電子機器を提供することを課題の一とする。 Another object is to provide a semiconductor device including the transistor. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. Another object is to provide a new module. Another object is to provide a novel electronic device.
なお、これらの課題の記載は、他の課題の存在を妨げるものではない。なお、本発明の一態様は、これらの課題の全てを解決する必要はないものとする。なお、これら以外の課題は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の課題を抽出することが可能である。 Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.
本発明の一態様は、第１乃至第３の部分を有する半導体と、半導体上の第１の絶縁体と、第１の絶縁体上の第１の導電体と、を有し、第１の導電体は、第１の部分と重なる領域を有し、第１の導電体は、タングステン（Ｗ）と、シリコン（Ｓｉ）、炭素（Ｃ）、ゲルマニウム（Ｇｅ）、スズ（Ｓｎ）、アルミニウム（Ａｌ）またはニッケル（Ｎｉ）から選ばれた一以上の元素と、を有する領域を有し、第２の部分は、リン、ホウ素、窒素、アルゴンまたはキセノンのいずれか一以上を有し、第３の部分は、リン、ホウ素、窒素、アルゴンまたはキセノンのいずれか一以上を有し、第１の導電体は、非晶質である領域を有する半導体装置である。 One embodiment of the present invention includes a semiconductor including first to third portions, a first insulator over the semiconductor, and a first conductor over the first insulator. The conductor has a region overlapping with the first portion. The first conductor includes tungsten (W), silicon (Si), carbon (C), germanium (Ge), tin (Sn), aluminum ( A region having one or more elements selected from Al) or nickel (Ni), the second portion includes one or more of phosphorus, boron, nitrogen, argon, or xenon, and The portion includes at least one of phosphorus, boron, nitrogen, argon, and xenon, and the first conductor is a semiconductor device having a region that is amorphous.
本発明の一態様は、第１の導電体は、ラザフォード後方散乱分析（ＲＢＳ：Ｒｕｔｈｅｒｆｏｒｄ　Ｂａｃｋｓｃａｔｔｅｒｉｎｇ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）により得られるシリコン濃度が５ａｔｏｍｉｃ％以上７０ａｔｏｍｉｃ％以下である領域を有する半導体装置である。 One embodiment of the present invention is a semiconductor device in which the first conductor has a region in which a silicon concentration obtained by Rutherford Backscattering Spectroscopy (RBS) is 5 atomic% or more and 70 atomic% or less.
本発明の一態様は、第１の導電体は、表面にシリコンおよび酸素を有する領域を有し、該領域の厚さは０．２ｎｍ以上２０ｎｍ以下である半導体装置である。 One embodiment of the present invention is a semiconductor device in which the first conductor has a region containing silicon and oxygen on the surface, and the thickness of the region is 0.2 nm to 20 nm.
本発明の一態様は、上記半導体は、酸化物半導体を有する半導体装置である。 One embodiment of the present invention is a semiconductor device in which the semiconductor includes an oxide semiconductor.
本発明の一態様は、半導体を形成し、半導体上に第１の絶縁体を形成し、第１の絶縁体上に第１の導電体を形成し、第１の導電体をマスクにして、半導体にリン（Ｐ）、ホウ素（Ｂ）、窒素（Ｎ）、アルゴン（Ａｒ）またはキセノン（Ｘｅ）のいずれか一以上を添加し、第１の導電体は、タングステンと、シリコン、炭素、ゲルマニウム、スズまたはニッケルから選ばれた一以上の元素と、を有し、第１の導電体は、非晶質である領域を有する半導体装置の作製方法である。 According to one embodiment of the present invention, a semiconductor is formed, a first insulator is formed over the semiconductor, a first conductor is formed over the first insulator, and the first conductor is used as a mask. One or more of phosphorus (P), boron (B), nitrogen (N), argon (Ar), or xenon (Xe) is added to the semiconductor, and the first conductor is tungsten, silicon, carbon, germanium , One or more elements selected from tin or nickel, and the first conductor is a method for manufacturing a semiconductor device having a region that is amorphous.
本発明の一態様は、上記添加は、イオン注入により行う半導体装置の作製方法である。 One embodiment of the present invention is a method for manufacturing a semiconductor device, in which the addition is performed by ion implantation.
本発明の一態様は、第１の導電体は、スパッタリング法を用いて形成する半導体装置の作製方法である。 One embodiment of the present invention is a method for manufacturing a semiconductor device in which the first conductor is formed by a sputtering method.
また、本発明の一態様は、第１の導電体は、金属ＣＶＤ法を用いて形成する半導体装置の作製方法である。 Another embodiment of the present invention is a method for manufacturing a semiconductor device in which the first conductor is formed using a metal CVD method.
本発明の一態様により、ゲート電極に用いる導電体のイオン突き抜けを抑制し、良好な電気特性を有するトランジスタを提供することができる。 According to one embodiment of the present invention, a transistor having favorable electrical characteristics can be provided in which ion penetration of a conductor used for a gate electrode is suppressed.
また、安定した電気特性を有するトランジスタを提供することができる。または、非導通時のリーク電流の小さいトランジスタを提供することができる。または、高い周波数特性を有するトランジスタを提供することができる。または、ノーマリーオフの電気特性を有するトランジスタを提供することができる。または、サブスレッショルドスイング値の小さいトランジスタを提供することができる。または、信頼性の高いトランジスタを提供することができる。 In addition, a transistor having stable electrical characteristics can be provided. Alternatively, a transistor with low leakage current when not conducting can be provided. Alternatively, a transistor having high frequency characteristics can be provided. Alternatively, a transistor having normally-off electrical characteristics can be provided. Alternatively, a transistor with a small subthreshold swing value can be provided. Alternatively, a highly reliable transistor can be provided.
または、該トランジスタを有する半導体装置を提供することができる。または、該半導体装置を有するモジュールを提供することができる。または、該半導体装置、または該モジュールを有する電子機器を提供することができる。または、新規な半導体装置を提供することができる。または、新規なモジュールを提供することができる。または、新規な電子機器を提供することができる。 Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a new module can be provided. Alternatively, a novel electronic device can be provided.
なお、これらの効果の記載は、他の効果の存在を妨げるものではない。なお、本発明の一態様は、これらの効果の全てを有する必要はない。なお、これら以外の効果は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の効果を抽出することが可能である。 Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.
本発明の一態様に係るトランジスタを説明する上面図および断面図。4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. ＣＡＡＣ−ＯＳおよび単結晶酸化物半導体のＸＲＤによる構造解析を説明する図、ならびにＣＡＡＣ−ＯＳの制限視野電子回折パターンを示す図。FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and FIGS. ＣＡＡＣ−ＯＳの断面ＴＥＭ像、ならびに平面ＴＥＭ像およびその画像解析像。Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. ｎｃ−ＯＳの電子回折パターンを示す図、およびｎｃ−ＯＳの断面ＴＥＭ像。The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. ａ−ｌｉｋｅ　ＯＳの断面ＴＥＭ像。Cross-sectional TEM image of a-like OS. Ｉｎ−Ｇａ−Ｚｎ酸化物の電子照射による結晶部の変化を示す図。FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. 本発明の一態様に係るトランジスタを説明する断面図。6A and 6B are cross-sectional views illustrating a transistor according to one embodiment of the present invention. 本発明の一態様に係るトランジスタを説明する断面図。6A and 6B are cross-sectional views illustrating a transistor according to one embodiment of the present invention. 本発明の一態様に係るトランジスタの作製方法を説明する断面図。6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 本発明の一態様に係るトランジスタの作製方法を説明する断面図。6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す回路図。FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す断面図。FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す断面図。FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す断面図。FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置を示す回路図。FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す断面図。FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す断面図。FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す断面図。FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す回路図。FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す断面図。FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す回路図。FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す上面図。FIG. 6 is a top view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示すブロック図。1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す断面図。FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す断面図。FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す斜視図および断面図。4A and 4B are a perspective view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示すブロック図。1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す回路図。FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す回路図、上面図および断面図。4A and 4B are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す回路図および断面図。6A and 6B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る電子機器を示す斜視図。FIG. 11 is a perspective view illustrating an electronic device according to one embodiment of the present invention. 試料のＸＲＤ結果を説明する図。The figure explaining the XRD result of a sample.
本発明の実施の形態について、図面を用いて詳細に説明する。ただし、本発明は以下の説明に限定されず、その形態および詳細を様々に変更し得ることは、当業者であれば容易に理解される。また、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。なお、図面を用いて発明の構成を説明するにあたり、同じものを指す符号は異なる図面間でも共通して用いる。なお、同様のものを指す際にはハッチパターンを同じくし、特に符号を付さない場合がある。 Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed. In addition, the present invention is not construed as being limited to the description of the embodiments below. Note that in describing the structure of the present invention with reference to drawings, the same portions are denoted by the same reference numerals in different drawings. In addition, when referring to the same thing, a hatch pattern is made the same and there is a case where it does not attach a code in particular.
以下の実施の形態に示す構成は、実施の形態に示す他の構成に対して適宜、適用、組み合わせ、または置き換えなどを行って、本発明の一態様とすることができる。 The structures described in the following embodiments can be applied to, combined with, or replaced with the other structures described in the embodiments as appropriate, according to one embodiment of the present invention.
なお、図において、大きさ、膜（層）の厚さ、または領域は、明瞭化のために誇張されている場合がある。 Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.
なお、本明細書において、「膜」という表記と、「層」という表記と、を互いに入れ替えることが可能である。 Note that in this specification, the expression “film” and the expression “layer” can be interchanged with each other.
なお、本明細書などにおいて、「部分」という表記と、「領域」という表記と、を互いに入れ替えて用いることが可能である。 Note that in this specification and the like, the expression “part” and the expression “region” can be used interchangeably.
また、電圧は、ある電位と、基準の電位（例えば接地電位（ＧＮＤ）またはソース電位）との電位差のことを示す場合が多い。よって、電圧を電位と言い換えることが可能である。一般的に、電位（電圧）は、相対的なものであり、基準の電位からの相対的な大きさによって決定される。したがって、「接地電位」などと記載されている場合であっても、電位が０Ｖであるとは限らない。例えば、回路で最も低い電位が、「接地電位」となる場合もある。または、回路で中間くらいの電位が、「接地電位」となる場合もある。その場合には、その電位を基準として、正の電位と負の電位が規定される。 In many cases, the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential. Generally, the potential (voltage) is relative and is determined by a relative magnitude from a reference potential. Therefore, even when “ground potential” is described, the potential is not always 0V. For example, the lowest potential in the circuit may be the “ground potential”. Alternatively, an intermediate potential in the circuit may be a “ground potential”. In that case, a positive potential and a negative potential are defined based on the potential.
なお、第１、第２として付される序数詞は便宜的に用いるものであり、工程順または積層順を示すものではない。そのため、例えば、「第１の」を「第２の」または「第３の」などと適宜置き換えて説明することができる。また、本明細書などに記載されている序数詞と、本発明の一態様を特定するために用いられる序数詞は一致しない場合がある。 The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
半導体の不純物とは、例えば、半導体を構成する主成分以外をいう。例えば、濃度が０．１原子％（ａｔｏｍｉｃ％ともいう）未満の元素は不純物である。不純物が含まれることにより、例えば、半導体にＤＯＳ（Ｄｅｎｓｉｔｙ　ｏｆ　Ｓｔａｔｅ）が形成されることや、キャリア移動度が低下することや、結晶性が低下することなどが起こる場合がある。半導体が酸化物半導体である場合、半導体の特性を変化させる不純物としては、例えば、第１族元素、第２族元素、第１３族元素、第１４族元素、第１５族元素、主成分以外の遷移金属などがあり、特に、例えば、水素（水にも含まれる）、リチウム、ナトリウム、シリコン、ホウ素、リン、炭素、窒素などがある。酸化物半導体の場合、例えば水素などの不純物の混入によって酸素欠損を形成する場合がある。また、半導体がシリコン層である場合、半導体の特性を変化させる不純物としては、例えば、酸素、水素を除く第１族元素、第２族元素、第１３族元素、第１５族元素などがある。 A semiconductor impurity means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% (also referred to as atomic%) is an impurity. By including impurities, for example, DOS (Density of State) may be formed in a semiconductor, carrier mobility may be reduced, and crystallinity may be reduced. In the case where the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and components other than main components Examples include transition metals, and in particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
なお、チャネル長とは、例えば、トランジスタの上面図において、半導体（またはトランジスタがオン状態のときに半導体の中で電流の流れる部分）とゲート電極とが互いに重なる領域、またはチャネルが形成される領域における、ソース（ソース領域またはソース電極）とドレイン（ドレイン領域またはドレイン電極）との間の距離をいう。なお、一つのトランジスタにおいて、チャネル長が全ての領域で同じ値をとるとは限らない。即ち、一つのトランジスタのチャネル長は、一つの値に定まらない場合がある。そのため、本明細書では、チャネル長は、チャネルの形成される領域における、いずれか一の値、最大値、最小値または平均値とする。 Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
チャネル幅とは、例えば、半導体（またはトランジスタがオン状態のときに半導体の中で電流の流れる部分）とゲート電極とが互いに重なる領域、またはチャネルが形成される領域における、ソースとドレインとが向かい合っている部分の長さをいう。なお、一つのトランジスタにおいて、チャネル幅がすべての領域で同じ値をとるとは限らない。即ち、一つのトランジスタのチャネル幅は、一つの値に定まらない場合がある。そのため、本明細書では、チャネル幅は、チャネルの形成される領域における、いずれか一の値、最大値、最小値または平均値とする。 The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
なお、トランジスタの構造によっては、実際にチャネルの形成される領域におけるチャネル幅（以下、実効的なチャネル幅と呼ぶ。）と、トランジスタの上面図において示されるチャネル幅（以下、見かけ上のチャネル幅と呼ぶ。）と、が異なる場合がある。例えば、立体的な構造を有するトランジスタでは、実効的なチャネル幅が、トランジスタの上面図において示される見かけ上のチャネル幅よりも大きくなり、その影響が無視できなくなる場合がある。例えば、微細かつ立体的な構造を有するトランジスタでは、半導体の側面に形成されるチャネル領域の割合が大きくなる場合がある。その場合は、上面図において示される見かけ上のチャネル幅よりも、実際にチャネルの形成される実効的なチャネル幅の方が大きくなる。 Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.
ところで、立体的な構造を有するトランジスタにおいては、実効的なチャネル幅の、実測による見積もりが困難となる場合がある。例えば、設計値から実効的なチャネル幅を見積もるためには、半導体の形状が既知という仮定が必要である。したがって、半導体の形状が正確にわからない場合には、実効的なチャネル幅を正確に測定することは困難である。 By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.
そこで、本明細書では、トランジスタの上面図において、半導体とゲート電極とが互いに重なる領域における、ソースとドレインとが向かい合っている部分の長さである見かけ上のチャネル幅を、「囲い込みチャネル幅（ＳＣＷ：Ｓｕｒｒｏｕｎｄｅｄ　Ｃｈａｎｎｅｌ　Ｗｉｄｔｈ）」と呼ぶ場合がある。また、本明細書では、単にチャネル幅と記載した場合には、囲い込みチャネル幅または見かけ上のチャネル幅を指す場合がある。または、本明細書では、単にチャネル幅と記載した場合には、実効的なチャネル幅を指す場合がある。なお、チャネル長、チャネル幅、実効的なチャネル幅、見かけ上のチャネル幅、囲い込みチャネル幅などは、断面ＴＥＭ像などを取得して、その画像を解析することなどによって、値を決定することができる。 Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is expressed as “enclosed channel width ( SCW: Surrounded Channel Width). In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.
なお、トランジスタの電界効果移動度や、チャネル幅当たりの電流値などを計算して求める場合、囲い込みチャネル幅を用いて計算する場合がある。その場合には、実効的なチャネル幅を用いて計算する場合とは異なる値をとる場合がある。 Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.
なお、本明細書において、ＡがＢより迫り出した形状を有すると記載する場合、上面図または断面図において、Ａの少なくとも一端が、Ｂの少なくとも一端よりも外側にある形状を有することを示す場合がある。したがって、ＡがＢより迫り出した形状を有すると記載されている場合、例えば上面図において、Ａの一端が、Ｂの一端よりも外側にある形状を有すると読み替えることができる。 Note that in this specification, when A is described as having a shape protruding from B, in a top view or a cross-sectional view, it indicates that at least one end of A has a shape that is outside of at least one end of B. There is a case. Therefore, when it is described that A has a shape protruding from B, for example, in a top view, it can be read that one end of A has a shape outside of one end of B.
なお、本明細書において、単に半導体と記載される場合、様々な半導体に置き換えることができる場合がある。例えば、シリコン、ゲルマニウムなどの第１４族半導体、酸化物半導体、炭化シリコン、ケイ化ゲルマニウム、ヒ化ガリウム、リン化インジウム、セレン化亜鉛、硫化カドミウムなどの化合物半導体、および有機半導体に置き換えることができる。 Note that in this specification, in the case where the term “semiconductor” is simply used, it may be replaced with various kinds of semiconductors. For example, a group 14 semiconductor such as silicon and germanium, an oxide semiconductor, silicon carbide, germanium silicide, gallium arsenide, indium phosphide, zinc selenide, cadmium sulfide, and other compound semiconductors and organic semiconductors can be used. .
本明細書において、「平行」とは、二つの直線が−１０°以上１０°以下の角度で配置されている状態をいう。したがって、−５°以上５°以下の場合も含まれる。また、「略平行」とは、二つの直線が−３０°以上３０°以下の角度で配置されている状態をいう。また、「垂直」とは、二つの直線が８０°以上１００°以下の角度で配置されている状態をいう。したがって、８５°以上９５°以下の場合も含まれる。また、「略垂直」とは、二つの直線が６０°以上１２０°以下の角度で配置されている状態をいう。 In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
また、本明細書において、結晶が三方晶または菱面体晶である場合、六方晶系として表す。 In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.
（実施の形態１）
本実施の形態では、本発明の一態様に係る半導体装置の構成について、図１乃至図８を用いて説明する。 (Embodiment 1)
In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.
＜トランジスタの構成＞
以下では、本発明の一態様に係る半導体装置の一例としてトランジスタの構成について説明する。 <Structure of transistor>
The structure of a transistor is described below as an example of a semiconductor device according to one embodiment of the present invention.
図１（Ａ）乃至図１（Ｃ）を用いてトランジスタ１０の構成について説明する。図１（Ａ）はトランジスタ１０の上面図である。図１（Ｂ）は図１（Ａ）の一点鎖線Ａ１−Ａ２に対応する断面図である。図１（Ｃ）は図１（Ａ）の一点鎖線Ａ３−Ａ４に対応する断面図である。なお、図１（Ｂ）は、トランジスタ１０のチャネル長方向における構造を示しており、図１（Ｃ）は、トランジスタ１０のチャネル幅方向における構造を示している。なお、トランジスタのチャネル長方向とは、ソース（ソース領域またはソース電極）およびドレイン（ドレイン領域またはドレイン電極）間において、キャリアが移動する方向を意味し、チャネル幅方向は、基板と水平な面内において、チャネル長方向に対して垂直の方向を意味する。なお、図１（Ａ）は、煩雑になることを避けるため、トランジスタ１０の構成要素の一部（保護絶縁膜として機能する絶縁膜等）を省略して図示している。なお、トランジスタの上面図は、以降の図面においても図１（Ａ）と同様に、構成要素の一部を省略して図示する場合がある。 A structure of the transistor 10 is described with reference to FIGS. FIG. 1A is a top view of the transistor 10. FIG. 1B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. FIG. 1C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG. Note that FIG. 1B illustrates the structure of the transistor 10 in the channel length direction, and FIG. 1C illustrates the structure of the transistor 10 in the channel width direction. Note that the channel length direction of a transistor means a direction in which carriers move between a source (source region or source electrode) and a drain (drain region or drain electrode), and the channel width direction is in a plane parallel to the substrate. Means a direction perpendicular to the channel length direction. Note that FIG. 1A omits some components (such as an insulating film functioning as a protective insulating film) of the transistor 10 in order to avoid complexity. Note that the top view of the transistor may be illustrated with some components omitted in the following drawings as in FIG.
トランジスタ１０は、半導体１０６ｂと、導電体１１４と、絶縁体１０６ａと、絶縁体１０６ｃと、絶縁体１１２と、絶縁体１１６と、を有する。半導体１０６ｂは、絶縁体１０６ａ上に配置され、絶縁体１０６ｃは、半導体１０６ｂ上に配置され、絶縁体１１２は、絶縁体１０６ｃ上に配置され、導電体１１４は、絶縁体１１２上に配置される。絶縁体１１６は、導電体１１４上に配置され、絶縁体１１６は、絶縁体１０６ｃの上面と接する領域を有し、半導体１０６ｂは、絶縁体１０６ｃおよび絶縁体１１２を介して導電体１１４と重なる領域を有する。図１（Ａ）に示すように上面から見たとき、絶縁体１０６ａの外周が半導体１０６ｂの外周と概略一致し、絶縁体１０６ｃの外周が絶縁体１０６ａおよび半導体１０６ｂの外周よりも外側に位置することが好ましい。 The transistor 10 includes a semiconductor 106b, a conductor 114, an insulator 106a, an insulator 106c, an insulator 112, and an insulator 116. The semiconductor 106b is disposed on the insulator 106a, the insulator 106c is disposed on the semiconductor 106b, the insulator 112 is disposed on the insulator 106c, and the conductor 114 is disposed on the insulator 112. . The insulator 116 is provided over the conductor 114. The insulator 116 has a region in contact with the top surface of the insulator 106c. The semiconductor 106b overlaps with the conductor 114 with the insulator 106c and the insulator 112 interposed therebetween. Have As shown in FIG. 1A, when viewed from the top, the outer periphery of the insulator 106a substantially matches the outer periphery of the semiconductor 106b, and the outer periphery of the insulator 106c is located outside the outer periphery of the insulator 106a and the semiconductor 106b. It is preferable.
図１（Ａ）乃至図１（Ｃ）に示すように、トランジスタ１０は、基板１００の上に形成された絶縁体１０１、導電体１０２、絶縁体１０３および絶縁体１０４と、絶縁体１０４上に形成された絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃと、絶縁体１０６ｃ上に形成された絶縁体１１２および導電体１１４と、導電体１１４上に形成された絶縁体１１６、絶縁体１１８、導電体１０８ａ、導電体１０８ｂ、導電体１０９ａおよび導電体１０９ｂと、を有する。 As shown in FIGS. 1A to 1C, the transistor 10 includes an insulator 101, a conductor 102, an insulator 103, and an insulator 104 which are formed over a substrate 100, and the insulator 104. Insulator 106a, semiconductor 106b and insulator 106c formed, insulator 112 and conductor 114 formed on insulator 106c, insulator 116, insulator 118 formed on conductor 114, conductor 108a, a conductor 108b, a conductor 109a, and a conductor 109b.
ここで、絶縁体１０１、絶縁体１０３、絶縁体１０４、絶縁体１０６ａ、絶縁体１０６ｃ、絶縁体１１２、絶縁体１１６および絶縁体１１８は、絶縁膜または絶縁層ということもできる。また、導電体１０２、導電体１０８ａ、導電体１０８ｂ、導電体１０９ａ、導電体１０９ｂおよび導電体１１４は、導電膜または導電層ということもできる。また、半導体１０６ｂは、半導体膜または半導体層ということもできる。 Here, the insulator 101, the insulator 103, the insulator 104, the insulator 106a, the insulator 106c, the insulator 112, the insulator 116, and the insulator 118 can also be referred to as insulating films or insulating layers. The conductor 102, the conductor 108a, the conductor 108b, the conductor 109a, the conductor 109b, and the conductor 114 can also be referred to as conductive films or conductive layers. The semiconductor 106b can also be referred to as a semiconductor film or a semiconductor layer.
基板１００上に形成された絶縁体１０１の上に絶縁体１０３が形成され、絶縁体１０３に埋め込まれるように導電体１０２が形成されている。絶縁体１０３および導電体１０２上に絶縁体１０４が形成されている。ここで、絶縁体１０１は酸素、水素、水等に対してブロッキング効果を有する絶縁体を用いることが好ましい。また、絶縁体１０４は酸素を含む絶縁体を用いることが好ましい。 An insulator 103 is formed over an insulator 101 formed over the substrate 100, and a conductor 102 is formed so as to be embedded in the insulator 103. An insulator 104 is formed over the insulator 103 and the conductor 102. Here, the insulator 101 is preferably an insulator having a blocking effect against oxygen, hydrogen, water, or the like. The insulator 104 is preferably an insulator containing oxygen.
絶縁体１０４の上に絶縁体１０６ａが形成され、絶縁体１０６ａの上面に接して半導体１０６ｂが形成され、絶縁体１０６ａの上面と半導体１０６ｂの上面に接して絶縁体１０６ｃが形成される。ここで、半導体１０６ｂは少なくとも一部が、導電体１０２と重なるように形成されることが好ましい。絶縁体１０６ａの側面端部、特にチャネル幅方向の側面端部と、半導体１０６ｂの側面端部、特にチャネル幅方向の側面端部と、が概略一致する形状となっている。さらに、半導体１０６ｂの側面端部、特にチャネル幅方向の側面端部が、絶縁体１０６ｃと接して設けられている。このように本実施の形態に示すトランジスタ１０は、半導体１０６ｂが絶縁体１０６ａおよび絶縁体１０６ｃに包み込まれるように設けられている。 An insulator 106a is formed over the insulator 104, a semiconductor 106b is formed in contact with the upper surface of the insulator 106a, and an insulator 106c is formed in contact with the upper surface of the insulator 106a and the upper surface of the semiconductor 106b. Here, it is preferable that at least a part of the semiconductor 106 b overlap with the conductor 102. The side end of the insulator 106a, particularly the side end in the channel width direction, and the side end of the semiconductor 106b, particularly the side end in the channel width direction, are approximately matched. Further, a side surface end of the semiconductor 106b, particularly a side surface end in the channel width direction, is provided in contact with the insulator 106c. As described above, the transistor 10 described in this embodiment is provided so that the semiconductor 106b is surrounded by the insulator 106a and the insulator 106c.
また、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃは、酸化物半導体を用いることが好ましい。なお、トランジスタ１０に絶縁体１０６ａまたは絶縁体１０６ｃを設けない構成としてもよい。 The insulator 106a, the semiconductor 106b, and the insulator 106c are preferably formed using an oxide semiconductor. Note that the transistor 10 may not be provided with the insulator 106a or the insulator 106c.
また、絶縁体１０６ａおよび絶縁体１０６ｃは、単独で用いる場合、導電体または半導体として機能させることができる材料を用いる場合がある。しかし、半導体１０６ｂと積層させてトランジスタを形成する場合、キャリアは半導体１０６ｂ、半導体１０６ｂと絶縁体１０６ａの界面近傍、および半導体１０６ｂと絶縁体１０６ｃの界面近傍を流れ、絶縁体１０６ａおよび絶縁体１０６ｃは当該トランジスタのチャネルとして機能しない領域を有する。このため、本明細書などにおいては、絶縁体１０６ａおよび絶縁体１０６ｃは導電体および半導体と記載せず、絶縁体と記載するものとする。 The insulator 106a and the insulator 106c may be formed using a material that can function as a conductor or a semiconductor when used alone. However, in the case of forming a transistor by stacking with the semiconductor 106b, carriers flow in the vicinity of the semiconductor 106b, the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106c, and the insulator 106a and the insulator 106c The transistor does not function as a channel of the transistor. Therefore, in this specification and the like, the insulator 106a and the insulator 106c are not described as conductors and semiconductors but as insulators.
なお、図１（Ｂ）および図１（Ｃ）では、絶縁体１０６ｃの外周が絶縁体１０６ａの外周より外側に位置する形状となっているが、本実施の形態に示すトランジスタはこれに限られない。例えば、絶縁体１０６ａの外周が絶縁体１０６ｃの外周より外側に位置してもよいし、絶縁体１０６ａの側面端部と、絶縁体１０６ｃの側面端部とが概略一致する形状としてもよい。 Note that in FIGS. 1B and 1C, the outer periphery of the insulator 106c is located outside the outer periphery of the insulator 106a; however, the transistor described in this embodiment is not limited to this. Absent. For example, the outer periphery of the insulator 106a may be positioned outside the outer periphery of the insulator 106c, or the side surface end portion of the insulator 106a and the side surface end portion of the insulator 106c may be approximately matched.
本実施の形態に示すトランジスタ１０の、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃには、領域１２６ａ、領域１２６ｂおよび領域１２６ｃが形成されている。領域１２６ｂおよび領域１２６ｃは、領域１２６ａと比べてドーパントの濃度が高く、低抵抗化された領域である。なお、ドーパントは、ドナー、アクセプター、不純物または元素と言い換えてもよい。また、領域１２６ｂおよび領域１２７ｃは、それぞれトランジスタ１０のソース領域またはドレイン領域のいずれか一方および他方として機能することができる。 In the transistor 10 described in this embodiment, a region 126a, a region 126b, and a region 126c are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c. The region 126b and the region 126c have a higher dopant concentration than the region 126a and have low resistance. Note that a dopant may be paraphrased as a donor, an acceptor, an impurity, or an element. In addition, the region 126b and the region 127c can function as either one or the other of the source region or the drain region of the transistor 10, respectively.
図１（Ｄ）に、図１（Ｂ）に示すトランジスタ１０の導電体１１４近傍の拡大図を示す。図１（Ｄ）に示すように、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃにおいて、領域１２６ａは導電体１１４と概ね重なる領域である。なお、領域１２６ｂおよび領域１２６ｃの一部が、半導体１０６ｂの導電体１１４と重なる領域（チャネル形成領域ともいう。）の一部と重なっていてもよい。 FIG. 1D is an enlarged view of the vicinity of the conductor 114 of the transistor 10 illustrated in FIG. As shown in FIG. 1D, in the insulator 106a, the semiconductor 106b, and the insulator 106c, the region 126a is a region that substantially overlaps with the conductor 114. Note that part of the regions 126b and 126c may overlap with part of a region overlapping with the conductor 114 of the semiconductor 106b (also referred to as a channel formation region).
なお、領域１２６ｂおよび領域１２６ｃは、イオン注入またはイオンドーピングなどを用いて形成することができる。 Note that the region 126b and the region 126c can be formed by ion implantation, ion doping, or the like.
また、領域１２６ｂおよび領域１２６ｃは、リン、ホウ素、窒素、アルゴンまたはキセノンのいずれか一以上を有すると好ましい。それにより、領域１２６ｂおよび領域１２６ｃの抵抗値を低減させることができる。 The region 126b and the region 126c preferably include one or more of phosphorus, boron, nitrogen, argon, and xenon. Thereby, the resistance values of the region 126b and the region 126c can be reduced.
また、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃの絶縁体１１６との界面近傍（図１（Ｂ）では点線で表示）に低抵抗領域１０７ａおよび低抵抗領域１０７ｂが形成されていてもよい。低抵抗領域１０７ａおよび低抵抗領域１０７ｂは、絶縁体１１６に含まれる元素の少なくとも一が含まれることがある。また、低抵抗領域１０７ａおよび低抵抗領域１０７ｂの一部が、半導体１０６ｂの導電体１１４と重なる領域（チャネル形成領域）と概略接するか、当該領域の一部と重なることが好ましい。 Further, the low resistance region 107a and the low resistance region 107b may be formed in the vicinity of the interface of the insulator 106a, the semiconductor 106b, and the insulator 106c with the insulator 116 (indicated by a dotted line in FIG. 1B). The low resistance region 107a and the low resistance region 107b may include at least one element included in the insulator 116. In addition, it is preferable that a part of the low resistance region 107a and the low resistance region 107b be substantially in contact with a region (channel formation region) that overlaps with the conductor 114 of the semiconductor 106b or overlap with a part of the region.
領域１２６ｂ、領域１２６ｃ、低抵抗領域１０７ａおよび低抵抗領域１０７ｂが形成されることにより、導電体１０８ａおよび導電体１０８ｂと半導体１０６ｂとの、または導電体１０８ａおよび導電体１０８ｂと絶縁体１０６ｃとの接触抵抗を低減することが可能となる。それによりトランジスタ１０のオン電流を増大させることができる。 By forming the region 126b, the region 126c, the low resistance region 107a, and the low resistance region 107b, the conductor 108a and the conductor 108b and the semiconductor 106b, or the conductor 108a and the conductor 108b and the insulator 106c are in contact with each other. The resistance can be reduced. Accordingly, the on-state current of the transistor 10 can be increased.
なお、図１（Ａ）乃至（Ｄ）に示すトランジスタ１０は低抵抗領域１０７ａおよび低抵抗領域１０７ｂが形成される構成としているが、本実施の形態に示す半導体装置は、必ずしもこれに限られるものではない。例えば、領域１２６ｂおよび領域１２６ｃの抵抗が十分低い場合、低抵抗領域１０７ａおよび低抵抗領域１０７ｂが形成されていなくてもよい。 Note that the transistor 10 illustrated in FIGS. 1A to 1D has a structure in which the low-resistance region 107a and the low-resistance region 107b are formed; however, the semiconductor device described in this embodiment is not limited to this. is not. For example, when the resistance of the region 126b and the region 126c is sufficiently low, the low resistance region 107a and the low resistance region 107b may not be formed.
絶縁体１１２および導電体１１４は、少なくとも一部が導電体１０２および半導体１０６ｂと重なって設けられる。導電体１１４のチャネル長方向の側面端部と絶縁体１１２のチャネル長方向の側面端部は概略一致していることが好ましい。ここで、絶縁体１１２はトランジスタ１０のゲート絶縁膜として機能し、導電体１１４はトランジスタ１０のゲート電極として機能する。 The insulator 112 and the conductor 114 are provided so that at least a part thereof overlaps with the conductor 102 and the semiconductor 106b. It is preferable that the side surface end portion of the conductor 114 in the channel length direction and the side surface end portion of the insulator 112 in the channel length direction substantially coincide. Here, the insulator 112 functions as a gate insulating film of the transistor 10, and the conductor 114 functions as a gate electrode of the transistor 10.
絶縁体１１６は、トランジスタ１０の保護絶縁膜として機能することができ、絶縁体１１８は、トランジスタ１０の層間絶縁膜として機能することができる。絶縁体１１６は、酸素に対してブロッキング効果を有する絶縁体を用いることが好ましい。例えば、絶縁体１１８より、絶縁体１１６の酸素の拡散係数が小さいと好ましい。 The insulator 116 can function as a protective insulating film of the transistor 10, and the insulator 118 can function as an interlayer insulating film of the transistor 10. As the insulator 116, an insulator having a blocking effect on oxygen is preferably used. For example, it is preferable that the oxygen diffusion coefficient of the insulator 116 be smaller than that of the insulator 118.
図１（Ｃ）に示すように、導電体１０２および導電体１１４による電界によって、半導体１０６ｂを電気的に取り囲むことができる（なお、導電体から生じる電界によって、半導体を電気的に取り囲むトランジスタの構造を、ｓｕｒｒｏｕｎｄｅｄ　ｃｈａｎｎｅｌ（ｓ−ｃｈａｎｎｅｌ）構造とよぶ。）。そのため、半導体１０６ｂの全体（上面、下面および側面）にチャネルが形成される。ｓ−ｃｈａｎｎｅｌ構造では、トランジスタのソースおよびドレイン間に大きな電流を流すことができ、導通時の電流（オン電流）を高くすることができる。 As shown in FIG. 1C, the semiconductor 106b can be electrically surrounded by an electric field generated by the conductor 102 and the conductor 114 (note that the structure of the transistor that electrically surrounds the semiconductor by the electric field generated from the conductor) Is called a surround channel (s-channel) structure.). Therefore, a channel is formed in the entire semiconductor 106b (upper surface, lower surface, and side surface). In the s-channel structure, a large current can flow between the source and the drain of the transistor, and a current (on-state current) at the time of conduction can be increased.
高いオン電流が得られるため、ｓ−ｃｈａｎｎｅｌ構造は、微細化されたトランジスタに適した構造といえる。トランジスタを微細化できるため、該トランジスタを有する半導体装置は、集積度の高い、高密度化された半導体装置とすることが可能となる。例えば、トランジスタは、チャネル長が好ましくは４０ｎｍ以下、より好ましくは３０ｎｍ以下、さらに好ましくは２０ｎｍ以下の領域を有し、かつ、トランジスタは、チャネル幅が好ましくは４０ｎｍ以下、より好ましくは３０ｎｍ以下、さらに好ましくは２０ｎｍ以下の領域を有する。 Since a high on-state current can be obtained, the s-channel structure can be said to be a structure suitable for a miniaturized transistor. Since a transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration. For example, the transistor has a channel length of preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less, and the transistor preferably has a channel width of 40 nm or less, more preferably 30 nm or less, and further Preferably, it has a region of 20 nm or less.
絶縁体１１８、絶縁体１１６および絶縁体１０６ｃに設けられた開口部に、導電体１０８ａおよび導電体１０８ｂが形成され、導電体１０８ａ、導電体１０８ｂのそれぞれが低抵抗領域１０７ａおよび低抵抗領域１０７ｂに接している。さらに絶縁体１１８の上に、導電体１０８ａの上面に接して導電体１０９ａが形成され、導電体１０８ｂの上面に接して導電体１０９ｂが形成されている。導電体１０８ａと導電体１０８ｂは離間して形成されており、図１（Ｂ）に示すように導電体１１４を挟んで対向して形成されていることが好ましい。ここで、導電体１０８ａは、トランジスタ１０のソース電極またはドレイン電極の一方として機能し、導電体１０８ｂは、トランジスタ１０のソース電極またはドレイン電極の他方として機能する。また、導電体１０９ａは、トランジスタ１０のソース電極またはドレイン電極の一方と接続される配線として機能し、導電体１０９ｂは、トランジスタ１０のソース電極またはドレイン電極の他方と接続される配線として機能する。 A conductor 108a and a conductor 108b are formed in openings provided in the insulator 118, the insulator 116, and the insulator 106c, and the conductor 108a and the conductor 108b are formed in the low resistance region 107a and the low resistance region 107b, respectively. It touches. Further, a conductor 109a is formed over the insulator 118 in contact with the upper surface of the conductor 108a, and a conductor 109b is formed in contact with the upper surface of the conductor 108b. The conductor 108a and the conductor 108b are formed apart from each other, and are preferably formed to face each other with the conductor 114 interposed therebetween as shown in FIG. Here, the conductor 108a functions as one of a source electrode and a drain electrode of the transistor 10, and the conductor 108b functions as the other of the source electrode and the drain electrode of the transistor 10. The conductor 109a functions as a wiring connected to one of the source electrode and the drain electrode of the transistor 10, and the conductor 109b functions as a wiring connected to the other of the source electrode and the drain electrode of the transistor 10.
なお、図１（Ｂ）では、導電体１０８ａおよび導電体１０８ｂは半導体１０６ｂに接して設けられているが、本実施の形態はこれに限られるものではない。低抵抗領域１０７ａおよび低抵抗領域１０７ｂとの接触抵抗が十分低いなら、絶縁体１０６ｃが開口を有さず、導電体１０８ａおよび導電体１０８ｂと、絶縁体１０６ｃと、が接する構成としてもよい。 Note that in FIG. 1B, the conductor 108a and the conductor 108b are provided in contact with the semiconductor 106b; however, this embodiment is not limited thereto. If the contact resistance between the low resistance region 107a and the low resistance region 107b is sufficiently low, the insulator 106c may have no opening, and the conductor 108a and the conductor 108b may be in contact with the insulator 106c.
また、導電体１１４は、タングステンと、シリコン、炭素、ゲルマニウム、スズ、アルミニウムまたはニッケルから選ばれた一以上の元素と、を有する領域を有すると好ましい。それにより、非晶質の導電体１１４を形成することができる。 The conductor 114 preferably includes a region having tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, or nickel. Thereby, an amorphous conductor 114 can be formed.
特に、導電体１１４はタングステンとシリコンと、を有する領域を有する導電体を用いると好ましい。また、該導電体は、ＲＢＳにより得られるシリコン濃度が５ａｔｏｍｉｃ％以上７０ａｔｏｍｉｃ％以下である領域を有すると好ましい。 In particular, the conductor 114 is preferably a conductor having a region containing tungsten and silicon. The conductor preferably has a region where the silicon concentration obtained by RBS is 5 atomic% or more and 70 atomic% or less.
また、例えばスパッタリング法により被形成面にタングステンを成膜すると、結晶性を有する導電体となる場合がある。そのため、導電体の表面平坦性が悪くなることがある。しかし、本発明に示すようなタングステンとシリコンと、を有する領域を有する導電体を用いることによって、非晶質を有する導電体をトランジスタ１０に形成することができる。それにより、良好な表面平坦性を有する導電体を形成しやすい。さらに、該導電体は非晶質である領域を有するため、イオン注入などによるイオンの突き抜けを抑制することができる。 Further, when tungsten is formed over the surface to be formed by, for example, a sputtering method, a conductor having crystallinity may be obtained. Therefore, the surface flatness of the conductor may be deteriorated. However, an amorphous conductor can be formed in the transistor 10 by using a conductor having a region including tungsten and silicon as shown in the present invention. Thereby, it is easy to form a conductor having good surface flatness. Further, since the conductor has an amorphous region, penetration of ions due to ion implantation or the like can be suppressed.
また、半導体装置の集積化などにより、例えばトランジスタが微細化されるにつれて、該トランジスタを構成する絶縁体、半導体、導電体などのサイズが小さくなり、また膜厚も薄くなる。そのため、導電体をマスクにした場合においても、イオン注入において注入したイオンが該導電体を突き抜けやすくなってしまうが、本発明の一態様に示す導電体１１４のように、非晶質である領域を有する導電体を用いることによって、イオンが該導電体を突き抜けることを抑制したトランジスタを形成することができる。 Further, with the integration of semiconductor devices and the like, for example, as a transistor is miniaturized, the size of an insulator, a semiconductor, a conductor, and the like included in the transistor is reduced, and the film thickness is also reduced. Therefore, even when a conductor is used as a mask, ions implanted in ion implantation are likely to penetrate the conductor. However, an amorphous region such as the conductor 114 described in one embodiment of the present invention can be used. By using a conductor having the above, a transistor in which ions are prevented from penetrating through the conductor can be formed.
また、タングステンとシリコンと、を有する領域を有する導電体は、該導電体の表面にシリコンおよび酸素を有する領域を有し、該領域の厚さは０．２ｎｍ以上２０ｎｍ以下であると好ましい。該領域は、シリコンと酸素が多く含まれた領域とすることができ、その場合、該領域は絶縁体として機能することができる。また、該領域が酸素の浸入を抑制するバリア層として機能することによって、導電体全体が酸化されるのを抑制することができる。 A conductor having a region containing tungsten and silicon preferably has a region containing silicon and oxygen on the surface of the conductor, and the thickness of the region is preferably 0.2 nm to 20 nm. The region can be a region containing a large amount of silicon and oxygen, in which case the region can function as an insulator. In addition, since the region functions as a barrier layer that suppresses intrusion of oxygen, the entire conductor can be prevented from being oxidized.
また、導電体１１４に、上記に示したような導電体を用いることによって、例えばトランジスタ１０を作製する過程において、熱処理によって導電体１１４が酸化性雰囲気に曝される場合に導電体１１４の全体が酸化されるのを抑制することができる。それにより、導電体の抵抗値が増加するのを抑制できるため、良好な電気特性（オン電流など）のトランジスタを作製することができる。 In addition, by using a conductor as described above for the conductor 114, for example, in the process of manufacturing the transistor 10, when the conductor 114 is exposed to an oxidizing atmosphere by heat treatment, the entire conductor 114 is made. Oxidation can be suppressed. Accordingly, an increase in the resistance value of the conductor can be suppressed, so that a transistor with favorable electrical characteristics (such as on-state current) can be manufactured.
＜半導体＞
以下、半導体１０６ｂの詳細な構成について説明する。 <Semiconductor>
Hereinafter, a detailed configuration of the semiconductor 106b will be described.
なお、半導体１０６ｂとともに絶縁体１０６ａ、絶縁体１０６ｃの詳細な構成についても説明する。 Note that the detailed structures of the insulator 106a and the insulator 106c as well as the semiconductor 106b are described.
半導体１０６ｂは、例えば、インジウムを含む酸化物半導体である。半導体１０６ｂは、例えば、インジウムを含むと、キャリア移動度（電子移動度）が高くなる。また、半導体１０６ｂは、元素Ｍを含むと好ましい。元素Ｍは、好ましくは、Ｔｉ、Ｇａ、Ｙ、Ｚｒ、Ｌａ、Ｃｅ、Ｎｄ、ＳｎまたはＨｆを表すとする。ただし、元素Ｍとして、前述の元素を複数組み合わせても構わない場合がある。元素Ｍは、例えば、酸素との結合エネルギーが高い元素である。例えば、酸素との結合エネルギーがインジウムよりも高い元素である。または、元素Ｍは、例えば、酸化物半導体のエネルギーギャップを大きくする機能を有する元素である。また、半導体１０６ｂは、亜鉛を含むと好ましい。酸化物半導体は、亜鉛を含むと結晶化しやすくなる場合がある。 The semiconductor 106b is an oxide semiconductor containing indium, for example. For example, when the semiconductor 106b contains indium, carrier mobility (electron mobility) increases. The semiconductor 106b preferably contains an element M. The element M preferably represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor 106b preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.
ただし、半導体１０６ｂは、インジウムを含む酸化物半導体に限定されない。半導体１０６ｂは、例えば、亜鉛スズ酸化物、ガリウムスズ酸化物などの、インジウムを含まず、亜鉛を含む酸化物半導体、ガリウムを含む酸化物半導体、スズを含む酸化物半導体などであっても構わない。 Note that the semiconductor 106b is not limited to the oxide semiconductor containing indium. The semiconductor 106b may be an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like that does not contain indium, such as zinc tin oxide and gallium tin oxide.
例えば、絶縁体１０６ａおよび絶縁体１０６ｃは、半導体１０６ｂを構成する酸素以外の元素一種以上、または二種以上から構成される酸化物半導体である。半導体１０６ｂを構成する酸素以外の元素一種以上、または二種以上から絶縁体１０６ａおよび絶縁体１０６ｃが構成されるため、絶縁体１０６ａと半導体１０６ｂとの界面、および半導体１０６ｂと絶縁体１０６ｃとの界面において、欠陥準位が形成されにくい。 For example, the insulator 106a and the insulator 106c are oxide semiconductors including one or more elements other than oxygen included in the semiconductor 106b, or two or more elements. Since the insulator 106a and the insulator 106c are composed of one or more elements other than oxygen constituting the semiconductor 106b, or two or more elements, the interface between the insulator 106a and the semiconductor 106b and the interface between the semiconductor 106b and the insulator 106c , Defect levels are difficult to form.
絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃは、少なくともインジウムを含むと好ましい。なお、絶縁体１０６ａがＩｎ−Ｍ−Ｚｎ酸化物のとき、ＩｎおよびＭの和を１００ａｔｏｍｉｃ％としたとき、好ましくはＩｎが５０ａｔｏｍｉｃ％未満、Ｍが５０ａｔｏｍｉｃ％より高く、さらに好ましくはＩｎが２５ａｔｏｍｉｃ％未満、Ｍが７５ａｔｏｍｉｃ％より高いとする。また、半導体１０６ｂがＩｎ−Ｍ−Ｚｎ酸化物のとき、ＩｎおよびＭの和を１００ａｔｏｍｉｃ％としたとき、好ましくはＩｎが２５ａｔｏｍｉｃ％より高く、Ｍが７５ａｔｏｍｉｃ％未満、さらに好ましくはＩｎが３４ａｔｏｍｉｃ％より高く、Ｍが６６ａｔｏｍｉｃ％未満とする。また、絶縁体１０６ｃがＩｎ−Ｍ−Ｚｎ酸化物のとき、ＩｎおよびＭの和を１００ａｔｏｍｉｃ％としたとき、好ましくはＩｎが５０ａｔｏｍｉｃ％未満、Ｍが５０ａｔｏｍｉｃ％より高く、さらに好ましくはＩｎが２５ａｔｏｍｉｃ％未満、Ｍが７５ａｔｏｍｉｃ％より高くする。なお、絶縁体１０６ｃは、絶縁体１０６ａと同種の酸化物を用いても構わない。ただし、絶縁体１０６ａまたは／および絶縁体１０６ｃがインジウムを含まなくても構わない場合がある。例えば、絶縁体１０６ａまたは／および絶縁体１０６ｃが酸化ガリウムであっても構わない。なお、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに含まれる各元素の原子数が、簡単な整数比にならなくても構わない。 The insulator 106a, the semiconductor 106b, and the insulator 106c preferably contain at least indium. Note that when the insulator 106a is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is 25 atomic%. And M is higher than 75 atomic%. In the case where the semiconductor 106b is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, the In is preferably higher than 25 atomic%, the M is less than 75 atomic%, and more preferably, In is more than 34 atomic%. High, and M is less than 66 atomic%. Further, when the insulator 106c is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is 25 atomic%. Less than, M is higher than 75 atomic%. Note that the insulator 106c may be formed using the same kind of oxide as the insulator 106a. Note that the insulator 106a and / or the insulator 106c may not contain indium in some cases. For example, the insulator 106a and / or the insulator 106c may be gallium oxide. Note that the number of atoms of each element included in the insulator 106a, the semiconductor 106b, and the insulator 106c may not be a simple integer ratio.
例えば、スパッタリング法を用いて成膜する場合、絶縁体１０６ａまたは絶縁体１０６ｃに用いるターゲットの金属元素の原子数比の代表例としては、Ｉｎ：Ｍ：Ｚｎ＝１：２：４、Ｉｎ：Ｍ：Ｚｎ＝１：３：２、Ｉｎ：Ｍ：Ｚｎ＝１：３：４、Ｉｎ：Ｍ：Ｚｎ＝１：３：６、Ｉｎ：Ｍ：Ｚｎ＝１：３：８、Ｉｎ：Ｍ：Ｚｎ＝１：４：３、Ｉｎ：Ｍ：Ｚｎ＝１：４：４、Ｉｎ：Ｍ：Ｚｎ＝１：４：５、Ｉｎ：Ｍ：Ｚｎ＝１：４：６、Ｉｎ：Ｍ：Ｚｎ＝１：６：３、Ｉｎ：Ｍ：Ｚｎ＝１：６：４、Ｉｎ：Ｍ：Ｚｎ＝１：６：５、Ｉｎ：Ｍ：Ｚｎ＝１：６：６、Ｉｎ：Ｍ：Ｚｎ＝１：６：７、Ｉｎ：Ｍ：Ｚｎ＝１：６：８、Ｉｎ：Ｍ：Ｚｎ＝１：６：９等がある。 For example, in the case where a film is formed by a sputtering method, typical examples of the atomic ratio of a metal element of a target used for the insulator 106a or the insulator 106c include In: M: Zn = 1: 2: 4, In: M : Zn = 1: 3: 2, In: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 6, In: M: Zn = 1: 3: 8, In: M: Zn = 1: 4: 3, In: M: Zn = 1: 4: 4, In: M: Zn = 1: 4: 5, In: M: Zn = 1: 4: 6, In: M: Zn = 1 : 6: 3, In: M: Zn = 1: 6: 4, In: M: Zn = 1: 6: 5, In: M: Zn = 1: 6: 6, In: M: Zn = 1: 6 : 7, In: M: Zn = 1: 6: 8, In: M: Zn = 1: 6: 9, and the like.
また、例えば、スパッタリング法を用いて成膜する場合、半導体１０６ｂに用いるターゲットの金属元素の原子数比の代表例としては、Ｉｎ：Ｍ：Ｚｎ＝１：１：１、Ｉｎ：Ｍ：Ｚｎ＝１：１：１．２、Ｉｎ：Ｍ：Ｚｎ＝２：１：１．５、Ｉｎ：Ｍ：Ｚｎ＝２：１：２．３、Ｉｎ：Ｍ：Ｚｎ＝２：１：３、Ｉｎ：Ｍ：Ｚｎ＝３：１：２、Ｉｎ：Ｍ：Ｚｎ＝４：２：４．１、Ｉｎ：Ｍ：Ｚｎ＝５：１：７等がある。特に、スパッタリングターゲットとして、原子数比がＩｎ：Ｇａ：Ｚｎ＝４：２：４．１を用いる場合、成膜される半導体１０６ｂの原子数比は、Ｉｎ：Ｇａ：Ｚｎ＝４：２：３近傍となる場合がある。 For example, when a film is formed by a sputtering method, typical examples of the atomic ratio of the metal element of the target used for the semiconductor 106b are In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1.5, In: M: Zn = 2: 1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 7, and the like. In particular, when an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as a sputtering target, the atomic ratio of the semiconductor 106b to be formed is In: Ga: Zn = 4: 2: 3. May be near.
なお、インジウムガリウム酸化物は、小さい電子親和力と、高い酸素ブロック性を有する。そのため、絶縁体１０６ｃがインジウムガリウム酸化物を含むと好ましい。ガリウム原子割合［Ｇａ／（Ｉｎ＋Ｇａ）］は、例えば、７０％以上、好ましくは８０％以上、さらに好ましくは９０％以上とする。 Note that indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the insulator 106c preferably contains indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.
半導体１０６ｂは、例えば、エネルギーギャップが大きい酸化物を用いる。半導体１０６ｂのエネルギーギャップは、例えば、２．５ｅＶ以上４．２ｅＶ以下、好ましくは２．８ｅＶ以上３．８ｅＶ以下、さらに好ましくは３ｅＶ以上３．５ｅＶ以下とする。ここで、絶縁体１０６ａのエネルギーギャップは、半導体１０６ｂのエネルギーギャップより大きい。また、絶縁体１０６ｃのエネルギーギャップは、半導体１０６ｂのエネルギーギャップより大きい。 For the semiconductor 106b, an oxide with a wide energy gap is used, for example. The energy gap of the semiconductor 106b is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV. Here, the energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b. In addition, the energy gap of the insulator 106c is larger than the energy gap of the semiconductor 106b.
半導体１０６ｂは、絶縁体１０６ａまたは絶縁体１０６ｃよりも電子親和力の大きい酸化物を用いる。例えば、半導体１０６ｂとして、絶縁体１０６ａおよび絶縁体１０６ｃよりも電子親和力の０．０７ｅＶ以上１．３ｅＶ以下、好ましくは０．１ｅＶ以上０．７ｅＶ以下、さらに好ましくは０．１５ｅＶ以上０．４ｅＶ以下大きい酸化物を用いる。なお、電子親和力は、真空準位と伝導帯下端のエネルギーとの差である。言い換えると、絶縁体１０６ａまたは絶縁体１０６ｃの伝導帯下端のエネルギー準位は、半導体１０６ｂの伝導帯下端のエネルギー準位より真空準位に近い。 As the semiconductor 106b, an oxide having an electron affinity higher than that of the insulator 106a or the insulator 106c is used. For example, the semiconductor 106b has an electron affinity of 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.15 eV to 0.4 eV, compared to the insulator 106a and the insulator 106c. An oxide is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band. In other words, the energy level at the lower end of the conduction band of the insulator 106a or the insulator 106c is closer to the vacuum level than the energy level at the lower end of the conduction band of the semiconductor 106b.
このとき、ゲート電圧を印加すると、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃのうち、電子親和力の大きい半導体１０６ｂにチャネルが形成される。なお、高いゲート電圧を印加すると、絶縁体１０６ａの半導体１０６ｂとの界面近傍、および絶縁体１０６ｃの半導体１０６ｂとの界面近傍においても電流が流れる場合がある。 At this time, when a gate voltage is applied, a channel is formed in the semiconductor 106b having a high electron affinity among the insulator 106a, the semiconductor 106b, and the insulator 106c. Note that when a high gate voltage is applied, current may flow also in the vicinity of the interface between the insulator 106a and the semiconductor 106b and in the vicinity of the interface between the insulator 106c and the semiconductor 106b.
上記の通り、絶縁体１０６ａおよび絶縁体１０６ｃは、単独で用いる場合、導電体、半導体または絶縁体として機能させることができる物質からなる。しかしながら、半導体１０６ｂと積層させてトランジスタを形成する場合、電子は半導体１０６ｂ、半導体１０６ｂと絶縁体１０６ａの界面近傍、および半導体１０６ｂと絶縁体１０６ｃの界面近傍を流れ、絶縁体１０６ａおよび絶縁体１０６ｃは当該トランジスタのチャネルとして機能しない領域を有する。このため、本明細書などにおいては、絶縁体１０６ａおよび絶縁体１０６ｃを半導体と記載せず、絶縁体と記載するものとする。なお、絶縁体１０６ａおよび絶縁体１０６ｃを絶縁体と記載するのは、あくまで半導体１０６ｂと比較してトランジスタの機能上絶縁体に近い機能を有するためなので、絶縁体１０６ａまたは絶縁体１０６ｃとして、半導体１０６ｂに用いることができる物質を用いる場合もある。 As described above, the insulator 106a and the insulator 106c are made of a substance that can function as a conductor, a semiconductor, or an insulator when used alone. However, when a transistor is formed by stacking with the semiconductor 106b, electrons flow in the vicinity of the semiconductor 106b, the interface between the semiconductor 106b and the insulator 106a, and the vicinity of the interface between the semiconductor 106b and the insulator 106c, and the insulator 106a and the insulator 106c The transistor does not function as a channel of the transistor. Therefore, in this specification and the like, the insulator 106a and the insulator 106c are not described as semiconductors but are described as insulators. Note that the insulator 106a and the insulator 106c are described as insulators because they have a function similar to that of an insulator compared to the semiconductor 106b. Therefore, the insulator 106a or the insulator 106c is referred to as the semiconductor 106b. In some cases, a substance that can be used in the process is used.
ここで、絶縁体１０６ａと半導体１０６ｂとの間には、絶縁体１０６ａと半導体１０６ｂとの混合領域を有する場合がある。また、半導体１０６ｂと絶縁体１０６ｃとの間には、半導体１０６ｂと絶縁体１０６ｃとの混合領域を有する場合がある。混合領域は、欠陥準位密度が低くなる。そのため、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃの積層体は、それぞれの界面近傍において、エネルギーが連続的に変化する（連続接合ともいう。）バンド図となる。なお、絶縁体１０６ａと半導体１０６ｂ、または絶縁体１０６ｃと半導体１０６ｂは、それぞれの界面を明確に判別できない場合がある。 Here, in some cases, there is a mixed region of the insulator 106a and the semiconductor 106b between the insulator 106a and the semiconductor 106b. Further, in some cases, there is a mixed region of the semiconductor 106b and the insulator 106c between the semiconductor 106b and the insulator 106c. The mixed region has a low density of defect states. Therefore, the stacked body of the insulator 106a, the semiconductor 106b, and the insulator 106c has a band diagram in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface. Note that the interface between the insulator 106a and the semiconductor 106b or between the insulator 106c and the semiconductor 106b may not be clearly distinguished.
このとき、電子は、絶縁体１０６ａ中および絶縁体１０６ｃ中ではなく、半導体１０６ｂ中を主として移動する。上述したように、絶縁体１０６ａと半導体１０６ｂとの界面における欠陥準位密度、および半導体１０６ｂと絶縁体１０６ｃとの界面における欠陥準位密度を低くすることによって、半導体１０６ｂ中で電子の移動が阻害されることが少なく、トランジスタのオン電流を高くすることができる。 At this time, electrons move mainly in the semiconductor 106b, not in the insulator 106a and the insulator 106c. As described above, by reducing the defect level density at the interface between the insulator 106a and the semiconductor 106b and the defect level density at the interface between the semiconductor 106b and the insulator 106c, movement of electrons in the semiconductor 106b is inhibited. The on-state current of the transistor can be increased.
また、トランジスタのオン電流は、電子の移動を阻害する要因を低減するほど、高くすることができる。例えば、電子の移動を阻害する要因のない場合、効率よく電子が移動すると推定される。電子の移動は、例えば、チャネル形成領域の物理的な凹凸が大きい場合にも阻害される。 Further, the on-state current of the transistor can be increased as the factor that hinders the movement of electrons is reduced. For example, when there is no factor that hinders the movement of electrons, it is estimated that electrons move efficiently. Electron movement is inhibited, for example, even when the physical unevenness of the channel formation region is large.
トランジスタのオン電流を高くするためには、例えば、半導体１０６ｂの上面または下面（被形成面、ここでは絶縁体１０６ａの上面）の、１μｍ×１μｍの範囲における二乗平均平方根（ＲＭＳ：Ｒｏｏｔ　Ｍｅａｎ　Ｓｑｕａｒｅ）粗さが１ｎｍ未満、好ましくは０．６ｎｍ未満、さらに好ましくは０．５ｎｍ未満、より好ましくは０．４ｎｍ未満とすればよい。また、１μｍ×１μｍの範囲における平均面粗さ（Ｒａともいう。）が１ｎｍ未満、好ましくは０．６ｎｍ未満、さらに好ましくは０．５ｎｍ未満、より好ましくは０．４ｎｍ未満とすればよい。また、１μｍ×１μｍの範囲における最大高低差（Ｐ−Ｖともいう。）が１０ｎｍ未満、好ましくは９ｎｍ未満、さらに好ましくは８ｎｍ未満、より好ましくは７ｎｍ未満とすればよい。ＲＭＳ粗さ、ＲａおよびＰ−Ｖは、エスアイアイ・ナノテクノロジー株式会社製走査型プローブ顕微鏡システムＳＰＡ−５００などを用いて測定することができる。 In order to increase the on-state current of the transistor, for example, the root mean square (RMS) of the upper surface or the lower surface of the semiconductor 106b (formation surface, here, the upper surface of the insulator 106a) in the range of 1 μm × 1 μm (RMS: Root Mean Square) The roughness may be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, more preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. The maximum height difference (also referred to as PV) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and more preferably less than 7 nm. The RMS roughness, Ra, and PV can be measured using a scanning probe microscope system SPA-500 manufactured by SII Nano Technology.
また、トランジスタのオン電流を高くするためには、絶縁体１０６ｃの厚さは小さいほど好ましい。絶縁体１０６ｃの厚さは、絶縁体１０６ａの厚さの厚さより小さく、半導体１０６ｂの厚さより小さいことが好ましい。例えば、１０ｎｍ未満、好ましくは５ｎｍ以下、さらに好ましくは３ｎｍ以下の領域を有する絶縁体１０６ｃとすればよい。一方、絶縁体１０６ｃは、チャネルの形成される半導体１０６ｂへ、隣接する絶縁体を構成する酸素以外の元素（水素、シリコンなど）が入り込まないようブロックする機能を有する。そのため、絶縁体１０６ｃは、ある程度の厚さを有することが好ましい。例えば、０．３ｎｍ以上、好ましくは１ｎｍ以上、さらに好ましくは２ｎｍ以上の厚さの領域を有する絶縁体１０６ｃとすればよい。 In order to increase the on-state current of the transistor, the thickness of the insulator 106c is preferably as small as possible. The thickness of the insulator 106c is preferably smaller than the thickness of the insulator 106a and smaller than the thickness of the semiconductor 106b. For example, the insulator 106c having a region of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less may be used. On the other hand, the insulator 106c has a function of blocking elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator from entering the semiconductor 106b in which a channel is formed. Therefore, the insulator 106c preferably has a certain thickness. For example, the insulator 106c having a region with a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more may be used.
また、信頼性を高くするためには、絶縁体１０６ａは厚いことが好ましい。例えば、１０ｎｍ以上、好ましくは２０ｎｍ以上、さらに好ましくは４０ｎｍ以上、より好ましくは６０ｎｍ以上の厚さの領域を有する絶縁体１０６ａとすればよい。絶縁体１０６ａの厚さを、厚くすることで、隣接する絶縁体と絶縁体１０６ａとの界面からチャネルの形成される半導体１０６ｂまでの距離を離すことができる。ただし、半導体装置の生産性が低下する場合があるため、例えば、２００ｎｍ以下、好ましくは１２０ｎｍ以下、さらに好ましくは８０ｎｍ以下の厚さの領域を有する絶縁体１０６ａとすればよい。 In order to increase reliability, the insulator 106a is preferably thick. For example, the insulator 106a may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more. By increasing the thickness of the insulator 106a, the distance from the interface between the adjacent insulator 106a to the semiconductor 106b where a channel is formed can be increased. However, since the productivity of the semiconductor device may be reduced, the insulator 106a having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less may be used.
酸化物半導体中のシリコンは、キャリアトラップやキャリア発生源となる場合がある。したがって、半導体１０６ｂのシリコン濃度は低いほど好ましい。例えば、半導体１０６ｂと絶縁体１０６ａとの間に、例えば、二次イオン質量分析法（ＳＩＭＳ：Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）において、１×１０１６ａｔｏｍｓ／ｃｍ３以上１×１０１９ａｔｏｍｓ／ｃｍ３以下、好ましくは１×１０１６ａｔｏｍｓ／ｃｍ３以上５×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは１×１０１６ａｔｏｍｓ／ｃｍ３以上２×１０１８ａｔｏｍｓ／ｃｍ３以下のシリコン濃度となる領域を有する。また、半導体１０６ｂと絶縁体１０６ｃとの間に、ＳＩＭＳにおいて、１×１０１６ａｔｏｍｓ／ｃｍ３以上１×１０１９ａｔｏｍｓ／ｃｍ３以下、好ましくは１×１０１６ａｔｏｍｓ／ｃｍ３以上５×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは１×１０１６ａｔｏｍｓ／ｃｍ３以上２×１０１８ａｔｏｍｓ／ｃｍ３以下のシリコン濃度となる領域を有する。 Silicon in the oxide semiconductor may serve as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 106b, the better. For example, between the semiconductor 106b and the insulator 106a, for example, in secondary ion mass spectrometry (SIMS), 1 × 10 16 atoms / cm 3 or more and 1 × 10 19 atoms / cm 3 or less, Preferably, it has a region having a silicon concentration of 1 × 10 16 atoms / cm 3 or more and 5 × 10 18 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 or more and 2 × 10 18 atoms / cm 3 or less. . Further, between SIMS 106b and the insulator 106c, in SIMS, 1 × 10 16 atoms / cm 3 or more and 1 × 10 19 atoms / cm 3 or less, preferably 1 × 10 16 atoms / cm 3 or more and 5 × 10 18 The region has a silicon concentration of atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 or more and 2 × 10 18 atoms / cm 3 or less.
また、半導体１０６ｂの水素濃度を低減するために、絶縁体１０６ａおよび絶縁体１０６ｃの水素濃度を低減すると好ましい。絶縁体１０６ａおよび絶縁体１０６ｃは、ＳＩＭＳにおいて、１×１０１６ａｔｏｍｓ／ｃｍ３以上２×１０２０ａｔｏｍｓ／ｃｍ３以下、好ましくは１×１０１６ａｔｏｍｓ／ｃｍ３以上５×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１６ａｔｏｍｓ／ｃｍ３以上１×１０１９ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは１×１０１６ａｔｏｍｓ／ｃｍ３以上５×１０１８ａｔｏｍｓ／ｃｍ３以下の水素濃度となる領域を有する。また、半導体１０６ｂの窒素濃度を低減するために、絶縁体１０６ａおよび絶縁体１０６ｃの窒素濃度を低減すると好ましい。絶縁体１０６ａおよび絶縁体１０６ｃは、ＳＩＭＳにおいて、１×１０１５ａｔｏｍｓ／ｃｍ３以上５×１０１９ａｔｏｍｓ／ｃｍ３以下、好ましくは１×１０１５ａｔｏｍｓ／ｃｍ３以上５×１０１８ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１５ａｔｏｍｓ／ｃｍ３以上１×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは１×１０１５ａｔｏｍｓ／ｃｍ３以上５×１０１７ａｔｏｍｓ／ｃｍ３以下の窒素濃度となる領域を有する。 In addition, in order to reduce the hydrogen concentration of the semiconductor 106b, it is preferable to reduce the hydrogen concentration of the insulator 106a and the insulator 106c. In the SIMS, the insulator 106a and the insulator 106c are 1 × 10 16 atoms / cm 3 or more and 2 × 10 20 atoms / cm 3 or less, preferably 1 × 10 16 atoms / cm 3 or more and 5 × 10 19 atoms / cm 3 in SIMS. Hereinafter, the hydrogen concentration is more preferably 1 × 10 16 atoms / cm 3 or more and 1 × 10 19 atoms / cm 3 or less, and further preferably 1 × 10 16 atoms / cm 3 or more and 5 × 10 18 atoms / cm 3 or less. Has a region. In addition, in order to reduce the nitrogen concentration of the semiconductor 106b, it is preferable to reduce the nitrogen concentrations of the insulator 106a and the insulator 106c. In the SIMS, the insulator 106a and the insulator 106c are 1 × 10 15 atoms / cm 3 or more and 5 × 10 19 atoms / cm 3 or less, preferably 1 × 10 15 atoms / cm 3 or more and 5 × 10 18 atoms / cm 3. Or less, more preferably 1 × 10 15 atoms / cm 3 or more and 1 × 10 18 atoms / cm 3 or less, and even more preferably 1 × 10 15 atoms / cm 3 or more and 5 × 10 17 atoms / cm 3 or less. Has a region.
本実施の形態に示す絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃ、特に半導体１０６ｂは、不純物濃度が低く、欠陥準位密度の低い（酸素欠損の少ない）酸化物半導体であり、高純度真性または実質的に高純度真性な酸化物半導体と呼ぶことができる。高純度真性または実質的に高純度真性である酸化物半導体は、キャリア発生源が少ないため、キャリア密度を低くすることができる。従って、該酸化物半導体にチャネル領域が形成されるトランジスタは、しきい値電圧がマイナスとなる電気特性（ノーマリーオンともいう。）になることが少ない。また、高純度真性または実質的に高純度真性である酸化物半導体は、欠陥準位密度が低いため、トラップ準位密度も低くなる場合がある。また、高純度真性または実質的に高純度真性である酸化物半導体は、オフ電流が著しく小さく、チャネル幅Ｗが１×１０６μｍでチャネル長Ｌが１０μｍの素子であっても、ソース電極とドレイン電極間の電圧（ドレイン電圧）が１Ｖから１０Ｖの範囲において、オフ電流が、半導体パラメータアナライザの測定限界以下、すなわち１×１０−１３Ａ以下という特性を得ることができる。 The insulator 106a, the semiconductor 106b, and the insulator 106c, particularly the semiconductor 106b described in this embodiment are oxide semiconductors with a low impurity concentration and a low density of defect states (the number of oxygen vacancies) is low. In particular, it can be called a highly pure intrinsic oxide semiconductor. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states, and thus may have a low density of trap states. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has an extremely small off-state current, an element having a channel width W of 1 × 10 6 μm and a channel length L of 10 μm. When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, it is possible to obtain a characteristic that the off-current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 −13 A or less.
したがって、上記高純度真性、または実質的に高純度真性の酸化物半導体にチャネル領域が形成されるトランジスタは、電気特性の変動が小さく、信頼性の高いトランジスタとすることができる。なお、酸化物半導体のトラップ準位に捕獲された電荷は、消失するまでに要する時間が長く、あたかも固定電荷のように振る舞うことがある。そのため、トラップ準位密度の高い酸化物半導体にチャネル領域が形成されるトランジスタは、電気特性が不安定となる場合がある。不純物としては、水素、窒素、アルカリ金属、またはアルカリ土類金属等がある。 Therefore, a transistor in which a channel region is formed in the above-described high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor can be a highly reliable transistor with little variation in electrical characteristics. Note that the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics. Examples of impurities include hydrogen, nitrogen, alkali metals, and alkaline earth metals.
絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに含まれる水素は、金属原子と結合する酸素と反応して水になると共に、酸素が脱離した格子（または酸素が脱離した部分）に酸素欠損を形成する。該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。また、水素の一部が金属原子と結合する酸素と結合して、キャリアである電子を生成することがある。特に酸素欠損にトラップされた水素は、半導体のバンド構造に対して浅いドナー準位を形成することがある。従って、水素が含まれている酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃは水素ができる限り低減されていることが好ましい。具体的には、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃにおいて、ＳＩＭＳにより得られる水素濃度を、２×１０２０ａｔｏｍｓ／ｃｍ３以下、好ましくは５×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３以下、５×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下、より好ましくは５×１０１７ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは１×１０１６ａｔｏｍｓ／ｃｍ３以下とする。 Hydrogen contained in the insulator 106a, the semiconductor 106b, and the insulator 106c reacts with oxygen bonded to a metal atom to be water, and oxygen vacancies are generated in a lattice from which oxygen is released (or a portion from which oxygen is released). Form. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. In particular, hydrogen trapped in oxygen vacancies may form a shallow donor level with respect to a semiconductor band structure. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. Therefore, the insulator 106a, the semiconductor 106b, and the insulator 106c are preferably reduced as much as possible. Specifically, in the insulator 106a, the semiconductor 106b, and the insulator 106c, the hydrogen concentration obtained by SIMS is 2 × 10 20 atoms / cm 3 or less, preferably 5 × 10 19 atoms / cm 3 or less, more preferably 1 × 10 19 atoms / cm 3 or less, 5 × 10 18 atoms / cm 3 or less, preferably 1 × 10 18 atoms / cm 3 or less, more preferably 5 × 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 or less.
絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃにおいて、第１４族元素の一つであるシリコンや炭素が含まれると、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃにおいて酸素欠損が増加し、ｎ型化してしまう。このため、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃにおけるシリコンや炭素の濃度と、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃとの界面近傍のシリコンや炭素の濃度（ＳＩＭＳにより得られる濃度）を、２×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１７ａｔｏｍｓ／ｃｍ３以下とする。 In the insulator 106a, the semiconductor 106b, and the insulator 106c, when silicon or carbon which is one of Group 14 elements is included, oxygen vacancies increase in the insulator 106a, the semiconductor 106b, and the insulator 106c, and become n-type. End up. Therefore, the silicon and carbon concentrations in the insulator 106a, the semiconductor 106b, and the insulator 106c, and the silicon and carbon concentrations (concentration obtained by SIMS) in the vicinity of the interface between the insulator 106a, the semiconductor 106b, and the insulator 106c, 2 × 10 18 atoms / cm 3 or less, preferably 2 × 10 17 atoms / cm 3 or less.
また、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃにおいて、ＳＩＭＳにより得られるアルカリ金属またはアルカリ土類金属の濃度を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にする。アルカリ金属およびアルカリ土類金属は、酸化物半導体と結合するとキャリアを生成する場合があり、トランジスタのオフ電流が増大してしまうことがある。このため、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃのアルカリ金属またはアルカリ土類金属の濃度を低減することが好ましい。 In the insulator 106a, the semiconductor 106b, and the insulator 106c, the concentration of alkali metal or alkaline earth metal obtained by SIMS is 1 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 atoms / cm 3 or less. To. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the insulator 106a, the semiconductor 106b, and the insulator 106c.
また、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに窒素が含まれていると、キャリアである電子が生じ、キャリア密度が増加し、ｎ型化しやすい。この結果、窒素が含まれている酸化物半導体膜を用いたトランジスタはノーマリーオン特性となりやすい。従って、該酸化物半導体膜において、窒素はできる限り低減されていることが好ましい、例えば、ＳＩＭＳにより得られる窒素濃度は、５×１０１８ａｔｏｍｓ／ｃｍ３以下にすることが好ましい。 In addition, when the insulator 106a, the semiconductor 106b, and the insulator 106c contain nitrogen, electrons serving as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to be normally on. Therefore, nitrogen in the oxide semiconductor film is preferably reduced as much as possible. For example, the nitrogen concentration obtained by SIMS is preferably 5 × 10 18 atoms / cm 3 or less.
上述の通り、本実施の形態に示す絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃは、不純物濃度が低く、欠陥準位密度の小さい（酸素欠損の少ない）酸化物であり、キャリア密度が小さい。そのため、ソース電極またはドレイン電極として機能する導電体１０８ａおよび導電体１０８ｂとの間で接触抵抗が大きくなりやすい。そこで、本実施の形態に示すトランジスタ１０では、導電体１０８ａまたは導電体１０８ｂと、絶縁体１０６ａ、半導体１０６ｂまたは絶縁体１０６ｃと、が、抵抗値が低い領域１２６ｂまたは領域１２６ｃにおいて接続されることにより、接触抵抗が増大するのを抑制できる。 As described above, the insulator 106a, the semiconductor 106b, and the insulator 106c described in this embodiment are oxides with low impurity concentration, low density of defect states (low oxygen vacancies), and low carrier density. Therefore, contact resistance tends to increase between the conductor 108a and the conductor 108b functioning as a source electrode or a drain electrode. Thus, in the transistor 10 described in this embodiment, the conductor 108a or the conductor 108b and the insulator 106a, the semiconductor 106b, or the insulator 106c are connected to each other in the region 126b or the region 126c having a low resistance value. The contact resistance can be prevented from increasing.
また、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃには、領域１２６ａ、領域１２６ｂおよび領域１２６ｃが形成されており、領域１２６ｂおよび領域１２６ｃは領域１２６ａと比較してドーパントの濃度が高く、低抵抗化されている。ここで、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃにおいて、領域１２６ａは導電体１１４と概ね重なる領域であり、領域１２６ｂおよび領域１２６ｃは、領域１２６ａを除いた領域である。ただし、領域１２６ｂおよび領域１２６ｃの一部が、半導体１０６ｂの導電体１１４と重なる領域（チャネル形成領域）の一部と重なることが好ましい。 The insulator 106a, the semiconductor 106b, and the insulator 106c are formed with a region 126a, a region 126b, and a region 126c. The region 126b and the region 126c have higher dopant concentration and lower resistance than the region 126a. Has been. Here, in the insulator 106a, the semiconductor 106b, and the insulator 106c, the region 126a is a region that substantially overlaps the conductor 114, and the region 126b and the region 126c are regions other than the region 126a. However, it is preferable that part of the region 126b and the region 126c overlap with part of a region (channel formation region) that overlaps with the conductor 114 of the semiconductor 106b.
さらに、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃの絶縁体１１６との界面近傍には、低抵抗領域１０７ａおよび低抵抗領域１０７ｂが形成されることが好ましい。領域１２６ｂ、領域１２６ｃ、低抵抗領域１０７ａおよび低抵抗領域１０７ｂでは、ドーパントや絶縁体１１６に含まれる元素が絶縁体１０６ａ、半導体１０６ｂまたは絶縁体１０６ｃに添加され、当該元素によって欠陥が形成される。このような欠陥は、例えば、添加されたドーパントや絶縁体１１６から添加された元素によって、酸素が引き抜かれて酸素欠損が形成される、またはドーパントや絶縁体１１６から添加された元素自体がキャリア発生源となることによって形成される。このような欠陥ではドナー準位が形成され、キャリア密度が増加するため、ドーパントや絶縁体１１６に含まれる元素が添加された領域が、領域１２６ｂ、領域１２６ｃ、低抵抗領域１０７ａおよび低抵抗領域１０７ｂとして機能することになる。 Further, it is preferable that a low resistance region 107a and a low resistance region 107b be formed in the vicinity of the interface of the insulator 106a, the semiconductor 106b, and the insulator 106c with the insulator 116. In the region 126b, the region 126c, the low resistance region 107a, and the low resistance region 107b, a dopant or an element contained in the insulator 116 is added to the insulator 106a, the semiconductor 106b, or the insulator 106c, and a defect is formed by the element. Such a defect is caused by, for example, oxygen being extracted by an added dopant or an element added from the insulator 116 to form an oxygen vacancy, or an element added from the dopant or the insulator 116 itself is a carrier. Formed by becoming a source. In such a defect, a donor level is formed and the carrier density is increased. Therefore, regions to which a dopant or an element included in the insulator 116 is added are regions 126b, a region 126c, a low-resistance region 107a, and a low-resistance region 107b. Will function as.
領域１２６ｂ、領域１２６ｃ、特に低抵抗領域１０７ａおよび低抵抗領域１０７ｂは、酸素欠損が多く形成されている。また、領域１２６ｂ、領域１２６ｃ、特に低抵抗領域１０７ａおよび低抵抗領域１０７ｂは、欠陥が多く形成されているため、領域１２６ａよりも結晶性が低くなっている。 The region 126b and the region 126c, in particular, the low resistance region 107a and the low resistance region 107b are formed with many oxygen vacancies. In addition, the region 126b, the region 126c, in particular, the low resistance region 107a and the low resistance region 107b are formed with many defects, and thus have lower crystallinity than the region 126a.
また、領域１２６ｂおよび領域１２６ｃはドーパントを添加して形成される。そのため、領域１２６ｂおよび領域１２６ｃは、領域１２６ａよりＳＩＭＳ分析により得られる当該ドーパントの濃度が高くなる。 The regions 126b and 126c are formed by adding a dopant. Therefore, the concentration of the dopant obtained by SIMS analysis in the region 126b and the region 126c is higher than that in the region 126a.
領域１２６ｂおよび領域１２６ｃに添加されるドーパントとしては、例えば、水素、ヘリウム、ネオン、アルゴン、クリプトン、キセノン、窒素、フッ素、リン、塩素、ヒ素、ホウ素、マグネシウム、アルミニウム、シリコン、チタン、バナジウム、クロム、ニッケル、亜鉛、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ニオブ、モリブデン、インジウム、スズ、ランタン、セリウム、ネオジム、ハフニウム、タンタルまたはタングステンなどが挙げられる。これらの元素の中でも、リン、ホウ素、窒素、アルゴンまたはキセノンのいずれか一以上を添加すると好ましい。また、該添加は、イオン注入またはイオンドーピングなどを用いるとよい。 Examples of the dopant added to the region 126b and the region 126c include hydrogen, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, boron, magnesium, aluminum, silicon, titanium, vanadium, and chromium. Nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum or tungsten. Among these elements, it is preferable to add one or more of phosphorus, boron, nitrogen, argon, or xenon. For the addition, ion implantation or ion doping may be used.
なお、上述の絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃの３層構造は一例である。例えば、絶縁体１０６ａまたは絶縁体１０６ｃのいずれか一方を設けない２層構造としてもよい。また、絶縁体１０６ａまたは絶縁体１０６ｃの両方を設けない単層構造としてもよい。または、絶縁体１０６ａ、半導体１０６ｂまたは絶縁体１０６ｃとして例示した絶縁体、半導体または導電体のいずれかを有するｎ層構造（ｎは４以上の整数）としても構わない。 Note that the above-described three-layer structure of the insulator 106a, the semiconductor 106b, and the insulator 106c is an example. For example, a two-layer structure in which either the insulator 106a or the insulator 106c is not provided may be employed. Alternatively, a single-layer structure in which both the insulator 106a and the insulator 106c are not provided may be employed. Alternatively, an n-layer structure (n is an integer of 4 or more) including any of the insulators, semiconductors, and conductors exemplified as the insulator 106a, the semiconductor 106b, and the insulator 106c may be used.
＜酸化物半導体の構造＞
以下では、酸化物半導体の構造について説明する。 <Structure of oxide semiconductor>
Hereinafter, the structure of the oxide semiconductor is described.
酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、ＣＡＡＣ−ＯＳ（ｃ−ａｘｉｓ−ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、多結晶酸化物半導体、ｎｃ−ＯＳ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、擬似非晶質酸化物半導体（ａ−ｌｉｋｅ　ＯＳ：ａｍｏｒｐｈｏｕｓ−ｌｉｋｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）および非晶質酸化物半導体などがある。 An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide OS) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
また別の観点では、酸化物半導体は、非晶質酸化物半導体と、それ以外の結晶性酸化物半導体と、に分けられる。結晶性酸化物半導体としては、単結晶酸化物半導体、ＣＡＡＣ−ＯＳ、多結晶酸化物半導体およびｎｃ−ＯＳなどがある。 From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
非晶質構造は、一般に、等方的であって不均質構造を持たない、準安定状態で原子の配置が固定化していない、結合角度が柔軟である、短距離秩序は有するが長距離秩序を有さない、などといわれている。 Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.
即ち、安定な酸化物半導体を完全な非晶質（ｃｏｍｐｌｅｔｅｌｙ　ａｍｏｒｐｈｏｕｓ）酸化物半導体とは呼べない。また、等方的でない（例えば、微小な領域において周期構造を有する）酸化物半導体を、完全な非晶質酸化物半導体とは呼べない。一方、ａ−ｌｉｋｅ　ＯＳは、等方的でないが、鬆（ボイドともいう。）を有する不安定な構造である。不安定であるという点では、ａ−ｌｉｋｅ　ＯＳは、物性的に非晶質酸化物半導体に近い。 That is, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically similar to an amorphous oxide semiconductor.
＜ＣＡＡＣ−ＯＳ＞
まずは、ＣＡＡＣ−ＯＳについて説明する。 <CAAC-OS>
First, the CAAC-OS will be described.
ＣＡＡＣ−ＯＳは、ｃ軸配向した複数の結晶部（ペレットともいう。）を有する酸化物半導体の一種である。 A CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).
ＣＡＡＣ−ＯＳをＸ線回折（ＸＲＤ：Ｘ−Ｒａｙ　Ｄｉｆｆｒａｃｔｉｏｎ）によって解析した場合について説明する。例えば、空間群Ｒ−３ｍに分類されるＩｎＧａＺｎＯ４の結晶を有するＣＡＡＣ−ＯＳに対し、ｏｕｔ−ｏｆ−ｐｌａｎｅ法による構造解析を行うと、図２（Ａ）に示すように回折角（２θ）が３１°近傍にピークが現れる。このピークは、ＩｎＧａＺｎＯ４の結晶の（００９）面に帰属されることから、ＣＡＡＣ−ＯＳでは、結晶がｃ軸配向性を有し、ｃ軸がＣＡＡＣ−ＯＳの膜を形成する面（被形成面ともいう。）、または上面に略垂直な方向を向いていることが確認できる。なお、２θが３１°近傍のピークの他に、２θが３６°近傍にもピークが現れる場合がある。２θが３６°近傍のピークは、空間群Ｆｄ−３ｍに分類される結晶構造に起因する。そのため、ＣＡＡＣ−ＯＳは、該ピークを示さないことが好ましい。 A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS having an InGaZnO 4 crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO 4 crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.
一方、ＣＡＡＣ−ＯＳに対し、被形成面に平行な方向からＸ線を入射させるｉｎ−ｐｌａｎｅ法による構造解析を行うと、２θが５６°近傍にピークが現れる。このピークは、ＩｎＧａＺｎＯ４の結晶の（１１０）面に帰属される。そして、２θを５６°近傍に固定し、試料面の法線ベクトルを軸（φ軸）として試料を回転させながら分析（φスキャン）を行っても、図２（Ｂ）に示すように明瞭なピークは現れない。一方、単結晶ＩｎＧａＺｎＯ４に対し、２θを５６°近傍に固定してφスキャンした場合、図２（Ｃ）に示すように（１１０）面と等価な結晶面に帰属されるピークが６本観察される。したがって、ＸＲＤを用いた構造解析から、ＣＡＡＣ−ＯＳは、ａ軸およびｂ軸の配向が不規則であることが確認できる。 On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO 4 crystal. Further, even when analysis (φ scan) is performed while rotating the sample with 2θ fixed at around 56 ° and the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when single-crystal InGaZnO 4 is φ-scanned with 2θ fixed at around 56 °, six peaks attributed to the crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.
次に、電子回折によって解析したＣＡＡＣ−ＯＳについて説明する。例えば、ＩｎＧａＺｎＯ４の結晶を有するＣＡＡＣ−ＯＳに対し、ＣＡＡＣ−ＯＳの被形成面に平行にプローブ径が３００ｎｍの電子線を入射させると、図２（Ｄ）に示すような回折パターン（制限視野電子回折パターンともいう。）が現れる場合がある。この回折パターンには、ＩｎＧａＺｎＯ４の結晶の（００９）面に起因するスポットが含まれる。したがって、電子回折によっても、ＣＡＡＣ−ＯＳに含まれるペレットがｃ軸配向性を有し、ｃ軸が被形成面または上面に略垂直な方向を向いていることがわかる。一方、同じ試料に対し、試料面に垂直にプローブ径が３００ｎｍの電子線を入射させたときの回折パターンを図２（Ｅ）に示す。図２（Ｅ）より、リング状の回折パターンが確認される。したがって、プローブ径が３００ｎｍの電子線を用いた電子回折によっても、ＣＡＡＣ−ＯＳに含まれるペレットのａ軸およびｂ軸は配向性を有さないことがわかる。なお、図２（Ｅ）における第１リングは、ＩｎＧａＺｎＯ４の結晶の（０１０）面および（１００）面などに起因すると考えられる。また、図２（Ｅ）における第２リングは（１１０）面などに起因すると考えられる。 Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO 4 crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO 4 crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 2E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 2E is considered to originate from the (010) plane and the (100) plane of InGaZnO 4 crystal. Further, the second ring in FIG. 2E is considered to be due to the (110) plane and the like.
また、透過型電子顕微鏡（ＴＥＭ：Ｔｒａｎｓｍｉｓｓｉｏｎ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ）によって、ＣＡＡＣ−ＯＳの明視野像と回折パターンとの複合解析像（高分解能ＴＥＭ像ともいう。）を観察すると、複数のペレットを確認することができる。一方、高分解能ＴＥＭ像であってもペレット同士の境界、即ち結晶粒界（グレインバウンダリーともいう。）を明確に確認することができない場合がある。そのため、ＣＡＡＣ−ＯＳは、結晶粒界に起因する電子移動度の低下が起こりにくいといえる。 In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of CAAC-OS is observed with a transmission electron microscope (TEM: Transmission Electron Microscope), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.
図３（Ａ）に、試料面と略平行な方向から観察したＣＡＡＣ−ＯＳの断面の高分解能ＴＥＭ像を示す。高分解能ＴＥＭ像の観察には、球面収差補正（Ｓｐｈｅｒｉｃａｌ　Ａｂｅｒｒａｔｉｏｎ　Ｃｏｒｒｅｃｔｏｒ）機能を用いた。球面収差補正機能を用いた高分解能ＴＥＭ像を、特にＣｓ補正高分解能ＴＥＭ像と呼ぶ。Ｃｓ補正高分解能ＴＥＭ像は、例えば、日本電子株式会社製原子分解能分析電子顕微鏡ＪＥＭ−ＡＲＭ２００Ｆなどによって観察することができる。 FIG. 3A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
図３（Ａ）より、金属原子が層状に配列している領域であるペレットを確認することができる。ペレット一つの大きさは１ｎｍ以上のものや、３ｎｍ以上のものがあることがわかる。したがって、ペレットを、ナノ結晶（ｎｃ：ｎａｎｏｃｒｙｓｔａｌ）と呼ぶこともできる。また、ＣＡＡＣ−ＯＳを、ＣＡＮＣ（Ｃ−Ａｘｉｓ　Ａｌｉｇｎｅｄ　ｎａｎｏｃｒｙｓｔａｌｓ）を有する酸化物半導体と呼ぶこともできる。ペレットは、ＣＡＡＣ−ＯＳの膜を被形成面または上面の凹凸を反映しており、ＣＡＡＣ−ＯＳの被形成面または上面と平行となる。 From FIG. 3A, a pellet which is a region where metal atoms are arranged in a layered manner can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). The CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals). The pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.
また、図３（Ｂ）および図３（Ｃ）に、試料面と略垂直な方向から観察したＣＡＡＣ−ＯＳの平面のＣｓ補正高分解能ＴＥＭ像を示す。図３（Ｄ）および図３（Ｅ）は、それぞれ図３（Ｂ）および図３（Ｃ）を画像処理した像である。以下では、画像処理の方法について説明する。まず、図３（Ｂ）を高速フーリエ変換（ＦＦＴ：Ｆａｓｔ　Ｆｏｕｒｉｅｒ　Ｔｒａｎｓｆｏｒｍ）処理することでＦＦＴ像を取得する。次に、取得したＦＦＴ像において原点を基準に、２．８ｎｍ−１から５．０ｎｍ−１の間の範囲を残すマスク処理する。次に、マスク処理したＦＦＴ像を、逆高速フーリエ変換（ＩＦＦＴ：Ｉｎｖｅｒｓｅ　Ｆａｓｔ　Ｆｏｕｒｉｅｒ　Ｔｒａｎｓｆｏｒｍ）処理することで画像処理した像を取得する。こうして取得した像をＦＦＴフィルタリング像と呼ぶ。ＦＦＴフィルタリング像は、Ｃｓ補正高分解能ＴＥＭ像から周期成分を抜き出した像であり、格子配列を示している。 3B and 3C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. 3D and 3E are images obtained by performing image processing on FIGS. 3B and 3C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is obtained by performing a fast Fourier transform (FFT) process on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm -1 from 2.8 nm -1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.
図３（Ｄ）では、格子配列の乱れた箇所を破線で示している。破線で囲まれた領域が、一つのペレットである。そして、破線で示した箇所がペレットとペレットとの連結部である。破線は、六角形状であるため、ペレットが六角形状であることがわかる。なお、ペレットの形状は、正六角形状とは限らず、非正六角形状である場合が多い。 In FIG. 3D, the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.
図３（Ｅ）では、格子配列の揃った領域と、別の格子配列の揃った領域と、の間を点線で示している。点線近傍においても、明確な結晶粒界を確認することはできない。点線近傍の格子点を中心に周囲の格子点を繋ぐと、歪んだ六角形や、五角形または／および七角形などが形成できる。即ち、格子配列を歪ませることによって結晶粒界の形成を抑制していることがわかる。これは、ＣＡＡＣ−ＯＳが、ａ−ｂ面方向において原子配列が稠密でないことや、金属元素が置換することで原子間の結合距離が変化することなどによって、歪みを許容することができるためと考えられる。 In FIG. 3E, a dotted line is shown between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. By connecting the surrounding lattice points around the lattice points in the vicinity of the dotted line, a distorted hexagon, pentagon, and / or heptagon can be formed. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.
以上に示すように、ＣＡＡＣ−ＯＳは、ｃ軸配向性を有し、かつａ−ｂ面方向において複数のペレット（ナノ結晶）が連結し、歪みを有した結晶構造となっている。よって、ＣＡＡＣ−ＯＳを、ＣＡＡｃｒｙｓｔａｌ（ｃ−ａｘｉｓ−ａｌｉｇｎｅｄ　ａ−ｂ−ｐｌａｎｅ−ａｎｃｈｏｒｅｄ　ｃｒｙｓｔａｌ）を有する酸化物半導体と称することもできる。 As described above, the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as an oxide semiconductor having CAAcrystal (c-axis-aligned ab-plane-anchored crystal).
ＣＡＡＣ−ＯＳは結晶性の高い酸化物半導体である。酸化物半導体の結晶性は不純物の混入や欠陥の生成などによって低下する場合があるため、ＣＡＡＣ−ＯＳは不純物や欠陥（酸素欠損など）の少ない酸化物半導体ともいえる。 The CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).
なお、不純物は、酸化物半導体の主成分以外の元素で、水素、炭素、シリコン、遷移金属元素などがある。例えば、シリコンなどの、酸化物半導体を構成する金属元素よりも酸素との結合力の強い元素は、酸化物半導体から酸素を奪うことで酸化物半導体の原子配列を乱し、結晶性を低下させる要因となる。また、鉄やニッケルなどの重金属、アルゴン、二酸化炭素などは、原子半径（または分子半径）が大きいため、酸化物半導体の原子配列を乱し、結晶性を低下させる要因となる。 Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
酸化物半導体が不純物や欠陥を有する場合、光や熱などによって特性が変動する場合がある。例えば、酸化物半導体に含まれる不純物は、キャリアトラップとなる場合や、キャリア発生源となる場合がある。例えば、酸化物半導体中の酸素欠損は、キャリアトラップとなる場合や、水素を捕獲することによってキャリア発生源となる場合がある。 In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.
不純物および酸素欠損の少ないＣＡＡＣ−ＯＳは、キャリア密度の低い酸化物半導体である。具体的には、８×１０１１／ｃｍ３未満、好ましくは１×１０１１／ｃｍ３未満、さらに好ましくは１×１０１０／ｃｍ３未満であり、１×１０−９／ｃｍ３以上のキャリア密度の酸化物半導体とすることができる。そのような酸化物半導体を、高純度真性または実質的に高純度真性な酸化物半導体と呼ぶ。ＣＡＡＣ−ＯＳは、不純物濃度が低く、欠陥準位密度が低い。即ち、安定な特性を有する酸化物半導体であるといえる。 A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8 × 10 11 / cm 3 , preferably less than 1 × 10 11 / cm 3 , more preferably less than 1 × 10 10 / cm 3 , and a carrier of 1 × 10 −9 / cm 3 or more. A dense oxide semiconductor can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.
＜ｎｃ−ＯＳ＞
次に、ｎｃ−ＯＳについて説明する。 <Nc-OS>
Next, the nc-OS will be described.
ｎｃ−ＯＳをＸＲＤによって解析した場合について説明する。例えば、ｎｃ−ＯＳに対し、ｏｕｔ−ｏｆ−ｐｌａｎｅ法による構造解析を行うと、配向性を示すピークが現れない。即ち、ｎｃ−ＯＳの結晶は配向性を有さない。 A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.
また、例えば、ＩｎＧａＺｎＯ４の結晶を有するｎｃ−ＯＳを薄片化し、厚さが３４ｎｍの領域に対し、被形成面に平行にプローブ径が５０ｎｍの電子線を入射させると、図４（Ａ）に示すようなリング状の回折パターン（ナノビーム電子回折パターン）が観測される。また、同じ試料にプローブ径が１ｎｍの電子線を入射させたときの回折パターン（ナノビーム電子回折パターン）を図４（Ｂ）に示す。図４（Ｂ）より、リング状の領域内に複数のスポットが観測される。したがって、ｎｃ−ＯＳは、プローブ径が５０ｎｍの電子線を入射させることでは秩序性が確認されないが、プローブ径が１ｎｍの電子線を入射させることでは秩序性が確認される。 For example, when an nc-OS including an InGaZnO 4 crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm in parallel to the formation surface, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 4B shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam having a probe diameter of 1 nm is incident on the same sample. From FIG. 4B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.
また、厚さが１０ｎｍ未満の領域に対し、プローブ径が１ｎｍの電子線を入射させると、図４（Ｃ）に示すように、スポットが略正六角状に配置された電子回折パターンを観測される場合がある。したがって、厚さが１０ｎｍ未満の範囲において、ｎｃ−ＯＳが秩序性の高い領域、即ち結晶を有することがわかる。なお、結晶が様々な方向を向いているため、規則的な電子回折パターンが観測されない領域もある。 When an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.
図４（Ｄ）に、被形成面と略平行な方向から観察したｎｃ−ＯＳの断面のＣｓ補正高分解能ＴＥＭ像を示す。ｎｃ−ＯＳは、高分解能ＴＥＭ像において、補助線で示す箇所などのように結晶部を確認することのできる領域と、明確な結晶部を確認することのできない領域と、を有する。ｎｃ−ＯＳに含まれる結晶部は、１ｎｍ以上１０ｎｍ以下の大きさであり、特に１ｎｍ以上３ｎｍ以下の大きさであることが多い。なお、結晶部の大きさが１０ｎｍより大きく１００ｎｍ以下である酸化物半導体を微結晶酸化物半導体（ｍｉｃｒｏ　ｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）と呼ぶことがある。ｎｃ−ＯＳは、例えば、高分解能ＴＥＭ像では、結晶粒界を明確に確認できない場合がある。なお、ナノ結晶は、ＣＡＡＣ−ＯＳにおけるペレットと起源を同じくする可能性がある。そのため、以下ではｎｃ−ＯＳの結晶部をペレットと呼ぶ場合がある。 FIG. 4D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.
このように、ｎｃ−ＯＳは、微小な領域（例えば、１ｎｍ以上１０ｎｍ以下の領域、特に１ｎｍ以上３ｎｍ以下の領域）において原子配列に周期性を有する。また、ｎｃ−ＯＳは、異なるペレット間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、ｎｃ−ＯＳは、分析方法によっては、ａ−ｌｉｋｅ　ＯＳや非晶質酸化物半導体と区別が付かない場合がある。 Thus, the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
なお、ペレット（ナノ結晶）間で結晶方位が規則性を有さないことから、ｎｃ−ＯＳを、ＲＡＮＣ（Ｒａｎｄｏｍ　Ａｌｉｇｎｅｄ　ｎａｎｏｃｒｙｓｔａｌｓ）を有する酸化物半導体、またはＮＡＮＣ（Ｎｏｎ−Ａｌｉｇｎｅｄ　ｎａｎｏｃｒｙｓｔａｌｓ）を有する酸化物半導体と呼ぶこともできる。 Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.
ｎｃ−ＯＳは、非晶質酸化物半導体よりも規則性の高い酸化物半導体である。そのため、ｎｃ−ＯＳは、ａ−ｌｉｋｅ　ＯＳや非晶質酸化物半導体よりも欠陥準位密度が低くなる。ただし、ｎｃ−ＯＳは、異なるペレット間で結晶方位に規則性が見られない。そのため、ｎｃ−ＯＳは、ＣＡＡＣ−ＯＳと比べて欠陥準位密度が高くなる。 The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
＜ａ−ｌｉｋｅ　ＯＳ＞
ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳと非晶質酸化物半導体との間の構造を有する酸化物半導体である。 <A-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.
図５に、ａ−ｌｉｋｅ　ＯＳの高分解能断面ＴＥＭ像を示す。ここで、図５（Ａ）は電子照射開始時におけるａ−ｌｉｋｅ　ＯＳの高分解能断面ＴＥＭ像である。図５（Ｂ）は４．３×１０８ｅ−／ｎｍ２の電子（ｅ−）照射後におけるａ−ｌｉｋｅ　ＯＳの高分解能断面ＴＥＭ像である。図５（Ａ）および図５（Ｂ）より、ａ−ｌｉｋｅ　ＯＳは電子照射開始時から、縦方向に延伸する縞状の明領域が観察されることがわかる。また、明領域は、電子照射後に形状が変化することがわかる。なお、明領域は、鬆または低密度領域と推測される。 FIG. 5 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 5A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 5B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e − ) of 4.3 × 10 8 e − / nm 2 . From FIG. 5A and FIG. 5B, it can be seen that the a-like OS has a striped bright region extending in the vertical direction from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.
鬆を有するため、ａ−ｌｉｋｅ　ＯＳは、不安定な構造である。以下では、ａ−ｌｉｋｅ　ＯＳが、ＣＡＡＣ−ＯＳおよびｎｃ−ＯＳと比べて不安定な構造であることを示すため、電子照射による構造の変化を示す。 Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, a change in structure due to electron irradiation is shown.
試料として、ａ−ｌｉｋｅ　ＯＳ、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳを準備する。いずれの試料もＩｎ−Ｇａ−Ｚｎ酸化物である。 As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.
まず、各試料の高分解能断面ＴＥＭ像を取得する。高分解能断面ＴＥＭ像により、各試料は、いずれも結晶部を有する。 First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.
なお、ＩｎＧａＺｎＯ４の結晶の単位格子は、Ｉｎ−Ｏ層を３層有し、またＧａ−Ｚｎ−Ｏ層を６層有する、計９層がｃ軸方向に層状に重なった構造を有することが知られている。これらの近接する層同士の間隔は、（００９）面の格子面間隔（ｄ値ともいう。）と同程度であり、結晶構造解析からその値は０．２９ｎｍと求められている。したがって、以下では、格子縞の間隔が０．２８ｎｍ以上０．３０ｎｍ以下である箇所を、ＩｎＧａＺｎＯ４の結晶部と見なした。なお、格子縞は、ＩｎＧａＺｎＯ４の結晶のａ−ｂ面に対応する。 Note that a unit cell of an InGaZnO 4 crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO 4 . Note that the lattice fringes correspond to the ab plane of the InGaZnO 4 crystal.
図６は、各試料の結晶部（２２箇所から３０箇所）の平均の大きさを調査した例である。なお、上述した格子縞の長さを結晶部の大きさとしている。図６より、ａ−ｌｉｋｅ　ＯＳは、ＴＥＭ像の取得などに係る電子の累積照射量に応じて結晶部が大きくなっていくことがわかる。図６より、ＴＥＭによる観察初期においては１．２ｎｍ程度の大きさだった結晶部（初期核ともいう。）が、電子（ｅ−）の累積照射量が４．２×１０８ｅ−／ｎｍ２においては１．９ｎｍ程度の大きさまで成長していることがわかる。一方、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳは、電子照射開始時から電子の累積照射量が４．２×１０８ｅ−／ｎｍ２までの範囲で、結晶部の大きさに変化が見られないことがわかる。図６より、電子の累積照射量によらず、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳの結晶部の大きさは、それぞれ１．３ｎｍ程度および１．８ｎｍ程度であることがわかる。なお、電子線照射およびＴＥＭの観察は、日立透過電子顕微鏡Ｈ−９０００ＮＡＲを用いた。電子線照射条件は、加速電圧を３００ｋＶ、電流密度を６．７×１０５ｅ−／（ｎｍ２・ｓ）、照射領域の直径を２３０ｎｍとした。 FIG. 6 is an example in which the average size of crystal parts (22 to 30 locations) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 6, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative dose of electrons related to the acquisition of the TEM image or the like. From FIG. 6, the crystal part (also referred to as the initial nucleus) having a size of about 1.2 nm at the beginning of observation by TEM has an accumulated electron (e − ) irradiation dose of 4.2 × 10 8 e − / nm. In FIG. 2 , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 8 e − / nm 2. I understand. FIG. 6 indicates that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 5 e − / (nm 2 · s), and an irradiation region diameter of 230 nm.
このように、ａ−ｌｉｋｅ　ＯＳは、電子照射によって結晶部の成長が見られる場合がある。一方、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳは、電子照射による結晶部の成長がほとんど見られない。即ち、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳと比べて、不安定な構造であることがわかる。 As described above, in the a-like OS, the crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
また、鬆を有するため、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳと比べて密度の低い構造である。具体的には、ａ−ｌｉｋｅ　ＯＳの密度は、同じ組成の単結晶の密度の７８．６％以上９２．３％未満である。また、ｎｃ−ＯＳの密度およびＣＡＡＣ−ＯＳの密度は、同じ組成の単結晶の密度の９２．３％以上１００％未満である。単結晶の密度の７８％未満である酸化物半導体は、成膜すること自体が困難である。 In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of single crystals having the same composition. An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.
例えば、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］を満たす酸化物半導体において、菱面体晶構造を有する単結晶ＩｎＧａＺｎＯ４の密度は６．３５７ｇ／ｃｍ３である。よって、例えば、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］を満たす酸化物半導体において、ａ−ｌｉｋｅ　ＯＳの密度は５．０ｇ／ｃｍ３以上５．９ｇ／ｃｍ３未満である。また、例えば、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］を満たす酸化物半導体において、ｎｃ−ＯＳの密度およびＣＡＡＣ−ＯＳの密度は５．９ｇ／ｃｍ３以上６．３ｇ／ｃｍ３未満である。 For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO 4 having a rhombohedral structure is 6.357 g / cm 3 . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm 3 or more and 6.3 g / less than cm 3 .
なお、同じ組成の単結晶が存在しない場合、任意の割合で組成の異なる単結晶を組み合わせることにより、所望の組成における単結晶に相当する密度を見積もることができる。所望の組成の単結晶に相当する密度は、組成の異なる単結晶を組み合わせる割合に対して、加重平均を用いて見積もればよい。ただし、密度は、可能な限り少ない種類の単結晶を組み合わせて見積もることが好ましい。 Note that when single crystals having the same composition do not exist, it is possible to estimate a density corresponding to a single crystal having a desired composition by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.
以上のように、酸化物半導体は、様々な構造をとり、それぞれが様々な特性を有する。なお、酸化物半導体は、例えば、非晶質酸化物半導体、ａ−ｌｉｋｅ　ＯＳ、ｎｃ−ＯＳ、ＣＡＡＣ−ＯＳのうち、二種以上を有する積層膜であってもよい。 As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
＜基板、絶縁体、導電体＞
以下に、トランジスタ１０の半導体以外の各構成要素について詳細な説明を行う。 <Substrate, insulator, conductor>
Hereinafter, each component other than the semiconductor of the transistor 10 will be described in detail.
基板１００は、例えば、絶縁体基板、半導体基板または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板（イットリア安定化ジルコニア基板など）、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの単体半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムなどの半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えばＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。 As the substrate 100, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
また、基板１００として、トランジスタ作製時の加熱処理に耐えうる可とう性基板を用いてもよい。なお、可とう性基板上にトランジスタを設ける方法としては、非可とう性の基板上にトランジスタを作製した後、トランジスタを剥離し、可とう性基板である基板１００に転置する方法もある。その場合には、非可とう性基板とトランジスタとの間に剥離層を設けるとよい。なお、基板１００として、繊維を編みこんだシート、フィルムまたは箔などを用いてもよい。また、基板１００が伸縮性を有してもよい。また、基板１００は、折り曲げや引っ張りをやめた際に、元の形状に戻る性質を有してもよい。または、元の形状に戻らない性質を有してもよい。基板１００の厚さは、例えば、５μｍ以上７００μｍ以下、好ましくは１０μｍ以上５００μｍ以下、さらに好ましくは１５μｍ以上３００μｍ以下とする。基板１００を薄くすると、半導体装置を軽量化することができる。また、基板１００を薄くすることで、ガラスなどを用いた場合にも伸縮性を有する場合や、折り曲げや引っ張りをやめた際に、元の形状に戻る性質を有する場合がある。そのため、落下などによって基板１００上の半導体装置に加わる衝撃などを緩和することができる。即ち、丈夫な半導体装置を提供することができる。 Alternatively, a flexible substrate that can withstand heat treatment at the time of manufacturing the transistor may be used as the substrate 100. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is manufactured over a non-flexible substrate, the transistor is peeled off and transferred to the substrate 100 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate 100. Further, the substrate 100 may have elasticity. Further, the substrate 100 may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The thickness of the substrate 100 is, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, more preferably 15 μm to 300 μm. When the substrate 100 is thinned, the semiconductor device can be reduced in weight. Further, by reducing the thickness of the substrate 100, there are cases where the glass 100 or the like is stretchable or has a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 100 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.
可とう性基板である基板１００としては、例えば、金属、合金、樹脂もしくはガラス、またはそれらの繊維などを用いることができる。可とう性基板である基板１００は、線膨張率が低いほど環境による変形が抑制されて好ましい。可とう性基板である基板１００としては、例えば、線膨張率が１×１０−３／Ｋ以下、５×１０−５／Ｋ以下、または１×１０−５／Ｋ以下である材質を用いればよい。樹脂としては、例えば、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミドなど）、ポリイミド、ポリカーボネート、アクリルなどがある。特に、アラミドは、線膨張率が低いため、可とう性基板である基板１００として好適である。 As the substrate 100 which is a flexible substrate, for example, metal, alloy, resin, glass, or fiber thereof can be used. The substrate 100, which is a flexible substrate, is preferable because the deformation due to the environment is suppressed as the linear expansion coefficient is lower. As the substrate 100 that is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 −3 / K or less, 5 × 10 −5 / K or less, or 1 × 10 −5 / K or less is used. Good. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as the substrate 100 that is a flexible substrate.
絶縁体１０１は、水素または水をブロックする機能を有する絶縁体を用いる。絶縁体１０６ａ、半導体１０６ｂ、絶縁体１０６ｃ近傍に設けられる絶縁体中の水素や水は、絶縁体１０６ａ、半導体１０６ｂ、絶縁体１０６ｃ中にキャリアを生成する要因の一つとなることがある。これによりトランジスタ１０の信頼性が低下するおそれがある。特に基板１００としてスイッチ素子などのシリコン系半導体素子を設けた基板を用いる場合、当該半導体素子のダングリングボンドを終端するために水素が用いられ、当該水素がトランジスタ１０まで拡散するおそれがある。これに対して水素または水をブロックする機能を有する絶縁体１０１を設けることによりトランジスタ１０の下層から水素または水が拡散するのを抑制し、トランジスタ１０の信頼性を向上させることができる。 As the insulator 101, an insulator having a function of blocking hydrogen or water is used. Hydrogen and water in the insulator provided in the vicinity of the insulator 106a, the semiconductor 106b, and the insulator 106c may be one of the factors that generate carriers in the insulator 106a, the semiconductor 106b, and the insulator 106c. This may reduce the reliability of the transistor 10. In particular, when a substrate provided with a silicon-based semiconductor element such as a switch element is used as the substrate 100, hydrogen is used to terminate dangling bonds of the semiconductor element, and the hydrogen may diffuse to the transistor 10. On the other hand, by providing the insulator 101 having a function of blocking hydrogen or water, diffusion of hydrogen or water from the lower layer of the transistor 10 can be suppressed, and the reliability of the transistor 10 can be improved.
また、絶縁体１０１は酸素をブロックする機能も有することが好ましい。絶縁体１０１が絶縁体１０４から拡散する酸素をブロックすることにより、例えば絶縁体１０４などから絶縁体１０６ａ、半導体１０６ｂ、絶縁体１０６ｃに効果的に酸素を供給することができる。 The insulator 101 preferably has a function of blocking oxygen. When the insulator 101 blocks oxygen diffused from the insulator 104, oxygen can be effectively supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c, for example.
絶縁体１０１としては、例えば、酸化アルミニウム、酸化窒化アルミニウム、酸化ガリウム、酸化窒化ガリウム、酸化イットリウム、酸化窒化イットリウム、酸化ハフニウム、酸化窒化ハフニウム等を用いることができる。これらを絶縁体１０１として用いることにより、酸素、水素または水の拡散をブロックする効果を示す絶縁膜として機能することができる。また、絶縁体１０１としては、例えば、窒化シリコン、窒化酸化シリコン等を用いることができる。これらを絶縁体１０１として用いることにより、水素、水の拡散をブロックする効果を示す絶縁膜として機能することができる。 As the insulator 101, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. By using these as the insulator 101, it can function as an insulating film which has an effect of blocking diffusion of oxygen, hydrogen, or water. As the insulator 101, for example, silicon nitride, silicon nitride oxide, or the like can be used. By using these as the insulator 101, it can function as an insulating film having an effect of blocking diffusion of hydrogen and water.
導電体１０２は、少なくとも一部が導電体１０８ａと導電体１０８ｂに挟まれる領域において半導体１０６ｂと重なることが好ましい。導電体１０２は、トランジスタ１０のバックゲートとして機能する。このような導電体１０２を設けることにより、トランジスタ１０のしきい値電圧の制御を行うことができる。しきい値電圧の制御を行うことによって、トランジスタ１０のゲート（導電体１１４）に印加された電圧が低い、例えば印加された電圧が０Ｖ以下のときに、トランジスタ１０が導通状態となることを防ぐことができる。つまり、トランジスタ１０の電気特性を、よりノーマリーオフの方向にシフトさせることが容易になる。なお、導電体１１４と導電体１０２は、電気的に接続され、同じ電位を与える構成としてもよい。また、導電体１１４と導電体１０２は、電気的に接続せず、それぞれに電位を与える構成としてもよい。 The conductor 102 preferably overlaps with the semiconductor 106b in a region where at least part of the conductor 102 is sandwiched between the conductor 108a and the conductor 108b. The conductor 102 functions as a back gate of the transistor 10. By providing such a conductor 102, the threshold voltage of the transistor 10 can be controlled. By controlling the threshold voltage, the transistor 10 is prevented from becoming conductive when the voltage applied to the gate (conductor 114) of the transistor 10 is low, for example, when the applied voltage is 0 V or less. be able to. That is, it becomes easier to shift the electrical characteristics of the transistor 10 in a normally-off direction. Note that the conductor 114 and the conductor 102 may be electrically connected to provide the same potential. Alternatively, the conductor 114 and the conductor 102 may not be electrically connected, and may be configured to apply a potential to each.
導電体１０２としては、例えば、ホウ素、窒素、酸素、フッ素、シリコン、リン、アルミニウム、チタン、クロム、マンガン、コバルト、ニッケル、銅、亜鉛、ガリウム、イットリウム、ジルコニウム、モリブデン、ルテニウム、銀、インジウム、スズ、タンタルおよびタングステンを一種以上含む導電体を、単層で、または積層で用いればよい。例えば、合金や化合物であってもよく、アルミニウムを含む導電体、銅およびチタンを含む導電体、銅およびマンガンを含む導電体、インジウム、スズおよび酸素を含む導電体、チタンおよび窒素を含む導電体などを用いてもよい。 Examples of the conductor 102 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, A conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.
また、導電体１０２としては、タングステンと、シリコン、炭素、ゲルマニウム、スズ、アルミニウムまたはニッケルから選ばれた一以上の元素と、を有する領域を有する導電体を用いてもよい。特に、タングステンと、シリコンと、を有する導電体が好ましい。さらに、ＲＢＳにより得られるシリコン濃度が５ａｔｏｍｉｃ％以上７０ａｔｏｍｉｃ％以下である領域を有すると好ましく、シリコン濃度が１０ａｔｏｍｉｃ％以上６０ａｔｏｍｉｃ％以下である領域を有すると、さらに好ましい。導電体１０２は、例えば合金や化合物であってもよく、単層で、または積層で形成すればよい。 Alternatively, the conductor 102 may be a conductor having a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, or nickel. In particular, a conductor including tungsten and silicon is preferable. Furthermore, it is preferable to have a region where the silicon concentration obtained by RBS is 5 atomic% or more and 70 atomic% or less, and it is further preferable that the region has a silicon concentration of 10 atomic% or more and 60 atomic% or less. The conductor 102 may be an alloy or a compound, for example, and may be formed as a single layer or a stacked layer.
また、導電体１０２は、導電体１０２の表面にシリコンおよび酸素を有する領域を有し、該領域の厚さは０．２ｎｍ以上２０ｎｍ以下であると好ましい。該領域は、シリコンと酸素が多く含まれた領域とすることができ、その場合、該領域は絶縁体として機能することができる。また、該領域がバリア層として機能することによって、導電体全体が酸化されるのを抑制することができる。 The conductor 102 has a region including silicon and oxygen on the surface of the conductor 102, and the thickness of the region is preferably 0.2 nm to 20 nm. The region can be a region containing a large amount of silicon and oxygen, in which case the region can function as an insulator. Further, since the region functions as a barrier layer, the entire conductor can be prevented from being oxidized.
また、導電体１０２は、スパッタリング法により成膜すればよい。または、金属ＣＶＤ（ＭＣＶＤ：Ｍｅｔａｌ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法により成膜すればよい。 The conductor 102 may be formed by a sputtering method. Alternatively, the film may be formed by a metal CVD (Metal Chemical Vapor Deposition) method.
絶縁体１０５は導電体１０２を覆うように設けられる。絶縁体１０５は、後述する絶縁体１０４または絶縁体１１２と同様の絶縁体を用いることができる。 The insulator 105 is provided so as to cover the conductor 102. As the insulator 105, an insulator similar to the insulator 104 or the insulator 112 described later can be used.
絶縁体１０３は絶縁体１０５を覆うように設けられる。絶縁体１０３は、酸素をブロックする機能を有することが好ましい。このような絶縁体１０３を設けることにより絶縁体１０４から導電体１０２が酸素を引き抜くことを防ぐことができる。これにより、絶縁体１０４から絶縁体１０６ａ、半導体１０６ｂ、絶縁体１０６ｃに効果的に酸素を供給することができる。 The insulator 103 is provided so as to cover the insulator 105. The insulator 103 preferably has a function of blocking oxygen. By providing such an insulator 103, the conductor 102 can be prevented from extracting oxygen from the insulator 104. Accordingly, oxygen can be effectively supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c.
絶縁体１０３としては、ホウ素、アルミニウム、シリコン、スカンジウム、チタン、ガリウム、イットリウム、ジルコニウム、インジウム、ランタン、セリウム、ネオジム、ハフニウムまたはタリウムを有する酸化物または窒化物を、単層で、または積層で用いればよい。例えば、酸化シリコンまたは酸化窒化シリコンを用いてもよい。また、酸化ハフニウムまたは酸化アルミニウムを用いてもよい。 As the insulator 103, an oxide or nitride containing boron, aluminum, silicon, scandium, titanium, gallium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, hafnium, or thallium is used as a single layer or a stacked layer. That's fine. For example, silicon oxide or silicon oxynitride may be used. Further, hafnium oxide or aluminum oxide may be used.
図１（Ｂ）に示すように、絶縁体１０３と導電体１０２の上面は、化学機械研磨（ＣＭＰ：Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）法などによって平坦化処理を行って平坦性の向上を図ることが好ましい。これにより、バックゲートとして機能する導電体１０２を設けても、半導体１０６ｂを形成する面の平坦性が損なわれないため、キャリアの移動度を向上させ、トランジスタ１０のオン電流を増大させることができる。 As shown in FIG. 1B, it is preferable that the upper surfaces of the insulator 103 and the conductor 102 be planarized by a chemical mechanical polishing (CMP) method or the like to improve planarity. Accordingly, even when the conductor 102 functioning as a back gate is provided, the flatness of the surface over which the semiconductor 106b is formed is not impaired, so that carrier mobility can be improved and the on-state current of the transistor 10 can be increased. .
また、導電体１０２は、絶縁体１０３中に埋め込まれるように設けられているが、本実施の形態に示す半導体装置の構成はこれに限られるものではなく、例えば、導電体１０２を覆うように絶縁体１０３を設ける構成としてもよい。その場合、絶縁体１０３は、酸素をブロックする機能を有することが好ましい。このような絶縁体１０３を設けることにより、導電体１０２の酸化を防ぐ、言い換えると絶縁体１０４から導電体１０２が酸素を引き抜くことを防ぐことができる。これにより、絶縁体１０４から絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに効果的に酸素を供給することができる。 The conductor 102 is provided so as to be embedded in the insulator 103; however, the structure of the semiconductor device described in this embodiment is not limited thereto, and for example, covers the conductor 102. The insulator 103 may be provided. In that case, the insulator 103 preferably has a function of blocking oxygen. By providing such an insulator 103, oxidation of the conductor 102 can be prevented, in other words, the conductor 102 can be prevented from extracting oxygen from the insulator 104. Accordingly, oxygen can be effectively supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c.
絶縁体１０４は膜中に含まれる水または水素の量が少ないことが好ましい。例えば、絶縁体１０４としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁体を、単層で、または積層で用いればよい。例えば、絶縁体１０４としては、酸化アルミニウム、酸化マグネシウム、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウムまたは酸化タンタルを用いればよい。好ましくは、酸化シリコンまたは酸化窒化シリコンを用いる。 The insulator 104 preferably contains a small amount of water or hydrogen contained in the film. For example, the insulator 104 includes, for example, an insulating material including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The body may be used in a single layer or a stack. For example, as the insulator 104, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used. Preferably, silicon oxide or silicon oxynitride is used.
絶縁体１０４中に含まれる水または水素の量は、少ないことが好ましい。例えば、絶縁体１０４は、昇温脱離ガス分析（ＴＤＳ：Ｔｈｅｒｍａｌ　Ｄｅｓｏｒｐｔｉｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）にて、１００℃以上７００℃以下または１００℃以上５００℃以下の表面温度の範囲で、水分子の脱離量が１．０×１０１３分子／ｃｍ２以上１．４×１０１６分子／ｃｍ２以下、さらに１．０×１０１３分子／ｃｍ２以上４．０×１０１５分子／ｃｍ２以下、さらに１．０×１０１３分子／ｃｍ２以上２．０×１０１５分子／ｃｍ２以下となることが好ましい。また、ＴＤＳにて、１００℃以上７００℃以下または１００℃以上５００℃以下の表面温度の範囲で、水素分子の脱離量が１．０×１０１３分子／ｃｍ２以上１．２×１０１５分子／ｃｍ２以下、さらに１．０×１０１３分子／ｃｍ２以上９．０×１０１４分子／ｃｍ２以下となることが好ましい。なお、ＴＤＳを用いた分子の放出量の測定方法の詳細については、後述する。 The amount of water or hydrogen contained in the insulator 104 is preferably small. For example, the insulator 104 has a desorption amount of water molecules in a surface temperature range of 100 ° C. or higher and 700 ° C. or lower or 100 ° C. or higher and 500 ° C. or lower in a temperature desorption gas analysis (TDS: Thermal Desorption Spectroscopy). 1.0 × 10 13 molecules / cm 2 or more and 1.4 × 10 16 molecules / cm 2 or less, 1.0 × 10 13 molecules / cm 2 or more and 4.0 × 10 15 molecules / cm 2 or less, and further 1. It is preferably 0 × 10 13 molecules / cm 2 or more and 2.0 × 10 15 molecules / cm 2 or less. Further, in TDS, the desorption amount of hydrogen molecules is 1.0 × 10 13 molecules / cm 2 or more and 1.2 × 10 15 in the range of the surface temperature of 100 ° C. or more and 700 ° C. or less or 100 ° C. or more and 500 ° C. or less. molecules / cm 2 or less, preferably further comprising a 1.0 × 10 13 molecules / cm 2 or more 9.0 × 10 14 molecules / cm 2 or less. The details of the method for measuring the amount of released molecules using TDS will be described later.
水、水素などの不純物は、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃ、特に半導体１０６ｂにおいて欠陥準位を形成し、トランジスタの電気特性を変動させる要因となる。このため、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃの下に設けられている絶縁体１０４中の水または水素量を低減することにより、絶縁体１０４から水、水素などが半導体１０６ｂなどに供給されて欠陥準位が形成されることを低減できる。このように欠陥準位密度が低減された酸化物半導体を用いることにより、安定した電気特性を有するトランジスタを提供することができる。 Impurities such as water and hydrogen form defect levels in the insulator 106a, the semiconductor 106b, and the insulator 106c, particularly the semiconductor 106b, and cause fluctuation in electric characteristics of the transistor. Therefore, water, hydrogen, or the like is supplied from the insulator 104 to the semiconductor 106b or the like by reducing the amount of water or hydrogen in the insulator 104 provided under the insulator 106a, the semiconductor 106b, and the insulator 106c. Thus, the formation of defect levels can be reduced. In this manner, by using an oxide semiconductor with a reduced density of defect states, a transistor having stable electric characteristics can be provided.
絶縁体１０４の成膜は、比較的低温で高品質の膜が得られるプラズマＣＶＤ（ＰＥＣＶＤ：Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＣＶＤ）法を用いて成膜するのが好ましい。しかし、例えば、酸化シリコン膜などをＰＥＣＶＤ法で成膜する場合、原料ガスとしてシリコン水素化物などが用いられることが多く、成膜時に絶縁体１０４中に水素、水などが導入されてしまう。そのため、本実施の形態に示す絶縁体１０４の成膜は、原料ガスとしてハロゲン化シリコンを用いて行うことが好ましい。ここで、ハロゲン化シリコンとしては、例えば、ＳｉＦ４（四フッ化シリコン）、ＳｉＣｌ４（四塩化シリコン）、ＳｉＨＣｌ３（三塩化シリコン）、ＳｉＨ２Ｃｌ２（ジクロルシラン）またはＳｉＢｒ４（四臭化シリコン）などを用いることができ、特にＳｉＦ４（四フッ化シリコン）を用いることが好ましい。 The insulator 104 is preferably formed using a plasma enhanced CVD (PECVD) method in which a high-quality film can be obtained at a relatively low temperature. However, for example, in the case where a silicon oxide film or the like is formed by a PECVD method, silicon hydride or the like is often used as a source gas, and hydrogen, water, or the like is introduced into the insulator 104 at the time of film formation. Therefore, the insulator 104 described in this embodiment is preferably formed using silicon halide as a source gas. Here, as the silicon halide, for example, SiF 4 (silicon tetrafluoride), SiCl 4 (silicon tetrachloride), SiHCl 3 (silicon trichloride), SiH 2 Cl 2 (dichlorosilane) or SiBr 4 (tetrabromide). Silicon) or the like can be used, and SiF 4 (silicon tetrafluoride) is particularly preferable.
また、絶縁体１０４の成膜に、原料ガスとしてハロゲン化シリコンを用いる場合、ハロゲン化シリコンに加えてシリコン水素化物を加えてもよい。これにより、シリコン水素化物だけを原料ガスにした場合より絶縁体１０４中の水素、水の含有量を減らし、且つハロゲン化シリコンだけを原料ガスとした場合より成膜速度の向上を図ることができる。例えば、ＳｉＦ４とＳｉＨ４を原料ガスとして絶縁体１０４の成膜を行えばよい。なお、ＳｉＦ４とＳｉＨ４の流量の割合は、絶縁体１０４中の水、水素の含有量と成膜速度を考慮して適宜設定すればよい。 Further, in the case where silicon halide is used as a source gas for forming the insulator 104, silicon hydride may be added in addition to silicon halide. Thereby, the content of hydrogen and water in the insulator 104 can be reduced as compared with the case where only silicon hydride is used as the source gas, and the film formation rate can be improved as compared with the case where only silicon halide is used as the source gas. . For example, the insulator 104 may be formed using SiF 4 and SiH 4 as source gases. Note that the ratio of the flow rates of SiF 4 and SiH 4 may be set as appropriate in consideration of the water and hydrogen contents in the insulator 104 and the film formation rate.
また、絶縁体１０４は過剰酸素を有する絶縁体であることが好ましい。このような絶縁体１０４を設けることにより、絶縁体１０４から絶縁体１０６ａ、半導体１０６ｂ、絶縁体１０６ｃに酸素を供給することができる。当該酸素により、酸化物半導体である絶縁体１０６ａ、半導体１０６ｂ、絶縁体１０６ｃの欠陥となる酸素欠損を低減することができる。これにより、絶縁体１０６ａ、半導体１０６ｂ、絶縁体１０６ｃを欠陥準位密度が低い、安定な特性を有する酸化物半導体とすることができる。 The insulator 104 is preferably an insulator having excess oxygen. By providing such an insulator 104, oxygen can be supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c. With the oxygen, oxygen vacancies that are defects in the insulator 106a, the semiconductor 106b, and the insulator 106c which are oxide semiconductors can be reduced. Accordingly, the insulator 106a, the semiconductor 106b, and the insulator 106c can be oxide semiconductors with low density of defect states and stable characteristics.
なお、本明細書などにおいて、過剰酸素とは、例えば、化学量論的組成を超えて含まれる酸素をいう。または、過剰酸素とは、例えば、加熱することで当該過剰酸素が含まれる膜または層から放出される酸素をいう。過剰酸素は、例えば、膜や層の内部を移動することができる。過剰酸素の移動は、膜や層の原子間を移動する場合や、膜や層を構成する酸素と置き換わりながら玉突き的に移動する場合などがある。 Note that in this specification and the like, excess oxygen refers to oxygen contained in excess of the stoichiometric composition, for example. Alternatively, excess oxygen refers to oxygen released from a film or layer containing the excess oxygen by heating, for example. Excess oxygen can move, for example, inside a film or layer. Excess oxygen may be moved between atoms of a film or layer, or may be moved in a rushing manner while replacing oxygen constituting the film or layer.
過剰酸素を有する絶縁体１０４は、ＴＤＳにて、１００℃以上７００℃以下または１００℃以上５００℃以下の表面温度の範囲で、酸素分子の脱離量が１．０×１０１４分子／ｃｍ２以上１．０×１０１６分子／ｃｍ２以下、より好ましくは、１．０×１０１５分子／ｃｍ２以上５．０×１０１５分子／ｃｍ２以下となる。 The insulator 104 having excess oxygen has an oxygen molecule desorption amount of 1.0 × 10 14 molecules / cm 2 in a surface temperature range of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. in TDS. It is 1.0 × 10 16 molecules / cm 2 or less, more preferably 1.0 × 10 15 molecules / cm 2 or more and 5.0 × 10 15 molecules / cm 2 or less.
ＴＤＳを用いた分子の放出量の測定方法について、酸素の放出量を例として、以下に説明する。 A method for measuring the amount of released molecules using TDS will be described below by taking oxygen released as an example.
測定試料をＴＤＳにより分析したときの気体の全放出量は、放出ガスのイオン強度の積分値に比例する。そして標準試料との比較により、気体の全放出量を計算することができる。 The total amount of gas released when the measurement sample is analyzed by TDS is proportional to the integral value of the ionic strength of the released gas. The total amount of gas released can be calculated by comparison with a standard sample.
例えば、標準試料である所定の密度の水素を含むシリコン基板のＴＤＳ結果、および測定試料のＴＤＳ結果から、測定試料の酸素分子の放出量（ＮＯ２）は、下に示す式で求めることができる。ここで、ＴＤＳによる分析で得られる質量電荷比３２で検出されるガスの全てが酸素分子由来と仮定する。ＣＨ３ＯＨの質量電荷比は３２であるが、存在する可能性が低いものとしてここでは考慮しない。また、酸素原子の同位体である質量数１７の酸素原子および質量数１８の酸素原子を含む酸素分子についても、自然界における存在比率が極微量であるため考慮しない。 For example, the release amount of oxygen molecules (N O2 ) of the measurement sample can be obtained from the TDS result of the silicon substrate containing hydrogen of a predetermined density as a standard sample and the TDS result of the measurement sample by the following equation. . Here, it is assumed that all of the gases detected at the mass to charge ratio of 32 obtained by the TDS analysis are derived from oxygen molecules. The mass to charge ratio of CH 3 OH is 32 but is not considered here as it is unlikely to exist. In addition, oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18 which are isotopes of oxygen atoms are not considered because the existence ratio in nature is extremely small.
ＮＯ２＝ＮＨ２／ＳＨ２×ＳＯ２×α N O2 = N H2 / S H2 × S O2 × α
ＮＨ２は、標準試料から脱離した水素分子を密度で換算した値である。ＳＨ２は、標準試料をＴＤＳにより分析したときのイオン強度の積分値である。ここで、標準試料の基準値を、ＮＨ２／ＳＨ２とする。ＳＯ２は、測定試料をＴＤＳにより分析したときのイオン強度の積分値である。αは、ＴＤＳにおけるイオン強度に影響する係数である。上に示す式の詳細に関しては、特開平６−２７５６９７公報を参照する。なお、上記酸素の放出量は、電子科学株式会社製の昇温脱離分析装置ＥＭＤ−ＷＡ１０００Ｓ／Ｗを用い、標準試料として一定量の水素原子を含むシリコン基板を用いて測定する。 N H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. SH2 is an integral value of ionic strength when a standard sample is analyzed by TDS. Here, the reference value of the standard sample is N H2 / SH 2 . S O2 is an integral value of ion intensity when the measurement sample is analyzed by TDS. α is a coefficient that affects the ionic strength in TDS. For details of the above formula, refer to JP-A-6-275697. The amount of released oxygen is measured using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. and using a silicon substrate containing a certain amount of hydrogen atoms as a standard sample.
また、ＴＤＳにおいて、酸素の一部は酸素原子として検出される。酸素分子と酸素原子の比率は、酸素分子のイオン化率から算出することができる。なお、上述のαは酸素分子のイオン化率を含むため、酸素分子の放出量を評価することで、酸素原子の放出量についても見積もることができる。 In TDS, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.
なお、ＮＯ２は酸素分子の放出量である。酸素原子に換算したときの放出量は、酸素分子の放出量の２倍となる。 Note that N 2 O 2 is the amount of released oxygen molecules. The amount of release when converted to oxygen atoms is twice the amount of release of oxygen molecules.
または、加熱処理によって酸素を放出する絶縁体は、過酸化ラジカルを含むこともある。具体的には、過酸化ラジカルに起因するスピン密度が、５×１０１７ｓｐｉｎｓ／ｃｍ３以上であることをいう。なお、過酸化ラジカルを含む絶縁体は、電子スピン共鳴法（ＥＳＲ：Ｅｌｅｃｔｒｏｎ　Ｓｐｉｎ　Ｒｅｓｏｎａｎｃｅ）にて、ｇ値が２．０１近傍に非対称の信号を有することもある。 Alternatively, the insulator from which oxygen is released by heat treatment may contain a peroxide radical. Specifically, it means that the spin density resulting from the peroxide radical is 5 × 10 17 spins / cm 3 or more. Note that an insulator containing a peroxide radical may have an asymmetric signal with a g value near 2.01 by an electron spin resonance (ESR) method.
また、絶縁体１０４は、基板１００からの不純物の拡散を防止する機能を有してもよい。 The insulator 104 may have a function of preventing diffusion of impurities from the substrate 100.
また、上述の通り半導体１０６ｂの上面または下面は平坦性が高いことが好ましい。このため、絶縁体１０４の上面に化学機械研磨（ＣＭＰ：Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）法などによって平坦化処理を行って平坦性の向上を図ってもよい。 In addition, as described above, the upper surface or the lower surface of the semiconductor 106b preferably has high flatness. For this reason, planarity may be improved by performing a planarization process on the upper surface of the insulator 104 by a chemical mechanical polishing (CMP) method or the like.
導電体１０８ａおよび導電体１０８ｂは、それぞれトランジスタ１０のソース電極またはドレイン電極のいずれかとして機能することができる。 The conductor 108a and the conductor 108b can function as either a source electrode or a drain electrode of the transistor 10, respectively.
導電体１０８ａおよび導電体１０８ｂは、導電体１０２と同様にして形成すればよい。 The conductor 108a and the conductor 108b may be formed in a manner similar to that of the conductor 102.
また、導電体１０８ａおよび導電体１０８ｂを、絶縁体１１８に埋め込むように形成し、絶縁体１１８上の導電体１０９ａおよび導電体１０９ｂと接続させる構成とする場合、絶縁体１１８、導電体１０８ａおよび導電体１０８ｂの上面を、ＣＭＰ法などを用いて平坦化処理し、平坦性を向上させることが好ましい。 In the case where the conductor 108a and the conductor 108b are formed so as to be embedded in the insulator 118 and connected to the conductor 109a and the conductor 109b on the insulator 118, the insulator 118, the conductor 108a, and the conductor The upper surface of the body 108b is preferably planarized using a CMP method or the like to improve planarity.
導電体１０９ａおよび導電体１０９ｂは、それぞれトランジスタ１０のソース電極またはドレイン電極のいずれかと接続する配線して機能する。導電体１０９ａおよび導電体１０９ｂとしては、導電体１０８ａおよび導電体１０８ｂとして用いることができる導電体を用いればよい。 The conductor 109a and the conductor 109b function as wirings connected to either the source electrode or the drain electrode of the transistor 10, respectively. As the conductor 109a and the conductor 109b, a conductor that can be used as the conductor 108a and the conductor 108b may be used.
絶縁体１１２は、トランジスタ１０のゲート絶縁膜として機能することができる。絶縁体１１２は、絶縁体１０４と同様に過剰酸素を有する絶縁体としてもよい。このような絶縁体１１２を設けることにより、絶縁体１１２から絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６に酸素を供給することができる。 The insulator 112 can function as a gate insulating film of the transistor 10. The insulator 112 may be an insulator having excess oxygen like the insulator 104. By providing such an insulator 112, oxygen can be supplied from the insulator 112 to the insulator 106 a, the semiconductor 106 b, and the insulator 106.
絶縁体１１２としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁体を、単層で、または積層で用いればよい。例えば、絶縁体１１２としては、酸化アルミニウム、酸化マグネシウム、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウムまたは酸化タンタルを用いればよい。 As the insulator 112, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer. For example, as the insulator 112, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.
導電体１１４はトランジスタ１０のゲート電極として機能することができる。導電体１１４としては、導電体１０２と同様にして形成すればよい。 The conductor 114 can function as a gate electrode of the transistor 10. The conductor 114 may be formed in a manner similar to that of the conductor 102.
また、導電体１０２と同様に、導電体１１４は、導電体１１４の表面にシリコンおよび酸素を有する領域を有し、該領域の厚さは０．２ｎｍ以上２０ｎｍ以下であると好ましい。該領域は、シリコンと酸素が多く含まれた領域とすることができ、その場合、該領域は絶縁体として機能することができる。また、該領域が酸素のバリア層として機能することによって、導電体全体が酸化されるのを抑制することができる。 Similarly to the conductor 102, the conductor 114 has a region containing silicon and oxygen on the surface of the conductor 114, and the thickness of the region is preferably 0.2 nm to 20 nm. The region can be a region containing a large amount of silicon and oxygen, in which case the region can function as an insulator. Further, since the region functions as an oxygen barrier layer, oxidation of the entire conductor can be suppressed.
また、上記シリコンおよび酸素を有する領域は、導電体１１４を大気中に暴露させるだけで自然と形成できる場合もある。また、意図的に形成させることもできる。意図的に形成させる方法としては、例えば酸化性雰囲気で熱処理を行えばよい。また、酸素を有する雰囲気にてプラズマ処理を行ってもよい。プラズマ処理は、例えば周波数が２．４５ＧＨｚの電源を用いた高密度プラズマ処理を用いると好ましい。 In some cases, the region containing silicon and oxygen can be formed naturally only by exposing the conductor 114 to the atmosphere. It can also be formed intentionally. As a method for intentional formation, for example, heat treatment may be performed in an oxidizing atmosphere. Further, plasma treatment may be performed in an atmosphere containing oxygen. For the plasma treatment, for example, high-density plasma treatment using a power source having a frequency of 2.45 GHz is preferably used.
また、上記シリコンおよび酸素を有する領域を、導電体１１４の表面、特に側面に形成させることによって、該領域をサイドウォールとして機能させることができる。例えば、導電体１１４をマスクにして、イオン注入によりドーパントを添加する場合、導電体１１４の側面に形成させた領域をサイドウォールとして機能させることによって、ＬＤＤ（Ｌｉｇｈｔｌｙ　Ｄｏｐｅｄ　Ｄｒａｉｎ）領域やエクステンション領域を形成することができる。 In addition, when the region containing silicon and oxygen is formed on the surface of the conductor 114, particularly on the side surface, the region can function as a sidewall. For example, when a dopant is added by ion implantation using the conductor 114 as a mask, an LDD (Lightly Doped Drain) region or an extension region is formed by causing the region formed on the side surface of the conductor 114 to function as a sidewall. can do.
ここで、図１（Ｃ）に示すように、導電体１０２および導電体１１４による電界によって、半導体１０６ｂを電気的に取り囲むことができる（なお、導電体から生じる電界によって、半導体を電気的に取り囲むトランジスタの構造を、ｓｕｒｒｏｕｎｄｅｄ　ｃｈａｎｎｅｌ（ｓ−ｃｈａｎｎｅｌ）構造とよぶ。）。そのため、半導体１０６ｂの全体（上面、下面および側面）にチャネルが形成される。ｓ−ｃｈａｎｎｅｌ構造では、トランジスタのソースおよびドレイン間に大きな電流を流すことができ、導通時の電流（オン電流）を高くすることができる。 Here, as illustrated in FIG. 1C, the semiconductor 106b can be electrically surrounded by an electric field generated by the conductor 102 and the conductor 114 (note that the semiconductor is electrically surrounded by an electric field generated from the conductor. The structure of the transistor is called a surrounded channel (s-channel) structure.) Therefore, a channel is formed in the entire semiconductor 106b (upper surface, lower surface, and side surface). In the s-channel structure, a large current can flow between the source and the drain of the transistor, and a current (on-state current) at the time of conduction can be increased.
また、高いオン電流が得られるため、ｓ−ｃｈａｎｎｅｌ構造は、微細化されたトランジスタに適した構造といえる。トランジスタを微細化できるため、該トランジスタを有する半導体装置は、集積度の高い、高密度化された半導体装置とすることが可能となる。例えば、トランジスタは、チャネル長が好ましくは４０ｎｍ以下、さらに好ましくは３０ｎｍ以下、より好ましくは２０ｎｍ以下の領域を有し、かつ、トランジスタは、チャネル幅が好ましくは４０ｎｍ以下、さらに好ましくは３０ｎｍ以下、より好ましくは２０ｎｍ以下の領域を有する。 Further, since a high on-state current can be obtained, the s-channel structure can be said to be a structure suitable for a miniaturized transistor. Since a transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration. For example, the transistor has a region with a channel length of preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor has a channel width of preferably 40 nm or less, more preferably 30 nm or less, and more. Preferably, it has a region of 20 nm or less.
絶縁体１１６は、トランジスタ１０の保護絶縁膜として機能することができる。ここで絶縁体１１６の膜厚としては、例えば１ｎｍ以上、または２０ｎｍ以上とすることができる。また、絶縁体１１６は少なくとも一部が絶縁体１０４または絶縁体１１２の上面と接して形成されることが好ましい。 The insulator 116 can function as a protective insulating film of the transistor 10. Here, the thickness of the insulator 116 can be set to, for example, 1 nm or more, or 20 nm or more. The insulator 116 is preferably formed so that at least a part thereof is in contact with the top surface of the insulator 104 or the insulator 112.
絶縁体１１６としては、例えば、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁体を、単層で、または積層で用いればよい。絶縁体１１６は酸素、水素、水、アルカリ金属、アルカリ土類金属等をブロックする効果を有することが好ましい。このような絶縁体としては、例えば、窒化物絶縁膜を用いることができる。該窒化物絶縁膜としては、窒化シリコン、窒化酸化シリコン、窒化アルミニウム、窒化酸化アルミニウム等がある。なお、窒化物絶縁膜の代わりに、酸素、水素、水等のブロッキング効果を有する酸化物絶縁膜を設けてもよい。酸化物絶縁膜としては、酸化アルミニウム、酸化窒化アルミニウム、酸化ガリウム、酸化窒化ガリウム、酸化イットリウム、酸化窒化イットリウム、酸化ハフニウム、酸化窒化ハフニウム等がある。 As the insulator 116, for example, an insulator containing carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. A layer or a stack may be used. The insulator 116 preferably has an effect of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like. As such an insulator, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.
ここで絶縁体１１６の成膜は、スパッタリング法を用いて行うことが好ましく、酸素を含む雰囲気下でスパッタリング法を用いて行うことがより好ましい。スパッタリング法で絶縁体１１６の成膜をおこなうことにより、成膜と同時に絶縁体１０４または絶縁体１１２の表面（絶縁体１１６成膜後は絶縁体１０４または絶縁体１１２と絶縁体１１６の界面）近傍に酸素が添加される。 Here, the insulator 116 is preferably formed by a sputtering method, and more preferably by a sputtering method in an atmosphere containing oxygen. By depositing the insulator 116 by a sputtering method, near the surface of the insulator 104 or the insulator 112 at the same time as the film formation (the interface between the insulator 104 or the insulator 112 and the insulator 116 after the insulator 116 is formed) Is added with oxygen.
絶縁体１１６は、絶縁体１０４および絶縁体１１２より酸素を透過させにくい絶縁体であり、酸素をブロックする効果を有することが好ましい。このような絶縁体１１６を設けることにより、絶縁体１０４および絶縁体１１２から絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに酸素を供給する際に、当該酸素が絶縁体１１６の上方に外部放出されてしまうことを防ぐことができる。 The insulator 116 is an insulator that transmits less oxygen than the insulators 104 and 112, and preferably has an effect of blocking oxygen. By providing such an insulator 116, when oxygen is supplied from the insulator 104 and the insulator 112 to the insulator 106a, the semiconductor 106b, and the insulator 106c, the oxygen is released to the outside of the insulator 116. Can be prevented.
なお、酸化アルミニウムは、水素、水分などの不純物、および酸素の両方に対して膜を透過させない遮断効果が高いので絶縁体１１６に適用するのに好ましい。 Note that aluminum oxide is preferable for application to the insulator 116 because it has a high blocking effect of preventing permeation of both hydrogen, moisture and other impurities, and oxygen.
また、絶縁体１１６は、上述の絶縁体１０６ａまたは絶縁体１０６ｃとして用いることができる酸化物を用いることもできる。これらの酸化物はスパッタリング法を用いて比較的容易に成膜できるため、絶縁体１０４および絶縁体１１２に効果的に酸素を添加することができる。このような絶縁体１１６としては、Ｉｎを含む酸化絶縁物を用いることが好ましく、例えば、Ｉｎ−Ａｌ酸化物、Ｉｎ−Ｇａ酸化物、Ｉｎ−Ｇａ−Ｚｎ酸化物を用いればよい。Ｉｎを含む酸化絶縁物はスパッタリング法で成膜する際に発生するパーティクル数が少ないので、絶縁体１１６として用いるのに好適である。 Alternatively, the insulator 116 can be formed using an oxide that can be used for the insulator 106a or the insulator 106c. Since these oxides can be formed relatively easily by a sputtering method, oxygen can be effectively added to the insulator 104 and the insulator 112. As such an insulator 116, an oxide insulator containing In is preferably used. For example, an In—Al oxide, an In—Ga oxide, or an In—Ga—Zn oxide may be used. An oxide insulator containing In is suitable for use as the insulator 116 because the number of particles generated when a film is formed by a sputtering method is small.
絶縁体１１８は、層間絶縁膜として機能する。絶縁体１１８としては、絶縁体１０５などと同様にして形成すればよい。 The insulator 118 functions as an interlayer insulating film. The insulator 118 may be formed in a manner similar to that of the insulator 105 or the like.
以上のような構成とすることにより、ゲート電極に用いる導電体のイオン突き抜けを抑制し、良好な電気特性を有するトランジスタを提供することができる。また、安定した電気特性を有するトランジスタを提供することができる。または、非導通時のリーク電流の小さいトランジスタを提供することができる。または、高い周波数特性を有するトランジスタを提供することができる。または、ノーマリーオフの電気特性を有するトランジスタを提供することができる。または、サブスレッショルドスイング値の小さいトランジスタを提供することができる。または、信頼性の高いトランジスタを提供することができる。 With the above structure, a transistor having favorable electrical characteristics can be provided by suppressing ion penetration of the conductor used for the gate electrode. In addition, a transistor having stable electrical characteristics can be provided. Alternatively, a transistor with low leakage current when not conducting can be provided. Alternatively, a transistor having high frequency characteristics can be provided. Alternatively, a transistor having normally-off electrical characteristics can be provided. Alternatively, a transistor with a small subthreshold swing value can be provided. Alternatively, a highly reliable transistor can be provided.
＜トランジスタ変形例＞
以下、トランジスタ１０の変形例について図７および図８を用いて説明する。なお、図７および図８は、図１（Ｂ）および図１（Ｃ）と同様に、トランジスタのチャネル長方向の断面図とトランジスタのチャネル幅方向の断面図になる。 <Transistor modification>
Hereinafter, modified examples of the transistor 10 will be described with reference to FIGS. 7 and 8 are a cross-sectional view in the channel length direction of the transistor and a cross-sectional view in the channel width direction of the transistor, as in FIGS. 1B and 1C.
図７（Ａ）および図７（Ｂ）に示すトランジスタ１１は、導電体１０２を設けない点において、トランジスタ１０とは異なる。 A transistor 11 illustrated in FIGS. 7A and 7B is different from the transistor 10 in that the conductor 102 is not provided.
図７（Ｃ）および図７（Ｄ）に示すトランジスタ１２は、絶縁体１４０および絶縁体１４２を有する点において、トランジスタ１０とは異なる。導電体１０２上に絶縁体１４０が形成され、絶縁体１４０上に絶縁体１４２が形成され、絶縁体１４２上に絶縁体１０４が形成されている。絶縁体１４０は、絶縁体１０４と同様の絶縁体を用いることができる。 A transistor 12 illustrated in FIGS. 7C and 7D is different from the transistor 10 in that an insulator 140 and an insulator 142 are included. An insulator 140 is formed over the conductor 102, an insulator 142 is formed over the insulator 140, and the insulator 104 is formed over the insulator 142. As the insulator 140, an insulator similar to the insulator 104 can be used.
絶縁体１４２は、酸素をブロックする機能を有することが好ましい。このような絶縁体１４２を設けることにより絶縁体１０４から導電体１０２が酸素を引き抜くことを防ぐことができる。これにより、絶縁体１０４から絶縁体１０６ａ、半導体１０６ｂ、絶縁体１０６ｃに効果的に酸素を供給することができる。 The insulator 142 preferably has a function of blocking oxygen. By providing such an insulator 142, the conductor 102 can be prevented from extracting oxygen from the insulator 104. Accordingly, oxygen can be effectively supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c.
絶縁体１４２としては、ホウ素、アルミニウム、シリコン、スカンジウム、チタン、ガリウム、イットリウム、ジルコニウム、インジウム、ランタン、セリウム、ネオジム、ハフニウムまたはタリウムを有する酸化物または窒化物を有していてもよい。好ましくは、酸化ハフニウムまたは酸化アルミニウムを用いる。 The insulator 142 may include an oxide or nitride containing boron, aluminum, silicon, scandium, titanium, gallium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, hafnium, or thallium. Preferably, hafnium oxide or aluminum oxide is used.
なお、絶縁体１４０、絶縁体１４２および絶縁体１０４において、絶縁体１４２が電子捕獲領域を有すると好ましい。絶縁体１４０および絶縁体１０４が電子の放出を抑制する機能を有するとき、絶縁体１４２に捕獲された電子は、負の固定電荷のように振舞うことがある。このように、絶縁体１４２に捕獲させる固定電荷の量を制御することによって、トランジスタの閾値電圧を制御することができる。 Note that in the insulator 140, the insulator 142, and the insulator 104, the insulator 142 preferably includes an electron-trapping region. When the insulator 140 and the insulator 104 have a function of suppressing emission of electrons, the electrons trapped in the insulator 142 may behave like a negative fixed charge. In this manner, the threshold voltage of the transistor can be controlled by controlling the amount of fixed charges captured by the insulator 142.
図７（Ｅ）および図７（Ｆ）に示すトランジスタ１３は、導電体１１４の形成方法が、トランジスタ１０とは異なる。トランジスタ１３の導電体１１４は、絶縁体１１８に設けられた開口部を埋めるように形成されている。 The transistor 13 illustrated in FIGS. 7E and 7F is different from the transistor 10 in the method for forming the conductor 114. The conductor 114 of the transistor 13 is formed so as to fill an opening provided in the insulator 118.
図８（Ａ）および図８（Ｂ）に示すトランジスタ１４は、導電体１１４の側面に絶縁体１１５が設けられている点において、トランジスタ１０とは異なる。絶縁体１１５は、サイドウォールとして機能することができる。また、絶縁体１１５は、絶縁体１０４などと同様にして形成すればよい。 A transistor 14 illustrated in FIGS. 8A and 8B is different from the transistor 10 in that an insulator 115 is provided on a side surface of the conductor 114. The insulator 115 can function as a sidewall. The insulator 115 may be formed in a manner similar to that of the insulator 104 or the like.
絶縁体１１５を設けることによって、導電体１１４をマスクにして、イオン注入によりドーパントを添加する場合、導電体１１４の側面に形成させた領域をサイドウォールとして機能させることによって、ＬＤＤ（Ｌｉｇｈｔｌｙ　Ｄｏｐｅｄ　Ｄｒａｉｎ）領域やエクステンション領域を形成することができる。なお、領域１２６ｄおよび領域１２６ｅは、ＬＤＤ領域として機能することができる。 By providing the insulator 115, when the dopant is added by ion implantation using the conductor 114 as a mask, the region formed on the side surface of the conductor 114 functions as a sidewall, thereby allowing LDD (Lightly Doped Drain). Regions and extension regions can be formed. Note that the region 126d and the region 126e can function as LDD regions.
図８（Ｃ）に、図８（Ａ）に示すトランジスタ１４の導電体１１４近傍の拡大図を示す。図８（Ｃ）に示すように、本実施の形態に示すトランジスタ１４の、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃは、領域１２６ａ、領域１２６ｂ、領域１２６ｃ、領域１２６ｄおよび領域１２６ｅが形成されている。領域１２６ｂ、領域１２６ｃ、領域１２６ｄおよび領域１２６ｅは、領域１２６ａと比較してドーパントの濃度が高く、低抵抗化されている。また、領域１２６ｂおよび領域１２６ｃは、領域１２６ｄおよび領域１２６ｅと比較してドーパントの濃度が高く、電気抵抗値も低い。 FIG. 8C illustrates an enlarged view of the vicinity of the conductor 114 of the transistor 14 illustrated in FIG. As shown in FIG. 8C, the insulator 106a, the semiconductor 106b, and the insulator 106c of the transistor 14 described in this embodiment include a region 126a, a region 126b, a region 126c, a region 126d, and a region 126e. Yes. The region 126b, the region 126c, the region 126d, and the region 126e have a higher dopant concentration and lower resistance than the region 126a. In addition, the region 126b and the region 126c have a higher dopant concentration and a lower electrical resistance value than the region 126d and the region 126e.
図８（Ｃ）に示すように、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃにおいて、領域１２６ａは導電体１１４と概ね重なる領域である。領域１２６ｄおよび領域１２６ｅにおいては、絶縁体１１５と概ね重なる領域である。 As shown in FIG. 8C, in the insulator 106a, the semiconductor 106b, and the insulator 106c, the region 126a is a region that substantially overlaps with the conductor 114. The regions 126d and 126e are regions that substantially overlap with the insulator 115.
なお、領域１２６ｂ、領域１２６ｃ、領域１２６ｄおよび領域１２６ｅは、イオン注入またはイオンドーピングなどを用いてドーパントを添加することによって形成すればよい。 Note that the region 126b, the region 126c, the region 126d, and the region 126e may be formed by adding a dopant by ion implantation, ion doping, or the like.
また上述したように、導電体１１４は、導電体１１４の表面にシリコンおよび酸素を有する領域を有し、該領域は、シリコンと酸素が多く含まれた領域とすることができる。例えば、図８（Ｄ）に示すように、導電体１１４の表面にシリコンおよび酸素を有する領域１４４を設けた構成とすることができる。なお、シリコンおよび酸素を有する領域１４４は絶縁体として機能することができる。 In addition, as described above, the conductor 114 has a region containing silicon and oxygen on the surface of the conductor 114, and the region can be a region containing a large amount of silicon and oxygen. For example, as illustrated in FIG. 8D, a region 144 having silicon and oxygen can be provided on the surface of the conductor 114. Note that the region 144 including silicon and oxygen can function as an insulator.
また、シリコンおよび酸素を有する領域１４４は、導電体１１４を大気中に暴露させるだけで自然と形成できる場合もある。また、意図的に形成させることもできる。意図的に形成させる方法としては、例えば酸化性雰囲気で熱処理を行えばよい。また、酸素を有する雰囲気にてプラズマ処理を行ってもよい。プラズマ処理は、例えば周波数が２．４５ＧＨｚの電源を用いた高密度プラズマ処理を用いると好ましい。 In some cases, the region 144 having silicon and oxygen can be formed naturally only by exposing the conductor 114 to the atmosphere. It can also be formed intentionally. As a method for intentional formation, for example, heat treatment may be performed in an oxidizing atmosphere. Further, plasma treatment may be performed in an atmosphere containing oxygen. For the plasma treatment, for example, high-density plasma treatment using a power source having a frequency of 2.45 GHz is preferably used.
以上のようにして、シリコンおよび酸素を有する領域１４４を、導電体１１４の表面、特に側面に形成させることによって、該領域をサイドウォールとして機能させることができる。 As described above, by forming the region 144 containing silicon and oxygen on the surface of the conductor 114, particularly on the side surface, the region can function as a sidewall.
また本実施の形態では、トランジスタのゲート電極に、タングステンと、シリコン、炭素、ゲルマニウム、スズ、アルミニウムまたはニッケルから選ばれた一以上の元素と、を有する領域を有する導電体を用いる構成について示したが、これに限られない。例えば、ＭＩＭ（Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｍｅｔａｌ）などの容量素子における電極に、タングステンと、シリコン、炭素、ゲルマニウム、スズ、アルミニウムまたはニッケルから選ばれた一以上の元素と、を有する領域を有する導電体を用いてもよい。またその際、該導電体の表面にシリコンおよび酸素を有する領域を有し、絶縁体と機能することができる該領域を、容量素子の誘電体として使用する構成としてもよい。 In this embodiment, a structure in which a conductor including a region including tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, or nickel is used for the gate electrode of the transistor is described. However, it is not limited to this. For example, a conductor having a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, or nickel is used as an electrode in a capacitor element such as MIM (Metal-Insulator-Metal). It may be used. At that time, a region having silicon and oxygen on the surface of the conductor and functioning as an insulator may be used as a dielectric of the capacitor.
本実施の形態により、ゲート電極に用いる導電体のイオン突き抜けを抑制し、良好な電気特性を有するトランジスタを提供することができる。 According to this embodiment, a transistor having favorable electric characteristics can be provided by suppressing ion penetration of a conductor used for a gate electrode.
以上、本実施の形態で示す構成、方法は、他の実施の形態で示す構成、方法と適宜組み合わせて用いることができる。 The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.
（実施の形態２）
本実施の形態では、本発明の一態様に係る半導体装置の作製方法について、図９および図１０を用いて説明する。 (Embodiment 2)
In this embodiment, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.
＜トランジスタの作製方法＞
以下において、図１に示すトランジスタ１０の作製方法について説明する。 <Method for Manufacturing Transistor>
Hereinafter, a method for manufacturing the transistor 10 illustrated in FIGS.
まずは、基板１００を準備する。基板１００に用いる基板としては上述の基板を用いればよい。 First, the substrate 100 is prepared. As the substrate used for the substrate 100, the above-described substrate may be used.
次に、絶縁体１０１を成膜する。絶縁体１０１としては上述の絶縁体を用いればよい。 Next, the insulator 101 is formed. As the insulator 101, the above insulator may be used.
絶縁体１０１の成膜は、スパッタリング法、化学気相成長（ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、分子線エピタキシー（ＭＢＥ：Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法またはパルスレーザ堆積（ＰＬＤ：Ｐｕｌｓｅｄ　Ｌａｓｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、原子層堆積（ＡＬＤ：Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法などを用いて行うことができる。 The insulator 101 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method or a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, an atomic layer. The deposition can be performed using an ALD (Atomic Layer Deposition) method or the like.
なお、ＣＶＤ法は、プラズマを利用するプラズマＣＶＤ（ＰＥＣＶＤ：Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＣＶＤ）法、熱を利用する熱ＣＶＤ（ＴＣＶＤ：Ｔｈｅｒｍａｌ　ＣＶＤ）法、光を利用する光ＣＶＤ（Ｐｈｏｔｏ　ＣＶＤ）法などに分類できる。さらに用いる原料ガスによって金属ＣＶＤ（ＭＣＶＤ：Ｍｅｔａｌ　ＣＶＤ）法、有機金属ＣＶＤ（ＭＯＣＶＤ：Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　ＣＶＤ）法に分けることができる。 In addition, the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.
ＰＥＣＶＤ法は、比較的低温で高品質の膜が得られる。また、ＴＣＶＤ法は、プラズマを用いないため、被処理物へのプラズマダメージを小さくすることが可能な成膜方法である。例えば、半導体装置に含まれる配線、電極、素子（トランジスタ、容量素子など）などは、プラズマから電荷を受け取ることでチャージアップする場合がある。このとき、蓄積した電荷によって、半導体装置に含まれる配線、電極、素子などが破壊される場合がある。一方、プラズマを用いないＴＣＶＤ法の場合、こういったプラズマダメージが生じないため、半導体装置の歩留まりを高くすることができる。また、ＴＣＶＤ法では、成膜中のプラズマダメージが生じないため、欠陥の少ない膜が得られる。 The PECVD method can obtain a high quality film at a relatively low temperature. The TCVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a TCVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the TCVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.
また、ＡＬＤ法も、被処理物へのプラズマダメージを小さくすることが可能な成膜方法である。よって、ＡＬＤ法を用いることにより、欠陥の少ない膜が得られる。 The ALD method is also a film forming method that can reduce plasma damage to an object to be processed. Therefore, a film with few defects can be obtained by using the ALD method.
ＣＶＤ法およびＡＬＤ法は、ターゲットなどから放出される粒子が堆積する成膜方法とは異なり、被処理物の表面における反応により膜が形成される成膜方法である。したがって、被処理物の形状の影響を受けにくく、良好な段差被覆性を有する成膜方法である。特に、ＡＬＤ法は、優れた段差被覆性と、優れた厚さの均一性を有するため、アスペクト比の高い開口部の表面を被覆する場合などに好適である。またこれにより、成膜した膜にピンホールなどが形成されにくくなる。ただし、ＡＬＤ法は、比較的成膜速度が遅いため、成膜速度の速いＣＶＤ法などの他の成膜方法と組み合わせて用いることが好ましい場合もある。 The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. This also makes it difficult to form pinholes or the like in the formed film. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
ＣＶＤ法およびＡＬＤ法は、原料ガスの流量比によって、得られる膜の組成を制御することができる。例えば、ＣＶＤ法およびＡＬＤ法では、原料ガスの流量比によって、任意の組成の膜を成膜することができる。また、例えば、ＣＶＤ法およびＡＬＤ法では、成膜しながら原料ガスの流量比を変化させることによって、組成が連続的に変化した膜を成膜することができる。原料ガスの流量比を変化させながら成膜する場合、複数の成膜室を用いて成膜する場合と比べて、搬送や圧力調整に掛かる時間の分、成膜に掛かる時間を短くすることができる。したがって、半導体装置の生産性を高めることができる場合がある。 In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the semiconductor device may be increased.
従来のＣＶＤ法を利用した成膜装置は、成膜の際、反応のための原料ガスの１種または複数種がチャンバーに同時に供給される。ＡＬＤ法を利用した成膜装置は、反応のための原料ガス（プリカーサとも呼ぶ）と反応剤として機能するガス（リアクタントとも呼ぶ）を交互にチャンバーに導入し、これらのガスの導入を繰り返すことで成膜を行う。なお、導入ガスの切り替えは、例えば、それぞれのスイッチングバルブ（高速バルブとも呼ぶ）を切り替えて行うことができる。 In a film forming apparatus using a conventional CVD method, at the time of film formation, one or more kinds of source gases for reaction are simultaneously supplied to a chamber. A film forming apparatus using the ALD method alternately introduces a source gas for reaction (also referred to as a precursor) and a gas functioning as a reactant (also referred to as a reactant) into the chamber, and repeatedly introduces these gases. Film formation is performed. The introduction gas can be switched by switching each switching valve (also referred to as a high-speed valve), for example.
例えば、以下のような手順で成膜を行う。まず、プリカーサをチャンバーに導入し、基板表面にプリカーサを吸着させる（第１ステップ）。ここで、プリカーサが基板表面に吸着することにより、表面化学反応の自己停止機構が作用し、基板上のプリカーサの層の上にさらにプリカーサが吸着することはない。なお、表面化学反応の自己停止機構が作用する基板温度の適正範囲をＡＬＤ　Ｗｉｎｄｏｗとも呼ぶ。ＡＬＤ　Ｗｉｎｄｏｗは、プリカーサの温度特性、蒸気圧、分解温度などによって決まる。次に、不活性ガス（アルゴン、或いは窒素など）などをチャンバーに導入し、余剰なプリカーサや反応生成物などをチャンバーから排出する（第２ステップ）。また、不活性ガスを導入する代わりに真空排気によって、余剰なプリカーサや反応生成物などをチャンバーから排出してもよい。次に、リアクタント（例えば、酸化剤（Ｈ２Ｏ、Ｏ３など））をチャンバーに導入し、基板表面吸着したプリカーサと反応させて、膜の構成分子を基板に吸着させたままプリカーサの一部を除去する（第３ステップ）。次に、不活性ガスの導入または真空排気によって、余剰なリアクタントや反応生成物などをチャンバーから排出する（第４ステップ）。 For example, film formation is performed in the following procedure. First, a precursor is introduced into the chamber, and the precursor is adsorbed on the substrate surface (first step). Here, when the precursor is adsorbed on the substrate surface, a self-stopping mechanism of the surface chemical reaction acts, and the precursor is not further adsorbed on the precursor layer on the substrate. The appropriate range of the substrate temperature at which the surface chemical reaction self-stopping mechanism operates is also referred to as ALD Window. The ALD window is determined by temperature characteristics of the precursor, vapor pressure, decomposition temperature, and the like. Next, an inert gas (such as argon or nitrogen) is introduced into the chamber, and excess precursors and reaction products are discharged from the chamber (second step). Further, surplus precursors and reaction products may be discharged from the chamber by evacuation instead of introducing the inert gas. Next, a reactant (for example, an oxidant (H 2 O, O 3, etc.)) is introduced into the chamber and reacted with the precursor adsorbed on the substrate surface, so that a part of the precursor remains adsorbed on the substrate. Is removed (third step). Next, surplus reactants and reaction products are discharged from the chamber by introducing an inert gas or evacuating (fourth step).
このようにして、基板表面に第１の単一層を成膜することができ、第１乃至第４ステップを再び行うことで、第１の単一層の上に第２の単一層を積層することができる。第１乃至第４ステップを、ガス導入を制御しつつ、膜が所望の厚さになるまで複数回繰り返すことで、段差被覆性に優れた薄膜を形成することができる。薄膜の厚さは、繰り返す回数によって調節することができるため、精密な膜厚調節が可能であり、微細なトランジスタを作製する場合に適している。 In this way, the first single layer can be formed on the substrate surface, and the second single layer is laminated on the first single layer by performing the first to fourth steps again. Can do. By repeating the first to fourth steps a plurality of times while controlling the gas introduction until the film has a desired thickness, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions, precise film thickness adjustment is possible, which is suitable for manufacturing a fine transistor.
ＡＬＤ法は、熱エネルギーを用いてプリカーサを反応させて行う成膜方法である。さらに、上記のリアクタントの反応において、プラズマを用いてリアクタントをラジカル状態として処理を行うＡＬＤ法をプラズマＡＬＤ法と呼ぶことがある。またこれに対して、プリカーサおよびリアクタントの反応を熱エネルギーで行うＡＬＤ法を熱ＡＬＤ法と呼ぶことがある。 The ALD method is a film forming method performed by reacting a precursor using thermal energy. Furthermore, in the above-described reactant reaction, the ALD method in which the reactant is treated in a radical state using plasma may be referred to as a plasma ALD method. On the other hand, the ALD method in which the reaction between the precursor and the reactant is performed with thermal energy may be referred to as a thermal ALD method.
ＡＬＤ法は、極めて薄い膜を均一な膜厚で成膜することができる。また、凹凸を有する面に対しても、表面被覆率が高い。 The ALD method can form a very thin film with a uniform film thickness. In addition, the surface coverage is high even on a surface having irregularities.
また、プラズマＡＬＤ法により成膜することで、熱ＡＬＤ法に比べてさらに低温での成膜が可能となる。プラズマＡＬＤ法は、例えば、１００℃以下でも成膜速度を低下させずに成膜することができる。また、プラズマＡＬＤ法では、酸化剤だけでなく、窒素ガスなど多くのリアクタントを用いることができるので、酸化物だけでなく、窒化物、フッ化物、金属など多くの種類の膜を成膜することができる。 In addition, the film formation by the plasma ALD method enables the film formation at a lower temperature than the thermal ALD method. In the plasma ALD method, for example, a film can be formed at a temperature of 100 ° C. or lower without reducing the film formation rate. In addition, in the plasma ALD method, not only an oxidizing agent but also many reactants such as nitrogen gas can be used, so that not only oxides but also many types of films such as nitrides, fluorides, and metals can be formed. Can do.
また、プラズマＡＬＤ法を行う場合には、ＩＣＰ（Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）などのように基板から離れた状態でプラズマを発生させることもできる。このようにプラズマを発生させることにより、プラズマダメージを抑えることができる。 In the case of performing the plasma ALD method, plasma can be generated in a state separated from the substrate, such as ICP (Inductively Coupled Plasma). By generating plasma in this way, plasma damage can be suppressed.
次に、絶縁体１０３を成膜する。絶縁体１０３としては上述の絶縁体を用いればよい。絶縁体１０３の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, the insulator 103 is formed. The insulator described above may be used as the insulator 103. The insulator 103 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
次に、絶縁体１０３上にレジストなどを形成し、絶縁体１０３に開口部を形成する。なお、単にレジストを形成するという場合、レジストの下に反射防止層を形成する場合も含まれる。 Next, a resist or the like is formed over the insulator 103, and an opening is formed in the insulator 103. Note that the case of simply forming a resist includes the case of forming an antireflection layer under the resist.
レジストは、対象物をエッチングなどによって加工した後で除去する。レジストの除去には、プラズマ処理または／およびウェットエッチングを用いる。なお、プラズマ処理としては、プラズマアッシングが好適である。レジストなどの除去が不十分な場合、０．００１重量％以上１重量％以下の濃度のフッ化水素酸または／およびオゾン水などによって取り残したレジストなどを除去しても構わない。 The resist is removed after the object is processed by etching or the like. For the removal of the resist, plasma treatment and / or wet etching is used. Note that plasma ashing is preferable as the plasma treatment. When the removal of the resist or the like is insufficient, the remaining resist or the like may be removed with hydrofluoric acid or / and ozone water having a concentration of 0.001 wt% or more and 1 wt% or less.
次に、導電体１０２となる導電体を成膜する。導電体１０２となる導電体としては、上述の導電体を用いることができる。導電体１０２となる導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, a conductor to be the conductor 102 is formed. As the conductor to be the conductor 102, the above-described conductor can be used. The conductor to be the conductor 102 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
次に、ＣＭＰ処理を行って、絶縁体１０３上の導電体１０２となる導電体を除去する。その結果、絶縁体１０３に形成された開口部の中のみに、導電体１０２が残存する。 Next, a CMP process is performed to remove the conductor to be the conductor 102 on the insulator 103. As a result, the conductor 102 remains only in the opening formed in the insulator 103.
次に、絶縁体１０４を成膜する（図９（Ａ）および図９（Ｂ）参照。）。絶縁体１０４としては上述の絶縁体を用いればよい。絶縁体１０４の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, the insulator 104 is formed (see FIGS. 9A and 9B). As the insulator 104, the above insulator may be used. The insulator 104 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
また、後で形成する半導体１０６ｂの上面又は下面は平坦性が高いことが好ましい。このため、絶縁体１０４の上面にＣＭＰ法などの平坦化処理を行って平坦性の向上を図ってもよい。 In addition, the upper surface or the lower surface of the semiconductor 106b to be formed later preferably has high flatness. Therefore, planarity may be improved by performing a planarization process such as a CMP method on the upper surface of the insulator 104.
次に、後の工程で絶縁体１０６ａとなる絶縁体を成膜する。当該絶縁体としては上述の絶縁体１０６ａとして用いることができる絶縁体、半導体又は導電体を用いればよい。当該絶縁体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, an insulator to be the insulator 106a is formed in a later step. As the insulator, an insulator, a semiconductor, or a conductor that can be used as the above-described insulator 106a may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
また、絶縁体１０６ａとなる絶縁体の成膜は、スパッタリング法を用いて行うことが好ましく、酸素を含む雰囲気下でスパッタリング法を用いて行うことがより好ましい。また、スパッタリング法を用いる際に、平行平板型のスパッタリング装置を用いてもよいし、対向ターゲット式のスパッタリング装置を用いてもよい。後述するが、対向ターゲット式のスパッタリング装置を用いた成膜では、被形成面へのダメージが小さくできるため、結晶性の高い膜を得やすい。よって後述するＣＡＡＣ−ＯＳの成膜には、対向ターゲット式のスパッタリング装置を用いることが好ましい場合がある。 The insulator to be the insulator 106a is preferably formed by a sputtering method, and more preferably by a sputtering method in an atmosphere containing oxygen. In addition, when using the sputtering method, a parallel plate type sputtering apparatus may be used, or a counter target type sputtering apparatus may be used. As will be described later, in the film formation using the facing target sputtering apparatus, damage to the formation surface can be reduced, so that a film with high crystallinity is easily obtained. Therefore, in some cases, it is preferable to use an opposing target sputtering apparatus for formation of a CAAC-OS to be described later.
スパッタリング法で絶縁体１０６ａとなる絶縁体の成膜を行うことにより、成膜と同時に絶縁体１０４の表面（絶縁体１０６ａ形成後は絶縁体１０６ａと絶縁体１０４の界面）近傍に酸素が添加されることがある。ここで、酸素は、例えば、酸素ラジカルとして絶縁体１０４に添加されるが、酸素が添加されるときの状態はこれに限定されない。当該酸素は、酸素原子、又は酸素イオンなどの状態で絶縁体１０４に添加されてもよい。このように酸素を絶縁体１０４に添加することにより、絶縁体１０４に過剰酸素を含ませることができる。 By forming an insulator to be the insulator 106a by a sputtering method, oxygen is added to the vicinity of the surface of the insulator 104 (the interface between the insulator 106a and the insulator 104 after the insulator 106a is formed) simultaneously with the film formation. Sometimes. Here, for example, oxygen is added to the insulator 104 as oxygen radicals; however, a state where oxygen is added is not limited thereto. The oxygen may be added to the insulator 104 in a state of oxygen atoms or oxygen ions. By adding oxygen to the insulator 104 in this manner, the insulator 104 can contain excess oxygen.
また、絶縁体１０４と絶縁体１０６ａとなる絶縁体の界面近傍の領域に混合領域が形成されることがある。混合領域では、絶縁体１０４を構成する成分と絶縁体１０６ａとなる絶縁体を構成する成分が含まれている。 In addition, a mixed region may be formed in a region near the interface between the insulator 104 and the insulator 106a. In the mixed region, a component constituting the insulator 104 and a component constituting the insulator to be the insulator 106a are included.
次に、後の工程で半導体１０６ｂとなる半導体を成膜する。当該半導体としては上述の半導体１０６ｂとして用いることができる半導体を用いればよい。当該半導体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。なお、絶縁体１０６ａとなる絶縁体の成膜と、半導体１０６ｂとなる半導体の成膜と、を大気に暴露することなく連続で行うことで、膜中および界面への不純物の混入を低減することができる。 Next, a semiconductor to be the semiconductor 106b is formed in a later step. As the semiconductor, a semiconductor that can be used as the semiconductor 106b described above may be used. The semiconductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the formation of the insulator to be the insulator 106a and the formation of the semiconductor to be the semiconductor 106b are continuously performed without being exposed to the air, so that contamination of impurities into the film and the interface can be reduced. Can do.
また、成膜ガスはアルゴンなどの希ガス（ほかにヘリウム、ネオン、クリプトン、キセノンなど）と酸素との混合ガスを用いると好ましい。例えば、全体に占める酸素の割合を５０体積％未満、好ましくは３３体積％以下、さらに好ましくは２０体積％以下、より好ましくは１５体積％以下とすればよい。 Further, it is preferable to use a mixed gas of a rare gas such as argon (in addition, helium, neon, krypton, xenon, etc.) and oxygen as the film forming gas. For example, the proportion of oxygen in the whole may be less than 50% by volume, preferably 33% by volume or less, more preferably 20% by volume or less, more preferably 15% by volume or less.
また、スパッタリング法を用いて成膜する場合、基板温度を高くしても構わない。基板温度を高くすることで、基板上面におけるスパッタ粒子のマイグレーションを助長させることができる。したがって、より密度が高く、より結晶性の高い酸化物を成膜することができる。なお、基板の温度は、例えば、１００℃以上４５０℃以下、好ましくは１５０℃以上４００℃以下、さらに好ましくは１７０℃以上３５０℃以下とすればよい。 In the case of forming a film using a sputtering method, the substrate temperature may be increased. By increasing the substrate temperature, the migration of sputtered particles on the upper surface of the substrate can be promoted. Therefore, an oxide with higher density and higher crystallinity can be formed. Note that the substrate temperature may be, for example, 100 ° C. or higher and 450 ° C. or lower, preferably 150 ° C. or higher and 400 ° C. or lower, more preferably 170 ° C. or higher and 350 ° C. or lower.
次に、加熱処理を行うことが好ましい。加熱処理を行うことで、後の工程で形成する絶縁体１０６ａおよび半導体１０６ｂの水素濃度を低減させることができる場合がある。また、後の工程で形成する絶縁体１０６ａおよび半導体１０６ｂの酸素欠損を低減させることができる場合がある。加熱処理は、２５０℃以上６５０℃以下、好ましくは４５０℃以上６００℃以下、さらに好ましくは５２０℃以上５７０℃以下で行えばよい。加熱処理は、不活性ガス雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上もしくは１０％以上含む雰囲気で行う。加熱処理は減圧状態で行ってもよい。または、加熱処理は、不活性ガス雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上または１０％以上含む雰囲気で加熱処理を行ってもよい。加熱処理によって、後の工程で形成する絶縁体１０６ａおよび半導体１０６ｂの結晶性を高めることや、水素や水などの不純物を除去することなどができる。加熱処理は、ランプ加熱によるＲＴＡ装置を用いることもできる。 Next, it is preferable to perform a heat treatment. By performing heat treatment, the hydrogen concentration in the insulator 106a and the semiconductor 106b which are formed in a later step may be reduced in some cases. In some cases, oxygen vacancies in the insulator 106a and the semiconductor 106b formed in a later step can be reduced. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By the heat treatment, crystallinity of the insulator 106a and the semiconductor 106b formed in a later step can be increased, impurities such as hydrogen and water can be removed, and the like. For the heat treatment, an RTA apparatus using lamp heating can also be used.
当該加熱処理により、絶縁体１０４から絶縁体１０６ａとなる絶縁体、および半導体１０６ｂとなる半導体に酸素を供給することができる。絶縁体１０４に対して加熱処理を行うことにより、極めて容易に酸素を絶縁体１０６ａとなる絶縁体、および半導体１０６ｂとなる半導体に供給することができる。 Through the heat treatment, oxygen can be supplied from the insulator 104 to the insulator to be the insulator 106a and the semiconductor to be the semiconductor 106b. By performing heat treatment on the insulator 104, oxygen can be supplied to the insulator to be the insulator 106a and the semiconductor to be the semiconductor 106b very easily.
ここで、絶縁体１０１は、酸素をブロックするバリア膜として機能する。絶縁体１０１が絶縁体１０４の下に設けられていることにより、絶縁体１０４中に拡散した酸素が絶縁体１０４より下層に拡散することを防ぐことができる。 Here, the insulator 101 functions as a barrier film that blocks oxygen. By providing the insulator 101 below the insulator 104, oxygen diffused in the insulator 104 can be prevented from diffusing below the insulator 104.
このように絶縁体１０６ａとなる絶縁体、および半導体１０６ｂとなる半導体に酸素を供給し、酸素欠損を低減させることにより、欠陥準位密度の低い、高純度真性または実質的に高純度真性な酸化物半導体とすることができる。 In this way, oxygen is supplied to the insulator to be the insulator 106a and the semiconductor to be the semiconductor 106b to reduce oxygen vacancies, so that high-purity intrinsic or substantially high-purity intrinsic oxidation with a low defect level density is achieved. It can be a physical semiconductor.
また、高密度プラズマ処理などを行ってもよい。高密度プラズマは、マイクロ波を用いて生成すればよい。高密度プラズマ処理では、例えば、酸素、亜酸化窒素などの酸化性ガスを用いればよい。または、酸化性ガスと、Ｈｅ、Ａｒ、Ｋｒ、Ｘｅなどの希ガスと、の混合ガスを用いてもよい。高密度プラズマ処理において、基板にバイアスを印加してもよい。これにより、プラズマ中の酸素イオンなどを基板側に引き込むことができる。高密度プラズマ処理は基板を加熱しながら行ってもよい。例えば、上記加熱処理の代わりに高密度プラズマ処理を行う場合、上記加熱処理の温度より低温で同様の効果を得ることができる。高密度プラズマ処理は、絶縁体１０６ａとなる絶縁体の成膜前に行ってもよいし、絶縁体１１２の成膜後に行ってもよいし、絶縁体１１６の成膜後などに行ってもよい。 Further, high-density plasma treatment or the like may be performed. The high density plasma may be generated using microwaves. In the high-density plasma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe may be used. In high-density plasma processing, a bias may be applied to the substrate. Thereby, oxygen ions or the like in the plasma can be drawn to the substrate side. The high density plasma treatment may be performed while heating the substrate. For example, when high-density plasma treatment is performed instead of the heat treatment, the same effect can be obtained at a temperature lower than the temperature of the heat treatment. The high density plasma treatment may be performed before the formation of the insulator to be the insulator 106a, may be performed after the insulator 112 is formed, or may be performed after the insulator 116 is formed. .
次に、半導体１０６ｂとなる半導体上にレジストなどを形成し、該レジストなどを用いて加工し、絶縁体１０６ａおよび半導体１０６ｂを形成する。なお、図９（Ｃ）および図９（Ｄ）に示すように、半導体１０６ｂの形成時に、絶縁体１０４の露出した表面が除去される場合がある。 Next, a resist or the like is formed over the semiconductor to be the semiconductor 106b and processed using the resist or the like, so that the insulator 106a and the semiconductor 106b are formed. Note that as illustrated in FIGS. 9C and 9D, the exposed surface of the insulator 104 may be removed when the semiconductor 106b is formed.
次に、後の工程で絶縁体１０６ｃとなる絶縁体を成膜する。当該絶縁体としては上述の絶縁体、半導体又は導電体を用いればよい。当該絶縁体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, an insulator to be the insulator 106c is formed in a later step. As the insulator, the above-described insulator, semiconductor, or conductor may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
次に、絶縁体１０６ｃとなる絶縁体上にレジストなどを形成し、該レジストなどを用いて加工し、絶縁体１０６ｃを形成する（図９（Ｃ）および図９（Ｄ）参照。）。なお、図９（Ｃ）および図９（Ｄ）に示すように、絶縁体１０６ｃの形成時に、絶縁体１０４の露出した表面が、一部除去される場合がある。 Next, a resist or the like is formed over the insulator to be the insulator 106c and processed using the resist or the like, so that the insulator 106c is formed (see FIGS. 9C and 9D). Note that as illustrated in FIGS. 9C and 9D, the exposed surface of the insulator 104 may be partially removed when the insulator 106c is formed.
ここで、絶縁体１０６ａおよび絶縁体１０６ｃについて、側面端部が半導体１０６ｂの側面端部の外側に位置するようにパターン形成を行う。特に、図９（Ｄ）に示すように、絶縁体１０６ａおよび絶縁体１０６ｃのチャネル幅方向の側面端部が、半導体１０６ｂのチャネル幅方向の側面端部の外側に位置するようにパターン形成を行うことが好ましい。このように絶縁体１０６ａおよび絶縁体１０６ｃを形成することにより、半導体１０６ｂが絶縁体１０６ａおよび絶縁体１０６ｃに包み込まれる構造となる。 Here, with respect to the insulator 106a and the insulator 106c, pattern formation is performed so that the side surface end portions are located outside the side surface end portions of the semiconductor 106b. In particular, as illustrated in FIG. 9D, pattern formation is performed so that the side surface end portions of the insulator 106a and the insulator 106c in the channel width direction are located outside the side surface end portions of the semiconductor 106b in the channel width direction. It is preferable. By forming the insulator 106a and the insulator 106c in this manner, the semiconductor 106b is enclosed in the insulator 106a and the insulator 106c.
このような構造とすることにより、半導体１０６ｂの側面端部、特にチャネル幅方向の側面端部が、絶縁体１０６ａおよび絶縁体１０６ｃと接して設けられている。これにより、半導体１０６ｂの側面端部において、絶縁体１０６ａ又は絶縁体１０６ｃとの間に連続接合が形成され、欠陥準位密度が低減される。よって、低抵抗領域１０７ａおよび低抵抗領域１０７ｂを設けることによりオン電流が流れやすくなっても、半導体１０６ｂのチャネル幅方向の側面端部が寄生チャネルとならず、安定した電気特性を得ることができる。 With such a structure, the side surface end portion of the semiconductor 106b, in particular, the side surface end portion in the channel width direction is provided in contact with the insulator 106a and the insulator 106c. Thus, a continuous junction is formed between the insulator 106a or the insulator 106c at the side edge of the semiconductor 106b, and the density of defect states is reduced. Therefore, even if the on-state current easily flows by providing the low resistance region 107a and the low resistance region 107b, the side end portion in the channel width direction of the semiconductor 106b does not become a parasitic channel, and stable electrical characteristics can be obtained. .
次に、絶縁体１１２となる絶縁体を成膜する。当該絶縁体としては上述の絶縁体１１２として用いることができる絶縁体を用いればよい。当該絶縁体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。例えば、ＡＬＤ法を用いて成膜時の基板温度を４００℃以上５２０℃以下、好ましくは４５０℃以上５００℃以下に設定して絶縁体１１２を成膜すればよい。成膜時の基板温度を高くすることによって、絶縁体１１２に含まれる不純物濃度を低減することができる。例えば、成膜ガスや成膜室に含まれる炭素化合物や水などを低減することができるため、炭素濃度または／および水素濃度を低減することができる。また、成膜時の基板温度を高くすることによって、絶縁体１１２の密度（膜密度ともいう。）を高くすることができる。絶縁体１１２の密度を高くすることによって、絶縁体１１２の欠陥準位密度を低くすることができるため、作製するトランジスタに安定した電気特性を付与することができる。 Next, an insulator to be the insulator 112 is formed. As the insulator, an insulator that can be used as the above-described insulator 112 may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, the insulator 112 may be formed using the ALD method with the substrate temperature at the time of film formation being set to 400 ° C. to 520 ° C., preferably 450 ° C. to 500 ° C. By increasing the substrate temperature at the time of film formation, the concentration of impurities contained in the insulator 112 can be reduced. For example, the carbon concentration and / or the hydrogen concentration can be reduced because the deposition gas, the carbon compound, water, and the like contained in the deposition chamber can be reduced. In addition, the density of the insulator 112 (also referred to as film density) can be increased by increasing the substrate temperature during film formation. By increasing the density of the insulator 112, the density of defect states of the insulator 112 can be decreased; thus, stable electrical characteristics can be imparted to the transistor to be manufactured.
次に、導電体１１４となる導電体を成膜する。当該導電体としては、上述の導電体１１４に用いることができる導電体を用いればよい。当該導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。特に、スパッタリング法または金属ＣＶＤ法を用いると好ましい。例えばスパッタリング法により成膜する場合、Ｗ−Ｓｉターゲットなどを用いて成膜すればよい。 Next, a conductor to be the conductor 114 is formed. As the conductor, a conductor that can be used for the above-described conductor 114 may be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In particular, it is preferable to use a sputtering method or a metal CVD method. For example, when a film is formed by a sputtering method, the film may be formed using a W-Si target or the like.
次に、導電体１１４に用いることができる導電体上にレジストなどを形成し、該レジストなどを用いて加工し、絶縁体１１２および導電体１１４を形成する（図９（Ｅ）および図９（Ｆ）参照。）。ここで、導電体１１４のチャネル長方向の側面端部と絶縁体１１２のチャネル長方向の側面端部は概略一致するように形成した後で、同じマスクを用いてウェットエッチングなどによって、導電体１１４のみを選択的にエッチングしてもよい。このようにエッチングすることで、導電体１１４のゲート長方向の幅が絶縁体１１２のゲート長方向の幅より小さい構成とすることができる。 Next, a resist or the like is formed over the conductor that can be used for the conductor 114 and processed using the resist or the like, so that the insulator 112 and the conductor 114 are formed (see FIGS. 9E and 9E). See F).). Here, after the side end in the channel length direction of the conductor 114 and the side end in the channel length direction of the insulator 112 are formed to substantially coincide with each other, the conductor 114 is formed by wet etching or the like using the same mask. Only the etching may be selectively performed. By etching in this manner, the width of the conductor 114 in the gate length direction can be smaller than the width of the insulator 112 in the gate length direction.
次に、導電体１１４および絶縁体１１２をマスクとして、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃにドーパント１１９を添加する（図９（Ｅ）および図９（Ｆ）参照）。これにより、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに領域１２６ａ、領域１２６ｂおよび領域１２６ｃが形成される。このため、領域１２６ｂおよび領域１２６ｃは領域１２６ａより、ＳＩＭＳ分析により得られるドーパント１１９の濃度が高くなる。ドーパント１１９の添加方法としては、イオン化された原料ガスを質量分離して添加するイオン注入法、イオン化された原料ガスを質量分離せずに添加するイオンドーピング法などを用いることができる。質量分離を行う場合、添加するイオン種およびその濃度を厳密に制御することができる。一方、質量分離を行わない場合、短時間で高濃度のイオンを添加することができる。また、原子または分子のクラスターを生成してイオン化するイオンドーピング法を用いてもよい。なお、ドーパントを、イオン、ドナー、アクセプター、不純物または元素と言い換えてもよい。 Next, using the conductor 114 and the insulator 112 as masks, a dopant 119 is added to the insulator 106a, the semiconductor 106b, and the insulator 106c (see FIGS. 9E and 9F). Accordingly, a region 126a, a region 126b, and a region 126c are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c. Therefore, the concentration of the dopant 119 obtained by SIMS analysis is higher in the region 126b and the region 126c than in the region 126a. As a method for adding the dopant 119, an ion implantation method in which an ionized source gas is added after mass separation, an ion doping method in which an ionized source gas is added without mass separation, or the like can be used. When mass separation is performed, the ionic species to be added and the concentration thereof can be strictly controlled. On the other hand, when mass separation is not performed, high-concentration ions can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be used. Note that the dopant may be paraphrased as an ion, a donor, an acceptor, an impurity, or an element.
ドーパント１１９の添加工程は、加速電圧、ドーズ量などの注入条件を適宜設定して制御すればよい。ドーパント１１９のドーズ量は、例えば、１×１０１２ｉｏｎｓ／ｃｍ２以上１×１０１６ｉｏｎｓ／ｃｍ２以下、好ましくは１×１０１３ｉｏｎｓ／ｃｍ２以上１×１０１５ｉｏｎｓ／ｃｍ２以下とすればよい。ドーパント１１９導入時の加速電圧は２ｋＶ以上５０ｋＶ以下、好ましくは５ｋＶ以上３０ｋＶ以下とすればよい。 The addition process of the dopant 119 may be controlled by appropriately setting implantation conditions such as an acceleration voltage and a dose. The dose of the dopant 119 is, for example, 1 × 10 12 ions / cm 2 or more and 1 × 10 16 ions / cm 2 or less, preferably 1 × 10 13 ions / cm 2 or more and 1 × 10 15 ions / cm 2 or less. That's fine. The acceleration voltage at the time of introducing the dopant 119 may be 2 kV or more and 50 kV or less, preferably 5 kV or more and 30 kV or less.
ドーパント１１９としては、例えば、水素、ヘリウム、ネオン、アルゴン、クリプトン、キセノン、窒素、フッ素、リン、塩素、ヒ素、ホウ素、マグネシウム、アルミニウム、シリコン、チタン、バナジウム、クロム、ニッケル、亜鉛、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ニオブ、モリブデン、インジウム、スズ、ランタン、セリウム、ネオジム、ハフニウム、タンタルまたはタングステンなどが挙げられる。これらの元素の中でも、ヘリウム、ネオン、アルゴン、クリプトン、キセノン、窒素、フッ素、リン、塩素、ヒ素またはホウ素は、イオン注入法、イオンドーピング法などを用いて比較的容易に添加することができるため、好適である。 Examples of the dopant 119 include hydrogen, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium. Yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum or tungsten. Among these elements, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, or boron can be added relatively easily using an ion implantation method, an ion doping method, or the like. Is preferable.
また、ドーパント１１９の添加処理後、加熱処理を行ってもよい。加熱処理は、例えば、２５０℃以上６５０℃以下、好ましくは３５０℃以上４５０℃以下とし、窒素雰囲気下、減圧下、大気（超乾燥エア）下で加熱処理を行ってもよい。 Further, heat treatment may be performed after the dopant 119 is added. The heat treatment may be, for example, 250 ° C. or more and 650 ° C. or less, preferably 350 ° C. or more and 450 ° C. or less, and the heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in the air (ultra-dry air).
次に、絶縁体１１６を成膜する（図１０（Ａ）および図１０（Ｂ）参照。）。絶縁体１１６としては上述の絶縁体を用いればよい。絶縁体１１６の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。絶縁体１１６を成膜することにより、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃの絶縁体１１６との界面近傍に低抵抗領域１０７ａおよび低抵抗領域１０７ｂが形成させることができる。また、低抵抗領域１０７ａおよび低抵抗領域１０７ｂを形成させない構成としてもよい。 Next, the insulator 116 is formed (see FIGS. 10A and 10B). As the insulator 116, the above insulator may be used. The insulator 116 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. By forming the insulator 116, the low resistance region 107a and the low resistance region 107b can be formed in the vicinity of the interface of the insulator 106a, the semiconductor 106b, and the insulator 106c with the insulator 116. Further, the low resistance region 107a and the low resistance region 107b may not be formed.
絶縁体１１６を、スパッタリング法を用いて成膜する場合、金属ターゲットを用いてもよいし、酸化物ターゲットを用いてもよい。金属ターゲットを用いて成膜する場合、酸素の流量を、金属ターゲットに含まれる元素からなる膜が成膜される酸素流量と、金属ターゲットに含まれる元素を含む酸化膜が成膜される酸素流量と、の間の酸素流量になるようにすることが好ましい。このような酸素流量で成膜することにより、絶縁体１１６を、亜酸化物からなる酸化膜とすることができるので、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃ中の酸素を引き抜き、容易に低抵抗領域１０７ａおよび低抵抗領域１０７ｂを形成することができる。ここで、亜酸化物は、酸化物ができる反応過程の中間体である。よって、亜酸化物は、酸化物より酸素が欠乏している。具体的には、酸化物と比較して、酸素濃度が、１原子％以上、２原子％以上、５原子％以上または１０原子％以上低くなるものを亜酸化物とする。 In the case where the insulator 116 is formed by a sputtering method, a metal target or an oxide target may be used. In the case of film formation using a metal target, the oxygen flow rate is such that the oxygen flow rate at which a film made of an element contained in the metal target is formed and the oxygen flow rate at which an oxide film containing an element contained in the metal target is formed It is preferable that the oxygen flow rate be between. By forming the film at such an oxygen flow rate, the insulator 116 can be an oxide film made of a suboxide, so that oxygen in the insulator 106a, the semiconductor 106b, and the insulator 106c can be extracted and easily reduced. The resistance region 107a and the low resistance region 107b can be formed. Here, the suboxide is an intermediate in the reaction process for forming an oxide. Thus, suboxides are deficient in oxygen than oxides. Specifically, an oxide whose oxygen concentration is 1 atomic% or more, 2 atomic% or more, 5 atomic% or more, or 10 atomic% or more lower than an oxide is defined as a suboxide.
また、酸化物ターゲットを用いてスパッタリング法で成膜する場合、成膜雰囲気に含まれる酸素濃度が低いことが好ましい。成膜雰囲気中の酸素濃度を低くすることにより、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに酸素欠損が形成されやすくなり、容易に低抵抗領域１０７ａおよび低抵抗領域１０７ｂを形成することができる。例えば、半導体１０６ｂの成膜雰囲気の酸素濃度より低くすればよく、全体に占める酸素の割合を、５体積％未満、好ましくは２体積％未満、さらに好ましくは１体積％未満、より好ましくは０．５体積％未満とすればよい。また、酸化物ターゲットを用いて成膜する場合、成膜ガスとして酸素を用いない雰囲気で絶縁体１１６を成膜してもよい。この場合、例えば、希ガス（アルゴン、クリプトン、キセノンなど）を成膜ガスとして用いて成膜すればよい。 In the case where a film is formed by a sputtering method using an oxide target, the oxygen concentration contained in the film formation atmosphere is preferably low. By reducing the oxygen concentration in the deposition atmosphere, oxygen vacancies are easily formed in the insulator 106a, the semiconductor 106b, and the insulator 106c, and the low resistance region 107a and the low resistance region 107b can be easily formed. For example, the concentration may be lower than the oxygen concentration in the film formation atmosphere of the semiconductor 106b, and the proportion of oxygen in the whole is less than 5% by volume, preferably less than 2% by volume, more preferably less than 1% by volume, more preferably less than 0. What is necessary is just to set it as less than 5 volume%. In the case where a film is formed using an oxide target, the insulator 116 may be formed in an atmosphere in which oxygen is not used as a film formation gas. In this case, for example, a film may be formed using a rare gas (such as argon, krypton, or xenon) as a film forming gas.
また、スパッタリング法を用いて成膜する場合、基板温度を高くしても構わない。基板温度を高くすることで、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに対する、絶縁体１１６に含まれる元素の添加を助長させることができる。なお、基板の温度は、例えば、１００℃以上４５０℃以下、好ましくは１５０℃以上４００℃以下、さらに好ましくは１７０℃以上３５０℃以下とすればよい。 In the case of forming a film using a sputtering method, the substrate temperature may be increased. By increasing the substrate temperature, addition of an element contained in the insulator 116 to the insulator 106a, the semiconductor 106b, and the insulator 106c can be promoted. Note that the substrate temperature may be, for example, 100 ° C. or higher and 450 ° C. or lower, preferably 150 ° C. or higher and 400 ° C. or lower, more preferably 170 ° C. or higher and 350 ° C. or lower.
また、スパッタリング法などを用いて成膜する場合、窒素を含む雰囲気で成膜することにより、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに窒素が添加され、ｎ型化させることができるため好適である。 Further, in the case where a film is formed by a sputtering method or the like, it is preferable to form the film in an atmosphere containing nitrogen because nitrogen can be added to the insulator 106a, the semiconductor 106b, and the insulator 106c and the n-type can be obtained. is there.
また、絶縁体１１６として、上述の、ホウ素、マグネシウム、アルミニウム、シリコン、チタン、バナジウム、クロム、ニッケル、亜鉛、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ニオブ、モリブデン、インジウム、スズ、ランタン、セリウム、ネオジム、ハフニウム、タンタルまたはタングステンなどを含む酸化物、酸化窒化物、窒化酸化物または窒化物を、反応性スパッタリング法などを用いて直接成膜してもよいし、上述の元素を含む膜を成膜した後で熱処理を行って、上述の元素を含む酸化物または酸化窒化物としてもよい。熱処理温度は、例えば、２５０℃以上６５０℃以下、好ましくは３５０℃以上４５０℃以下で行えばよい。 Further, as the insulator 116, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, An oxide, oxynitride, nitride oxide, or nitride containing hafnium, tantalum, or tungsten may be directly formed by a reactive sputtering method or the like, or a film containing the above element is formed. A heat treatment may be performed later to form an oxide or oxynitride containing the above element. The heat treatment temperature may be, for example, 250 ° C. or higher and 650 ° C. or lower, preferably 350 ° C. or higher and 450 ° C. or lower.
絶縁体１１６しては、酸素とアルミニウムを含む絶縁体、例えば、酸化アルミニウム（ＡｌＯｘ）を用いることが好ましい。酸化アルミニウムは、酸素、水素、水等に対してブロッキング効果を有する。 As the insulator 116, an insulator containing oxygen and aluminum, for example, aluminum oxide (AlOx) is preferably used. Aluminum oxide has a blocking effect against oxygen, hydrogen, water and the like.
また、絶縁体１１６は、上述の絶縁体１０６ａまたは絶縁体１０６ｃとして用いることができる酸化物を用いることもできる。このような絶縁体１１６としては、Ｉｎを含む酸化絶縁物を用いることが好ましく、例えば、Ｉｎ−Ａｌ酸化物、Ｉｎ−Ｇａ酸化物、Ｉｎ−Ｇａ−Ｚｎ酸化物を用いればよい。Ｉｎを含む酸化絶縁物はスパッタリング法で成膜する際に発生するパーティクル数が少ないので、絶縁体１１８として用いるのに好適である。 Alternatively, the insulator 116 can be formed using an oxide that can be used for the insulator 106a or the insulator 106c. As such an insulator 116, an oxide insulator containing In is preferably used. For example, an In—Al oxide, an In—Ga oxide, or an In—Ga—Zn oxide may be used. An oxide insulator containing In is suitable for use as the insulator 118 because the number of particles generated when a film is formed by a sputtering method is small.
また、絶縁体１１６を成膜した後で、ドーパント１１９として用いることができる元素を添加して、領域１２６ａ、領域１２６ｂ、低抵抗領域１０７ａおよび低抵抗領域１０７ｂをさらに低抵抗化してもよい。さらに、このように添加することにより、絶縁体１１６に含まれる元素を絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに押し込む（ノックオンする）ことができる。添加方法としては、例えば、イオン注入法、イオンドーピング法などを用いることができる。 Alternatively, after the insulator 116 is formed, an element that can be used as the dopant 119 may be added to further reduce the resistance of the region 126a, the region 126b, the low resistance region 107a, and the low resistance region 107b. Further, by adding in this manner, an element contained in the insulator 116 can be pushed into (knocked on) the insulator 106a, the semiconductor 106b, and the insulator 106c. As an addition method, for example, an ion implantation method, an ion doping method, or the like can be used.
次に、加熱処理を行うことが好ましい。加熱処理を行うことにより、絶縁体１０４などから、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに酸素を供給することができる。加熱処理は、２５０℃以上６５０℃以下、好ましくは３５０℃以上４５０℃以下で行えばよい。加熱処理は、不活性ガス雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上もしくは１０％以上含む雰囲気で行う。加熱処理は減圧状態で行ってもよい。加熱処理は、ランプ加熱によるＲＴＡ装置を用いることもできる。 Next, it is preferable to perform a heat treatment. By performing heat treatment, oxygen can be supplied from the insulator 104 or the like to the insulator 106a, the semiconductor 106b, and the insulator 106c. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 350 ° C to 450 ° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. For the heat treatment, an RTA apparatus using lamp heating can also be used.
また、当該加熱処理は、半導体１０６ｂとなる半導体の成膜後の加熱処理よりも低い温度が好ましい。半導体１０６ｂとなる半導体の成膜後の加熱処理との温度差は、２０℃以上１５０℃以下、好ましくは４０℃以上１００℃以下とする。これにより、絶縁体１０４などから余分に過剰酸素（酸素）が放出することを抑えることができる。なお、絶縁体１１６成膜後の加熱処理は、同等の加熱処理を各層の成膜時の加熱によって兼ねることができる場合（例えば絶縁体１１６の成膜で同等の加熱が行われる場合）、行わなくてもよい場合がある。 The heat treatment is preferably performed at a temperature lower than that of the heat treatment after film formation of the semiconductor to be the semiconductor 106b. The temperature difference from the heat treatment after the formation of the semiconductor to be the semiconductor 106b is 20 ° C to 150 ° C, preferably 40 ° C to 100 ° C. Thus, excess oxygen (oxygen) can be prevented from being released from the insulator 104 or the like. Note that the heat treatment after the formation of the insulator 116 is performed in the case where the equivalent heat treatment can be combined with the heating during the formation of each layer (for example, when the equivalent heating is performed in the formation of the insulator 116). There may be no need.
このとき、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃは、酸素をブロックする機能を有する絶縁体１０１および絶縁体１１６に包まれているので、酸素が外方拡散することを防ぐことができる。これにより、絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃ、特に半導体１０６ｂでチャネルが形成される領域に酸素を効果的に供給することができる。このように絶縁体１０６ａ、半導体１０６ｂおよび絶縁体１０６ｃに酸素を供給し、酸素欠損を低減させることにより、欠陥準位密度の低い、高純度真性または実質的に高純度真性な酸化物半導体とすることができる。 At this time, since the insulator 106a, the semiconductor 106b, and the insulator 106c are surrounded by the insulator 101 and the insulator 116 having a function of blocking oxygen, oxygen can be prevented from diffusing outward. Accordingly, oxygen can be effectively supplied to a region where a channel is formed in the insulator 106a, the semiconductor 106b, and the insulator 106c, particularly the semiconductor 106b. In this manner, oxygen is supplied to the insulator 106a, the semiconductor 106b, and the insulator 106c to reduce oxygen vacancies, whereby a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor with low density of defect states is obtained. be able to.
次に、絶縁体１１８を成膜する。絶縁体１１８としては上述の絶縁体を用いればよい。絶縁体１１８の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, the insulator 118 is formed. As the insulator 118, the above insulator may be used. The insulator 118 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
次に、絶縁体１１８上にレジストなどを形成し、絶縁体１１８、絶縁体１１６、絶縁体１０６ｃに開口部を形成する。それから、導電体１０８ａおよび導電体１０８ｂとなる導電体を成膜する。導電体１０８ａおよび導電体１０８ｂとなる導電体としては、上述の導電体を用いることができる。当該導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, a resist or the like is formed over the insulator 118, and openings are formed in the insulator 118, the insulator 116, and the insulator 106c. Then, a conductor to be the conductor 108a and the conductor 108b is formed. As the conductor to be the conductor 108a and the conductor 108b, the above-described conductors can be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
次に、ＣＭＰ処理を行って、絶縁体１１８上の導電体１０８ａおよび導電体１０８ｂとなる導電体を除去する。その結果、絶縁体１１８、絶縁体１１６、絶縁体１０６ｃに形成された開口部の中のみに、導電体１０８ａおよび導電体１０８ｂが残存する。 Next, CMP treatment is performed to remove the conductors 108 a and 108 b over the insulator 118. As a result, the conductor 108a and the conductor 108b remain only in the openings formed in the insulator 118, the insulator 116, and the insulator 106c.
次に、絶縁体１１８、導電体１０８ａおよび導電体１０８ｂ上に、導電体１０９ａおよび導電体１０９ｂとなる導電体を成膜する。導電体１０９ａおよび導電体１０９ｂとなる導電体としては、上述の導電体を用いることができる。当該導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, a conductor to be the conductor 109a and the conductor 109b is formed over the insulator 118, the conductor 108a, and the conductor 108b. As the conductor to be the conductor 109a and the conductor 109b, the above-described conductors can be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
次に、導電体１０９ａおよび導電体１０９ｂとなる導電体上にレジストなどを形成し、該レジストなどを用いて加工し、導電体１０９ａおよび導電体１０９ｂを形成する（図１０（Ｃ）および図１０（Ｄ）参照）。 Next, a resist or the like is formed over the conductor to be the conductor 109a and the conductor 109b and processed using the resist or the like, so that the conductor 109a and the conductor 109b are formed (FIGS. 10C and 10B). (See (D)).
以上の工程により、本発明の一態様に係るトランジスタ１０を作製することができる。 Through the above steps, the transistor 10 according to one embodiment of the present invention can be manufactured.
本実施の形態により、ゲート電極に用いる導電体のイオン突き抜けを抑制し、良好な電気特性を有するトランジスタを提供することができる。 According to this embodiment, a transistor having favorable electric characteristics can be provided by suppressing ion penetration of a conductor used for a gate electrode.
以上、本実施の形態で示す構成、方法は、他の実施の形態で示す構成、方法と適宜組み合わせて用いることができる。 The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.
（実施の形態３）
本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した半導体装置の回路の一例について説明する。 (Embodiment 3)
In this embodiment, an example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described.
＜ＣＭＯＳインバータ＞
図１１（Ａ）に示す回路図は、ｐチャネル型のトランジスタ２２００とｎチャネル型のトランジスタ２１００を直列に接続し、かつそれぞれのゲートを接続した、いわゆるＣＭＯＳインバータの構成を示している。 <CMOS inverter>
The circuit diagram shown in FIG. 11A shows a structure of a so-called CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.
＜半導体装置の構造１＞
図１２は、図１１（Ａ）に対応する半導体装置の断面図である。図１２に示す半導体装置は、トランジスタ２２００と、トランジスタ２１００と、を有する。また、トランジスタ２１００は、トランジスタ２２００の上方に配置する。なお、トランジスタ２１００として、上述の実施の形態において記載したトランジスタを用いることができる。よって、トランジスタ２１００については、適宜上述したトランジスタについての記載を参酌することができる。 <Structure 1 of Semiconductor Device>
FIG. 12 is a cross-sectional view of the semiconductor device corresponding to FIG. The semiconductor device illustrated in FIG. 12 includes a transistor 2200 and a transistor 2100. The transistor 2100 is provided above the transistor 2200. Note that the transistor described in any of the above embodiments can be used as the transistor 2100. Therefore, for the transistor 2100, the above description of the transistor can be referred to as appropriate.
図１２に示すトランジスタ２２００は、半導体基板４５０を用いたトランジスタである。トランジスタ２２００は、半導体基板４５０中の領域４７２ａと、半導体基板４５０中の領域４７２ｂと、絶縁体４６２と、導電体４５４と、を有する。 A transistor 2200 illustrated in FIG. 12 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.
トランジスタ２２００において、領域４７２ａおよび領域４７２ｂは、ソース領域およびドレイン領域としての機能を有する。また、絶縁体４６２は、ゲート絶縁体としての機能を有する。また、導電体４５４は、ゲート電極としての機能を有する。したがって、導電体４５４に印加する電位によって、チャネル形成領域の抵抗を制御することができる。即ち、導電体４５４に印加する電位によって、領域４７２ａと領域４７２ｂとの間の導通・非導通を制御することができる。 In the transistor 2200, the region 472a and the region 472b function as a source region and a drain region. The insulator 462 functions as a gate insulator. The conductor 454 functions as a gate electrode. Therefore, the resistance of the channel formation region can be controlled by the potential applied to the conductor 454. That is, conduction / non-conduction between the region 472a and the region 472b can be controlled by a potential applied to the conductor 454.
半導体基板４５０としては、例えば、シリコン、ゲルマニウムなどの単体半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムなどの半導体基板などを用いればよい。好ましくは、半導体基板４５０として単結晶シリコン基板を用いる。 As the semiconductor substrate 450, for example, a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used. A single crystal silicon substrate is preferably used as the semiconductor substrate 450.
半導体基板４５０は、ｎ型の導電型を付与する不純物を有する半導体基板を用いる。ただし、半導体基板４５０として、ｐ型の導電型を付与する不純物を有する半導体基板を用いても構わない。その場合、トランジスタ２２００となる領域には、ｎ型の導電型を付与する不純物を有するウェルを配置すればよい。または、半導体基板４５０がｉ型であっても構わない。 As the semiconductor substrate 450, a semiconductor substrate having an impurity imparting n-type conductivity is used. However, as the semiconductor substrate 450, a semiconductor substrate having an impurity imparting p-type conductivity may be used. In that case, a well having an impurity imparting n-type conductivity may be provided in a region to be the transistor 2200. Alternatively, the semiconductor substrate 450 may be i-type.
半導体基板４５０の上面は、（１１０）面を有することが好ましい。こうすることで、トランジスタ２２００のオン特性を向上させることができる。 The upper surface of the semiconductor substrate 450 preferably has a (110) plane. Thus, the on-state characteristics of the transistor 2200 can be improved.
領域４７２ａおよび領域４７２ｂは、ｐ型の導電型を付与する不純物を有する領域である。このようにして、トランジスタ２２００はｐチャネル型トランジスタを構成する。 The region 472a and the region 472b are regions having an impurity imparting p-type conductivity. In this manner, the transistor 2200 constitutes a p-channel transistor.
なお、トランジスタ２２００は、領域４６０などによって隣接するトランジスタと分離される。領域４６０は、絶縁性を有する領域である。 Note that the transistor 2200 is separated from an adjacent transistor by the region 460 or the like. The region 460 is a region having an insulating property.
図１２に示す半導体装置は、絶縁体４６４と、絶縁体４６６と、絶縁体４６８と、導電体４８０ａと、導電体４８０ｂと、導電体４８０ｃと、導電体４７８ａと、導電体４７８ｂと、導電体４７８ｃと、導電体４７６ａと、導電体４７６ｂと、導電体４７４ａと、導電体４７４ｂと、導電体４７４ｃと、導電体４９６ａと、導電体４９６ｂと、導電体４９６ｃと、導電体４９６ｄと、導電体４９８ａと、導電体４９８ｂと、導電体４９８ｃと、絶縁体４８９と、絶縁体４９０と、絶縁体４９１と、絶縁体４９２と、絶縁体４９３と、絶縁体４９４と、絶縁体４９５と、を有する。 The semiconductor device illustrated in FIG. 12 includes an insulator 464, an insulator 466, an insulator 468, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, a conductor 478b, and a conductor. 478c, a conductor 476a, a conductor 476b, a conductor 474a, a conductor 474b, a conductor 474c, a conductor 496a, a conductor 496b, a conductor 496c, a conductor 496d, and a conductor 498a, a conductor 498b, a conductor 498c, an insulator 489, an insulator 490, an insulator 491, an insulator 492, an insulator 493, an insulator 494, and an insulator 495. .
絶縁体４６４は、トランジスタ２２００上に配置する。また、絶縁体４６６は、絶縁体４６４上に配置する。また、絶縁体４６８は、絶縁体４６６上に配置する。また、絶縁体４８９は、絶縁体４６８上に配置する。また、トランジスタ２１００は、絶縁体４８９上に配置する。また、絶縁体４９３は、トランジスタ２１００上に配置する。また、絶縁体４９４は、絶縁体４９３上に配置する。 The insulator 464 is provided over the transistor 2200. The insulator 466 is provided over the insulator 464. The insulator 468 is provided over the insulator 466. The insulator 489 is disposed over the insulator 468. The transistor 2100 is provided over the insulator 489. The insulator 493 is provided over the transistor 2100. The insulator 494 is provided over the insulator 493.
絶縁体４６４は、領域４７２ａに達する開口部と、領域４７２ｂに達する開口部と、導電体４５４に達する開口部と、を有する。また、開口部には、それぞれ導電体４８０ａ、導電体４８０ｂまたは導電体４８０ｃが埋め込まれている。 The insulator 464 includes an opening reaching the region 472a, an opening reaching the region 472b, and an opening reaching the conductor 454. In addition, a conductor 480a, a conductor 480b, or a conductor 480c is embedded in each opening.
また、絶縁体４６６は、導電体４８０ａに達する開口部と、導電体４８０ｂに達する開口部と、導電体４８０ｃに達する開口部と、を有する。また、開口部には、それぞれ導電体４７８ａ、導電体４７８ｂまたは導電体４７８ｃが埋め込まれている。 The insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c. In addition, a conductor 478a, a conductor 478b, or a conductor 478c is embedded in each opening.
また、絶縁体４６８は、導電体４７８ｂに達する開口部と、導電体４７８ｃに達する開口部と、を有する。また、開口部には、それぞれ導電体４７６ａまたは導電体４７６ｂが埋め込まれている。 The insulator 468 includes an opening reaching the conductor 478b and an opening reaching the conductor 478c. In addition, a conductor 476a or a conductor 476b is embedded in each opening.
また、絶縁体４８９は、トランジスタ２１００のチャネル形成領域と重なる開口部と、導電体４７６ａに達する開口部と、導電体４７６ｂに達する開口部と、を有する。また、開口部には、それぞれ導電体４７４ａ、導電体４７４ｂまたは導電体４７４ｃが埋め込まれている。 The insulator 489 includes an opening overlapping with a channel formation region of the transistor 2100, an opening reaching the conductor 476a, and an opening reaching the conductor 476b. In addition, a conductor 474a, a conductor 474b, or a conductor 474c is embedded in each opening.
導電体４７４ａは、トランジスタ２１００のゲート電極としての機能を有しても構わない。または、例えば、導電体４７４ａに一定の電位を印加することで、トランジスタ２１００のしきい値電圧などの電気特性を制御しても構わない。または、例えば、導電体４７４ａとトランジスタ２１００のゲート電極としての機能を有する導電体５０４とを電気的に接続しても構わない。こうすることで、トランジスタ２１００のオン電流を大きくすることができる。また、パンチスルー現象を抑制することができるため、トランジスタ２１００の飽和領域における電気特性を安定にすることができる。なお、導電体４７４ａは上記実施の形態の導電体１０２に相当するため、詳細については導電体１０２の記載を参酌することができる。 The conductor 474a may function as the gate electrode of the transistor 2100. Alternatively, for example, electrical characteristics such as a threshold voltage of the transistor 2100 may be controlled by applying a certain potential to the conductor 474a. Alternatively, for example, the conductor 474a and the conductor 504 functioning as a gate electrode of the transistor 2100 may be electrically connected. Thus, the on-state current of the transistor 2100 can be increased. In addition, since the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 2100 can be stabilized. Note that since the conductor 474a corresponds to the conductor 102 in the above embodiment, the description of the conductor 102 can be referred to for details.
また、絶縁体４９０は、導電体４７４ｂに達する開口部と、導電体４７４ｃに達する開口部と、を有する。なお、絶縁体４９０は上記実施の形態に示す絶縁体１０１に用いた絶縁体を用いればよい。開口部を除いて導電体４７４ａ乃至４７４ｃの上を覆うように絶縁体４９０を設けることにより、絶縁体４９１から導電体４７４ａ乃至４７４ｃが酸素を引き抜くことを防ぐことができる。これにより、絶縁体４９１からトランジスタ２１００の酸化物半導体に効果的に酸素を供給することができる。 The insulator 490 includes an opening reaching the conductor 474b and an opening reaching the conductor 474c. Note that the insulator used for the insulator 101 described in the above embodiment may be used for the insulator 490. By providing the insulator 490 so as to cover the conductors 474a to 474c except for the openings, the conductors 474a to 474c can be prevented from extracting oxygen from the insulator 491. Accordingly, oxygen can be effectively supplied from the insulator 491 to the oxide semiconductor of the transistor 2100.
また、絶縁体４９１は、導電体４７４ｂに達する開口部と、導電体４７４ｃに達する開口部と、を有する。なお、絶縁体４９１は上記実施の形態の絶縁体１０４に相当するため、詳細については絶縁体１０４の記載を参酌することができる。 The insulator 491 includes an opening reaching the conductor 474b and an opening reaching the conductor 474c. Note that since the insulator 491 corresponds to the insulator 104 in the above embodiment, the description of the insulator 104 can be referred to for details.
また、絶縁体４９５は、トランジスタ２１００のソースまたはドレインの一方である領域５０７ｂを通って、導電体４７４ｂに達する開口部と、トランジスタ２１００のソースまたはドレインの他方である領域５０７ａに達する開口部と、トランジスタ２１００のゲート電極である導電体５０４に達する開口部と、導電体４７４ｃに達する開口部と、を有する。なお、絶縁体４９５は上記実施の形態の絶縁体１１６に相当するため、詳細については絶縁体１１６の記載を参酌することができる。 The insulator 495 includes an opening reaching the conductor 474b through the region 507b that is one of the source and the drain of the transistor 2100, and an opening reaching the region 507a that is the other of the source and the drain of the transistor 2100; An opening reaching the conductor 504 which is a gate electrode of the transistor 2100 and an opening reaching the conductor 474c are provided. Note that since the insulator 495 corresponds to the insulator 116 in the above embodiment, the description of the insulator 116 can be referred to for details.
また、絶縁体４９３は、トランジスタ２１００のソースまたはドレインの一方である領域５０７ｂを通って、導電体４７４ｂに達する開口部と、トランジスタ２１００のソースまたはドレインの他方である領域５０７ａに達する開口部と、トランジスタ２１００のゲート電極である導電体５０４に達する開口部と、導電体４７４ｃに達する開口部と、を有する。また、開口部には、それぞれ導電体４９６ａ、導電体４９６ｂ、導電体４９６ｃまたは導電体４９６ｄが埋め込まれている。ただし、それぞれの開口部は、さらにトランジスタ２１００などの構成要素のいずれかが有する開口部を介する場合がある。なお、絶縁体４９３は上記実施の形態の絶縁体１１８に相当するため、詳細については絶縁体１１８の記載を参酌することができる。 The insulator 493 includes an opening reaching the conductor 474b through the region 507b that is one of the source and the drain of the transistor 2100, and an opening reaching the region 507a that is the other of the source and the drain of the transistor 2100; An opening reaching the conductor 504 which is a gate electrode of the transistor 2100 and an opening reaching the conductor 474c are provided. In addition, a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496d is embedded in each opening. Note that each opening may be provided through an opening further included in any of the components such as the transistor 2100. Note that since the insulator 493 corresponds to the insulator 118 in the above embodiment, the description of the insulator 118 can be referred to for details.
また、絶縁体４９４は、導電体４９６ａに達する開口部と、導電体４９６ｂおよび導電体４９６ｄに達する開口部と、導電体４９６ｃに達する開口部と、を有する。また、開口部には、それぞれ導電体４９８ａ、導電体４９８ｂまたは導電体４９８ｃが埋め込まれている。 The insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b and the conductor 496d, and an opening reaching the conductor 496c. In addition, a conductor 498a, a conductor 498b, or a conductor 498c is embedded in each opening.
絶縁体４６４、絶縁体４６６、絶縁体４６８、絶縁体４８９、絶縁体４９３および絶縁体４９４としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁体を、単層で、または積層で用いればよい。 As the insulator 464, the insulator 466, the insulator 468, the insulator 489, the insulator 493, and the insulator 494, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, An insulator containing gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
絶縁体４６４、絶縁体４６６、絶縁体４６８、絶縁体４８９、絶縁体４９３または絶縁体４９４の一以上は、水素などの不純物および酸素をブロックする機能を有する絶縁体を有することが好ましい。トランジスタ２１００の近傍に、水素などの不純物および酸素をブロックする機能を有する絶縁体を配置することによって、トランジスタ２１００の電気特性を安定にすることができる。 One or more of the insulator 464, the insulator 466, the insulator 468, the insulator 489, the insulator 493, or the insulator 494 preferably includes an insulator having a function of blocking impurities such as hydrogen and oxygen. When an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 2100, the electrical characteristics of the transistor 2100 can be stabilized.
水素などの不純物および酸素をブロックする機能を有する絶縁体としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁体を、単層で、または積層で用いればよい。 Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum. An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
導電体４８０ａ、導電体４８０ｂ、導電体４８０ｃ、導電体４７８ａ、導電体４７８ｂ、導電体４７８ｃ、導電体４７６ａ、導電体４７６ｂ、導電体４７４ａ、導電体４７４ｂ、導電体４７４ｃ、導電体４９６ａ、導電体４９６ｂ、導電体４９６ｃ、導電体４９６ｄ、導電体４９８ａ、導電体４９８ｂおよび導電体４９８ｃとしては、例えば、ホウ素、窒素、酸素、フッ素、シリコン、リン、アルミニウム、チタン、クロム、マンガン、コバルト、ニッケル、銅、亜鉛、ガリウム、イットリウム、ジルコニウム、モリブデン、ルテニウム、銀、インジウム、スズ、タンタルおよびタングステンを一種以上含む導電体を、単層で、または積層で用いればよい。例えば、合金や化合物であってもよく、アルミニウムを含む導電体、銅およびチタンを含む導電体、銅およびマンガンを含む導電体、インジウム、スズおよび酸素を含む導電体、チタンおよび窒素を含む導電体などを用いてもよい。 Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, conductor 498a, conductor 498b, and conductor 498c include, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, A conductor including one or more of copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.
なお、図１３に示す半導体装置は、図１２に示した半導体装置のトランジスタ２２００の構造が異なるのみである。よって、図１３に示す半導体装置については、図１２に示した半導体装置の記載を参酌する。具体的には、図１３に示す半導体装置は、トランジスタ２２００がＦｉｎ型である場合を示している。トランジスタ２２００をＦｉｎ型とすることにより、実効上のチャネル幅が増大することによりトランジスタ２２００のオン特性を向上させることができる。また、ゲート電極の電界の寄与を高くすることができるため、トランジスタ２２００のオフ特性を向上させることができる。 Note that the semiconductor device illustrated in FIG. 13 is different only in the structure of the transistor 2200 of the semiconductor device illustrated in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 12 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 13 illustrates the case where the transistor 2200 is a Fin type. By setting the transistor 2200 to be a Fin type, an effective channel width can be increased, whereby the on-state characteristics of the transistor 2200 can be improved. In addition, since the contribution of the electric field of the gate electrode can be increased, off characteristics of the transistor 2200 can be improved.
また、図１４に示す半導体装置は、図１２に示した半導体装置のトランジスタ２２００の構造が異なるのみである。よって、図１４に示す半導体装置については、図１２に示した半導体装置の記載を参酌する。具体的には、図１４に示す半導体装置は、トランジスタ２２００がＳＯＩ基板である半導体基板４５０に設けられた場合を示している。図１４には、絶縁体４５２によって領域４５６が半導体基板４５０と分離されている構造を示す。半導体基板４５０としてＳＯＩ基板を用いることによって、パンチスルー現象などを抑制することができるためトランジスタ２２００のオフ特性を向上させることができる。なお、絶縁体４５２は、半導体基板４５０を絶縁体化させることによって形成することができる。例えば、絶縁体４５２としては、酸化シリコンを用いることができる。 Further, the semiconductor device shown in FIG. 14 is different only in the structure of the transistor 2200 of the semiconductor device shown in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 12 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 14 illustrates the case where the transistor 2200 is provided over a semiconductor substrate 450 which is an SOI substrate. FIG. 14 illustrates a structure in which the region 456 is separated from the semiconductor substrate 450 by an insulator 452. By using an SOI substrate as the semiconductor substrate 450, a punch-through phenomenon or the like can be suppressed, so that off characteristics of the transistor 2200 can be improved. Note that the insulator 452 can be formed by making the semiconductor substrate 450 an insulator. For example, as the insulator 452, silicon oxide can be used.
図１２乃至図１４に示した半導体装置は、半導体基板を用いてｐチャネル型トランジスタを作製し、その上方にｎチャネル型トランジスタを作製するため、素子の占有面積を縮小することができる。即ち、半導体装置の集積度を高くすることができる。また、ｎチャネル型トランジスタと、ｐチャネル型トランジスタとを同一の半導体基板を用いて作製した場合と比べて、工程を簡略化することができるため、半導体装置の生産性を高くすることができる。また、半導体装置の歩留まりを高くすることができる。また、ｐチャネル型トランジスタは、ＬＤＤ（Ｌｉｇｈｔｌｙ　Ｄｏｐｅｄ　Ｄｒａｉｎ）領域、シャロートレンチ構造、歪み設計などの複雑な工程を省略できる場合がある。そのため、ｎチャネル型トランジスタを、半導体基板を用いて作製する場合と比べて、生産性および歩留まりを高くすることができる場合がある。 In the semiconductor device illustrated in FIGS. 12 to 14, a p-channel transistor is manufactured using a semiconductor substrate and an n-channel transistor is formed thereabove, so that the area occupied by the element can be reduced. That is, the degree of integration of the semiconductor device can be increased. Further, since the process can be simplified as compared with the case where an n-channel transistor and a p-channel transistor are formed using the same semiconductor substrate, the productivity of the semiconductor device can be increased. In addition, the yield of the semiconductor device can be increased. In addition, a p-channel transistor can sometimes omit complicated processes such as an LDD (Lightly Doped Drain) region, a shallow trench structure, and a strain design. Therefore, productivity and yield may be increased as compared with the case where an n-channel transistor is manufactured using a semiconductor substrate.
＜ＣＭＯＳアナログスイッチ＞
また図１１（Ｂ）に示す回路図は、トランジスタ２１００とトランジスタ２２００のそれぞれのソースとドレインを接続した構成を示している。このような構成とすることで、いわゆるＣＭＯＳアナログスイッチとして機能させることができる。 <CMOS analog switch>
In addition, the circuit diagram illustrated in FIG. 11B illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, it can function as a so-called CMOS analog switch.
＜記憶装置１＞
本発明の一態様に係るトランジスタを用いた、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置（記憶装置）の一例を図１５に示す。 <Storage device 1>
FIG. 15 illustrates an example of a semiconductor device (memory device) using the transistor according to one embodiment of the present invention, which can hold stored data even in a state where power is not supplied and has no limit on the number of writing times.
図１５（Ａ）に示す半導体装置は、第１の半導体を用いたトランジスタ３２００と第２の半導体を用いたトランジスタ３３００、および容量素子３４００を有している。なお、トランジスタ３３００としては、上述のトランジスタ２１００と同様のトランジスタを用いることができる。 A semiconductor device illustrated in FIG. 15A includes a transistor 3200 including a first semiconductor, a transistor 3300 including a second semiconductor, and a capacitor 3400. Note that as the transistor 3300, a transistor similar to the above-described transistor 2100 can be used.
トランジスタ３３００は、オフ電流の小さいトランジスタが好ましい。トランジスタ３３００は、例えば、酸化物半導体を用いたトランジスタを用いることができる。トランジスタ３３００のオフ電流が小さいことにより、半導体装置の特定のノードに長期にわたり記憶内容を保持することが可能である。つまり、リフレッシュ動作を必要としない、またはリフレッシュ動作の頻度が極めて少なくすることが可能となるため、消費電力の低い半導体装置となる。 The transistor 3300 is preferably a transistor with low off-state current. As the transistor 3300, for example, a transistor including an oxide semiconductor can be used. Since the off-state current of the transistor 3300 is small, stored data can be held in a specific node of the semiconductor device for a long time. That is, a refresh operation is not required or the frequency of the refresh operation can be extremely low, so that the semiconductor device with low power consumption is obtained.
図１５（Ａ）において、第１の配線３００１はトランジスタ３２００のソースと電気的に接続され、第２の配線３００２はトランジスタ３２００のドレインと電気的に接続される。また、第３の配線３００３はトランジスタ３３００のソース、ドレインの一方と電気的に接続され、第４の配線３００４はトランジスタ３３００のゲートと電気的に接続されている。そして、トランジスタ３２００のゲート、およびトランジスタ３３００のソース、ドレインの他方は、容量素子３４００の電極の一方と電気的に接続され、第５の配線３００５は容量素子３４００の電極の他方と電気的に接続されている。 In FIG. 15A, the first wiring 3001 is electrically connected to the source of the transistor 3200, and the second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of a source and a drain of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one of the electrodes of the capacitor 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 3400. Has been.
図１５（Ａ）に示す半導体装置は、トランジスタ３２００のゲートの電位が保持可能という特性を有することで、以下に示すように、情報の書き込み、保持、読み出しが可能である。 The semiconductor device illustrated in FIG. 15A has a characteristic that the potential of the gate of the transistor 3200 can be held; thus, information can be written, held, and read as described below.
情報の書き込みおよび保持について説明する。まず、第４の配線３００４の電位を、トランジスタ３３００が導通状態となる電位にして、トランジスタ３３００を導通状態とする。これにより、第３の配線３００３の電位が、トランジスタ３２００のゲート、および容量素子３４００の電極の一方と電気的に接続するノードＦＧに与えられる。即ち、トランジスタ３２００のゲートには、所定の電荷が与えられる（書き込み）。ここでは、異なる二つの電位レベルを与える電荷（以下Ｌｏｗレベル電荷、Ｈｉｇｈレベル電荷という。）のどちらかが与えられるものとする。その後、第４の配線３００４の電位を、トランジスタ３３００が非導通状態となる電位にして、トランジスタ３３００を非導通状態とすることにより、ノードＦＧに電荷が保持される（保持）。 Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG electrically connected to one of the gate of the transistor 3200 and the electrode of the capacitor 3400. That is, predetermined charge is supplied to the gate of the transistor 3200 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off and the transistor 3300 is turned off, so that charge is held at the node FG (holding).
トランジスタ３３００のオフ電流が小さいため、ノードＦＧの電荷は長期間にわたって保持される。 Since the off-state current of the transistor 3300 is small, the charge of the node FG is held for a long time.
次に情報の読み出しについて説明する。第１の配線３００１に所定の電位（定電位）を与えた状態で、第５の配線３００５に適切な電位（読み出し電位）を与えると、第２の配線３００２は、ノードＦＧに保持された電荷量に応じた電位をとる。これは、トランジスタ３２００をｎチャネル型とすると、トランジスタ３２００のゲートにＨｉｇｈレベル電荷が与えられている場合の見かけ上のしきい値電圧Ｖｔｈ＿Ｈは、トランジスタ３２００のゲートにＬｏｗレベル電荷が与えられている場合の見かけ上のしきい値電圧Ｖｔｈ＿Ｌより低くなるためである。ここで、見かけ上のしきい値電圧とは、トランジスタ３２００を「導通状態」とするために必要な第５の配線３００５の電位をいうものとする。したがって、第５の配線３００５の電位をＶｔｈ＿ＨとＶｔｈ＿Ｌの間の電位Ｖ０とすることにより、ノードＦＧに与えられた電荷を判別できる。例えば、書き込みにおいて、ノードＦＧにＨｉｇｈレベル電荷が与えられていた場合には、第５の配線３００５の電位がＶ０（＞Ｖｔｈ＿Ｈ）となれば、トランジスタ３２００は「導通状態」となる。一方、ノードＦＧにＬｏｗレベル電荷が与えられていた場合には、第５の配線３００５の電位がＶ０（＜Ｖｔｈ＿Ｌ）となっても、トランジスタ３２００は「非導通状態」のままである。このため、第２の配線３００２の電位を判別することで、ノードＦＧに保持されている情報を読み出すことができる。 Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 3200 is an n-channel type, the apparent threshold voltage V th_H when a high level charge is applied to the gate of the transistor 3200 is the low level charge applied to the gate of the transistor 3200. This is because it becomes lower than the apparent threshold voltage V th_L in the case of being present. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 3200 into a “conducting state”. Therefore, by setting the potential of the fifth wiring 3005 to a potential V 0 between V th_H and V th_L , the charge given to the node FG can be determined. For example, in the case where a high-level charge is applied to the node FG in writing, the transistor 3200 is in a “conducting state” if the potential of the fifth wiring 3005 is V 0 (> V th_H ). On the other hand, when a low-level charge is supplied to the node FG, the transistor 3200 remains in the “non-conductive state” even when the potential of the fifth wiring 3005 becomes V 0 (<V th_L ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.
なお、メモリセルをアレイ状に配置する場合、読み出し時には、所望のメモリセルの情報を読み出さなくてはならない。情報を読み出さないメモリセルにおいては、ノードＦＧに与えられた電荷によらずトランジスタ３２００が「非導通状態」となるような電位、つまり、Ｖｔｈ＿Ｈより低い電位を第５の配線３００５に与えることで所望のメモリセルの情報のみを読み出せる構成とすればよい。または、情報を読み出さないメモリセルにおいては、ノードＦＧに与えられた電荷によらずトランジスタ３２００が「導通状態」となるような電位、つまり、Ｖｔｈ＿Ｌより高い電位を第５の配線３００５に与えることで所望のメモリセルの情報のみを読み出せる構成とすればよい。 Note that when memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. In a memory cell from which information is not read, the fifth wiring 3005 is supplied with a potential at which the transistor 3200 is in a “non-conduction state” regardless of the charge applied to the node FG, that is, a potential lower than V th_H. A configuration in which only information of a desired memory cell can be read out is sufficient. Alternatively , in the memory cell from which information is not read, the fifth wiring 3005 is supplied with a potential at which the transistor 3200 becomes “conductive” regardless of the charge applied to the node FG, that is, a potential higher than V th_L. Thus, only the desired memory cell information may be read.
なお、上記においては、２種類の電荷をノードＦＧに保持する例について示したが、本発明に係る半導体装置はこれに限られるものではない。例えば、半導体装置のノードＦＧに３種類以上の電荷をノードに保持できる構成としてもよい。このような構成とすることにより、当該半導体装置を多値化して記憶容量の増大を図ることができる。 Note that, in the above, an example in which two types of charges are held in the node FG has been described, but the semiconductor device according to the present invention is not limited to this. For example, a structure in which three or more kinds of electric charges can be held in the node FG of the semiconductor device may be employed. With such a structure, the semiconductor device can be multi-valued and the storage capacity can be increased.
＜記憶装置の構造１＞
図１６は、図１５（Ａ）に対応する半導体装置の断面図である。図１６に示す半導体装置は、トランジスタ３２００と、トランジスタ３３００と、容量素子３４００と、を有する。また、トランジスタ３３００および容量素子３４００は、トランジスタ３２００の上方に配置する。なお、トランジスタ３３００としては、上述したトランジスタ２１００についての記載を参照する。また、トランジスタ３２００としては、図１２に示したトランジスタ２２００についての記載を参照する。なお、図１２では、トランジスタ２２００がｐチャネル型トランジスタである場合について説明したが、トランジスタ３２００がｎチャネル型トランジスタであっても構わない。 <Structure 1 of storage device>
FIG. 16 is a cross-sectional view of the semiconductor device corresponding to FIG. The semiconductor device illustrated in FIG. 16 includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are provided above the transistor 3200. Note that as the transistor 3300, the above description of the transistor 2100 is referred to. For the transistor 3200, the description of the transistor 2200 illustrated in FIGS. Note that although FIG. 12 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.
図１６に示すトランジスタ２２００は、半導体基板４５０を用いたトランジスタである。トランジスタ２２００は、半導体基板４５０中の領域４７２ａと、半導体基板４５０中の領域４７２ｂと、絶縁体４６２と、導電体４５４と、を有する。 A transistor 2200 illustrated in FIG. 16 is a transistor including a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.
図１６に示す半導体装置は、絶縁体４６４と、絶縁体４６６と、絶縁体４６８と、導電体４８０ａと、導電体４８０ｂと、導電体４８０ｃと、導電体４７８ａと、導電体４７８ｂと、導電体４７８ｃと、導電体４７６ａと、導電体４７６ｂと、導電体４７４ａと、導電体４７４ｂと、導電体４７４ｃと、導電体４９６ａと、導電体４９６ｂと、導電体４９６ｃと、導電体４９６ｄと、導電体４９８ａと、導電体４９８ｂと、導電体４９８ｃと、絶縁体４８９と、絶縁体４９０と、絶縁体４９１と、絶縁体４９２と、絶縁体４９３と、絶縁体４９４と、絶縁体４９５と、を有する。 The semiconductor device illustrated in FIG. 16 includes an insulator 464, an insulator 466, an insulator 468, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, a conductor 478b, and a conductor. 478c, a conductor 476a, a conductor 476b, a conductor 474a, a conductor 474b, a conductor 474c, a conductor 496a, a conductor 496b, a conductor 496c, a conductor 496d, and a conductor 498a, a conductor 498b, a conductor 498c, an insulator 489, an insulator 490, an insulator 491, an insulator 492, an insulator 493, an insulator 494, and an insulator 495. .
絶縁体４６４は、トランジスタ３２００上に配置する。また、絶縁体４６６は、絶縁体４６４上に配置する。また、絶縁体４６８は、絶縁体４６６上に配置する。また、絶縁体４８９は、絶縁体４６８上に配置する。また、トランジスタ２１００は、絶縁体４８９上に配置する。また、絶縁体４９３は、トランジスタ２１００上に配置する。また、絶縁体４９４は、絶縁体４９３上に配置する。 The insulator 464 is provided over the transistor 3200. The insulator 466 is provided over the insulator 464. The insulator 468 is provided over the insulator 466. The insulator 489 is disposed over the insulator 468. The transistor 2100 is provided over the insulator 489. The insulator 493 is provided over the transistor 2100. The insulator 494 is provided over the insulator 493.
絶縁体４６４は、領域４７２ａに達する開口部と、領域４７２ｂに達する開口部と、導電体４５４に達する開口部と、を有する。また、開口部には、それぞれ導電体４８０ａ、導電体４８０ｂまたは導電体４８０ｃが埋め込まれている。 The insulator 464 includes an opening reaching the region 472a, an opening reaching the region 472b, and an opening reaching the conductor 454. In addition, a conductor 480a, a conductor 480b, or a conductor 480c is embedded in each opening.
また、絶縁体４６６は、導電体４８０ａに達する開口部と、導電体４８０ｂに達する開口部と、導電体４８０ｃに達する開口部と、を有する。また、開口部には、それぞれ導電体４７８ａ、導電体４７８ｂまたは導電体４７８ｃが埋め込まれている。 The insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c. In addition, a conductor 478a, a conductor 478b, or a conductor 478c is embedded in each opening.
また、絶縁体４６８は、導電体４７８ｂに達する開口部と、導電体４７８ｃに達する開口部と、を有する。また、開口部には、それぞれ導電体４７６ａまたは導電体４７６ｂが埋め込まれている。 The insulator 468 includes an opening reaching the conductor 478b and an opening reaching the conductor 478c. In addition, a conductor 476a or a conductor 476b is embedded in each opening.
また、絶縁体４８９は、トランジスタ３３００のチャネル形成領域と重なる開口部と、導電体４７６ａに達する開口部と、導電体４７６ｂに達する開口部と、を有する。また、開口部には、それぞれ導電体４７４ａ、導電体４７４ｂまたは導電体４７４ｃが埋め込まれている。 The insulator 489 includes an opening overlapping with a channel formation region of the transistor 3300, an opening reaching the conductor 476a, and an opening reaching the conductor 476b. In addition, a conductor 474a, a conductor 474b, or a conductor 474c is embedded in each opening.
導電体４７４ａは、トランジスタ３３００のボトムゲート電極としての機能を有しても構わない。または、例えば、導電体４７４ａに一定の電位を印加することで、トランジスタ３３００のしきい値電圧などの電気特性を制御しても構わない。または、例えば、導電体４７４ａとトランジスタ３３００のトップゲート電極である導電体５０４とを電気的に接続しても構わない。こうすることで、トランジスタ３３００のオン電流を大きくすることができる。また、パンチスルー現象を抑制することができるため、トランジスタ３３００の飽和領域における電気特性を安定にすることができる。 The conductor 474a may function as the bottom gate electrode of the transistor 3300. Alternatively, for example, electrical characteristics such as a threshold voltage of the transistor 3300 may be controlled by applying a certain potential to the conductor 474a. Alternatively, for example, the conductor 474a and the conductor 504 which is the top gate electrode of the transistor 3300 may be electrically connected. Thus, the on-state current of the transistor 3300 can be increased. In addition, since the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 3300 can be stabilized.
また、絶縁体４９０は、導電体４７４ｂに達する開口部と、導電体４７４ｃに達する開口部と、を有する。なお、絶縁体４９０は上記実施の形態に示す絶縁体１０１に用いた絶縁体を用いればよい。開口部を除いて導電体４７４ａ乃至４７４ｃの上を覆うように絶縁体４９０を設けることにより、絶縁体４９１から導電体４７４ａ乃至４７４ｃが酸素を引き抜くことを防ぐことができる。これにより、絶縁体４９１からトランジスタ３３００の酸化物半導体に効果的に酸素を供給することができる。 The insulator 490 includes an opening reaching the conductor 474b and an opening reaching the conductor 474c. Note that the insulator used for the insulator 101 described in the above embodiment may be used for the insulator 490. By providing the insulator 490 so as to cover the conductors 474a to 474c except for the openings, the conductors 474a to 474c can be prevented from extracting oxygen from the insulator 491. Accordingly, oxygen can be effectively supplied from the insulator 491 to the oxide semiconductor of the transistor 3300.
また、絶縁体４９１は、導電体４７４ｂに達する開口部と、導電体４７４ｃに達する開口部と、を有する。なお、絶縁体４９１は上記実施の形態の絶縁体１０４に相当するため、詳細については絶縁体１０４の記載を参酌することができる。 The insulator 491 includes an opening reaching the conductor 474b and an opening reaching the conductor 474c. Note that since the insulator 491 corresponds to the insulator 104 in the above embodiment, the description of the insulator 104 can be referred to for details.
また、絶縁体４９５は、トランジスタ３３００のソースまたはドレインの一方である領域５０７ｂを通って、導電体４７４ｂに達する開口部と、トランジスタ３３００のソースまたはドレインの他方である領域５０７ａと絶縁体５１１を介して重なる導電体５１４に達する開口部と、トランジスタ３３００のゲート電極である導電体５０４に達する開口部と、トランジスタ３３００のソースまたはドレインの他方である領域５０７ａを通って、導電体４７４ｃに達する開口部と、を有する。なお、絶縁体４９５は上記実施の形態の絶縁体１１６に相当するため、詳細については絶縁体１１６の記載を参酌することができる。 The insulator 495 includes an opening reaching the conductor 474b through the region 507b which is one of the source and the drain of the transistor 3300, and the region 507a which is the other of the source and the drain of the transistor 3300 and the insulator 511. An opening reaching the conductor 514 that overlaps, an opening reaching the conductor 504 which is the gate electrode of the transistor 3300, and an opening reaching the conductor 474c through the region 507a which is the other of the source and the drain of the transistor 3300 And having. Note that since the insulator 495 corresponds to the insulator 116 in the above embodiment, the description of the insulator 116 can be referred to for details.
また、絶縁体４９３は、トランジスタ３３００のソースまたはドレインの一方である領域５０７ｂを通って、導電体４７４ｂに達する開口部と、トランジスタ３３００のソースまたはドレインの他方である領域５０７ａと絶縁体５１１を介して重なる導電体５１４に達する開口部と、トランジスタ３３００のゲート電極である導電体５０４に達する開口部と、トランジスタ３３００のソースまたはドレインの他方である領域５０７ａを通って、導電体４７４ｃに達する開口部と、を有する。また、開口部には、それぞれ導電体４９６ａ、導電体４９６ｂ、導電体４９６ｃまたは導電体４９６ｄが埋め込まれている。ただし、それぞれの開口部は、さらにトランジスタ３３００などの構成要素のいずれかが有する開口部を介する場合がある。なお、絶縁体４９３は上記実施の形態の絶縁体１１８に相当するため、詳細については絶縁体１１８の記載を参酌することができる。 The insulator 493 passes through the region 507b which is one of the source and the drain of the transistor 3300 and reaches the conductor 474b, and the region 507a which is the other of the source and the drain of the transistor 3300 and the insulator 511. An opening reaching the conductor 514 that overlaps, an opening reaching the conductor 504 which is the gate electrode of the transistor 3300, and an opening reaching the conductor 474c through the region 507a which is the other of the source and the drain of the transistor 3300 And having. In addition, a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496d is embedded in each opening. Note that each opening may further pass through an opening included in any of the components such as the transistor 3300. Note that since the insulator 493 corresponds to the insulator 118 in the above embodiment, the description of the insulator 118 can be referred to for details.
また、絶縁体４９４は、導電体４９６ａに達する開口部と、導電体４９６ｂに達する開口部と、導電体４９６ｃに達する開口部と、導電体４９６ｄに達する開口部と、を有する。また、開口部には、それぞれ導電体４９８ａ、導電体４９８ｂまたは導電体４９８ｃが埋め込まれている。 The insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b, an opening reaching the conductor 496c, and an opening reaching the conductor 496d. In addition, a conductor 498a, a conductor 498b, or a conductor 498c is embedded in each opening.
絶縁体４６４、絶縁体４６６、絶縁体４６８、絶縁体４８９、絶縁体４９３または絶縁体４９４の一以上は、水素などの不純物および酸素をブロックする機能を有する絶縁体を有することが好ましい。トランジスタ３３００の近傍に、水素などの不純物および酸素をブロックする機能を有する絶縁体を配置することによって、トランジスタ３３００の電気特性を安定にすることができる。 One or more of the insulator 464, the insulator 466, the insulator 468, the insulator 489, the insulator 493, or the insulator 494 preferably includes an insulator having a function of blocking impurities such as hydrogen and oxygen. When an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 3300, electrical characteristics of the transistor 3300 can be stabilized.
トランジスタ３２００のソースまたはドレインは、導電体４８０ｂと、導電体４７８ｂと、導電体４７６ａと、導電体４７４ｂと、導電体４９６ｃと、を介してトランジスタ３３００のソースまたはドレインの一方である領域５０７ｂと電気的に接続する。また、トランジスタ３２００のゲート電極である導電体４５４は、導電体４８０ｃと、導電体４７８ｃと、導電体４７６ｂと、導電体４７４ｃと、導電体４９６ｄと、を介してトランジスタ３３００のソースまたはドレインの他方である領域５０７ａと電気的に接続する。 The source or the drain of the transistor 3200 is electrically connected to the region 507b which is one of the source and the drain of the transistor 3300 through the conductor 480b, the conductor 478b, the conductor 476a, the conductor 474b, and the conductor 496c. Connect. The conductor 454 that is a gate electrode of the transistor 3200 includes the other of the source and the drain of the transistor 3300 through the conductor 480c, the conductor 478c, the conductor 476b, the conductor 474c, and the conductor 496d. Is electrically connected to the region 507a.
容量素子３４００は、トランジスタ３３００のソースまたはドレインの他方である領域５０７ａと、導電体５１４と、絶縁体５１１、を有する。なお、絶縁体５１１は、トランジスタ３３００のゲート絶縁体として機能する絶縁体と同一工程を経て形成できるため、生産性を高めることができて好ましい場合がある。また、導電体５１４として、トランジスタ３３００のゲート電極として機能する導電体５０４と同一工程を経て形成した層を用いると、生産性を高めることができて好ましい場合がある。 The capacitor 3400 includes a region 507a which is the other of the source and the drain of the transistor 3300, a conductor 514, and an insulator 511. Note that since the insulator 511 can be formed through the same process as the insulator functioning as the gate insulator of the transistor 3300, productivity may be improved, which may be preferable. In addition, when the layer formed through the same step as the conductor 504 functioning as the gate electrode of the transistor 3300 is used as the conductor 514, productivity may be increased, which may be preferable.
そのほかの構造については、適宜図１２などについての記載を参酌することができる。 For other structures, the description of FIG. 12 and the like can be referred to as appropriate.
なお、図１７に示す半導体装置は、図１６に示した半導体装置のトランジスタ３２００の構造が異なるのみである。よって、図１７に示す半導体装置については、図１６に示した半導体装置の記載を参酌する。具体的には、図１７に示す半導体装置は、トランジスタ３２００がＦｉｎ型である場合を示している。Ｆｉｎ型であるトランジスタ３２００については、図１３に示したトランジスタ２２００の記載を参照する。なお、図１３では、トランジスタ２２００がｐチャネル型トランジスタである場合について説明したが、トランジスタ３２００がｎチャネル型トランジスタであっても構わない。 Note that the semiconductor device illustrated in FIG. 17 is different only in the structure of the transistor 3200 of the semiconductor device illustrated in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 16 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 17 illustrates the case where the transistor 3200 is a Fin type. For the Fin-type transistor 3200, the description of the transistor 2200 illustrated in FIGS. Note that although FIG. 13 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.
また、図１８に示す半導体装置は、図１６に示した半導体装置のトランジスタ３２００の構造が異なるのみである。よって、図１８に示す半導体装置については、図１６に示した半導体装置の記載を参酌する。具体的には、図１８に示す半導体装置は、トランジスタ３２００がＳＯＩ基板である半導体基板４５０に設けられた場合を示している。ＳＯＩ基板である半導体基板４５０に設けられたトランジスタ３２００については、図１４に示したトランジスタ２２００の記載を参照する。なお、図１４では、トランジスタ２２００がｐチャネル型トランジスタである場合について説明したが、トランジスタ３２００がｎチャネル型トランジスタであっても構わない。 Further, the semiconductor device illustrated in FIG. 18 is different only in the structure of the transistor 3200 of the semiconductor device illustrated in FIG. Therefore, for the semiconductor device illustrated in FIG. 18, the description of the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 18 illustrates the case where the transistor 3200 is provided over a semiconductor substrate 450 which is an SOI substrate. For the transistor 3200 provided over the semiconductor substrate 450 which is an SOI substrate, the description of the transistor 2200 illustrated in FIG. 14 is referred to. Note that although FIG. 14 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.
＜記憶装置２＞
図１５（Ｂ）に示す半導体装置は、トランジスタ３２００を有さない点で図１５（Ａ）に示した半導体装置と異なる。この場合も図１５（Ａ）に示した半導体装置と同様の動作により情報の書き込みおよび保持動作が可能である。 <Storage device 2>
The semiconductor device illustrated in FIG. 15B is different from the semiconductor device illustrated in FIG. 15A in that the transistor 3200 is not provided. In this case as well, information writing and holding operations can be performed by operations similar to those of the semiconductor device illustrated in FIG.
図１５（Ｂ）に示す半導体装置における、情報の読み出しについて説明する。トランジスタ３３００が導通状態になると、浮遊状態である第３の配線３００３と容量素子３４００とが導通し、第３の配線３００３と容量素子３４００の間で電荷が再分配される。その結果、第３の配線３００３の電位が変化する。第３の配線３００３の電位の変化量は、容量素子３４００の電極の一方の電位（または容量素子３４００に蓄積された電荷）によって、異なる値をとる。 Information reading in the semiconductor device illustrated in FIG. 15B is described. When the transistor 3300 is turned on, the floating third wiring 3003 and the capacitor 3400 are turned on, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on one potential of the electrode of the capacitor 3400 (or charge accumulated in the capacitor 3400).
例えば、容量素子３４００の電極の一方の電位をＶ、容量素子３４００の容量をＣ、第３の配線３００３が有する容量成分をＣＢ、電荷が再分配される前の第３の配線３００３の電位をＶＢ０とすると、電荷が再分配された後の第３の配線３００３の電位は、（ＣＢ×ＶＢ０＋ＣＶ）／（ＣＢ＋Ｃ）となる。したがって、メモリセルの状態として、容量素子３４００の電極の一方の電位がＶ１とＶ０（Ｖ１＞Ｖ０）の２つの状態をとるとすると、電位Ｖ１を保持している場合の第３の配線３００３の電位（＝（ＣＢ×ＶＢ０＋ＣＶ１）／（ＣＢ＋Ｃ））は、電位Ｖ０を保持している場合の第３の配線３００３の電位（＝（ＣＢ×ＶＢ０＋ＣＶ０）／（ＣＢ＋Ｃ））よりも高くなることがわかる。 For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before the charge is redistributed. Assuming VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + CV) / (CB + C). Therefore, when the potential of one of the electrodes of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. It can be seen that the potential (= (CB × VB0 + CV1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= (CB × VB0 + CV0) / (CB + C)). .
そして、第３の配線３００３の電位を所定の電位と比較することで、情報を読み出すことができる。 Then, information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.
この場合、メモリセルを駆動させるための駆動回路に上記第１の半導体が適用されたトランジスタを用い、トランジスタ３３００として第２の半導体が適用されたトランジスタを駆動回路上に積層して配置する構成とすればよい。 In this case, a transistor to which the first semiconductor is applied is used as a driver circuit for driving the memory cell, and a transistor to which the second semiconductor is applied is stacked over the driver circuit as the transistor 3300. do it.
以上に示した半導体装置は、酸化物半導体を用いたオフ電流の小さいトランジスタを適用することで、長期にわたって記憶内容を保持することが可能となる。つまり、リフレッシュ動作が不要となるか、またはリフレッシュ動作の頻度を極めて低くすることが可能となるため、消費電力の低い半導体装置を実現することができる。また、電力の供給がない場合（ただし、電位は固定されていることが好ましい）であっても、長期にわたって記憶内容を保持することが可能である。 The semiconductor device described above can hold stored data for a long time by using a transistor with an off-state current that includes an oxide semiconductor. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be extremely low, so that a semiconductor device with low power consumption can be realized. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).
また、該半導体装置は、情報の書き込みに高い電圧が不要であるため、素子の劣化が起こりにくい。例えば、従来の不揮発性メモリのように、フローティングゲートへの電子の注入や、フローティングゲートからの電子の引き抜きを行わないため、絶縁体の劣化といった問題が生じない。即ち、本発明の一態様に係る半導体装置は、従来の不揮発性メモリで問題となっている書き換え可能回数に制限はなく、信頼性が飛躍的に向上した半導体装置である。さらに、トランジスタの導通状態、非導通状態によって、情報の書き込みが行われるため、高速な動作が可能となる。 In addition, since the semiconductor device does not require a high voltage for writing information, the element hardly deteriorates. For example, unlike the conventional nonvolatile memory, since electrons are not injected into the floating gate and electrons are not extracted from the floating gate, there is no problem of deterioration of the insulator. In other words, the semiconductor device according to one embodiment of the present invention is a semiconductor device in which the number of rewritable times which is a problem in the conventional nonvolatile memory is not limited and the reliability is drastically improved. Further, since data is written depending on the conductive state and non-conductive state of the transistor, high-speed operation is possible.
＜記憶装置３＞
図１５（Ａ）に示す半導体装置（記憶装置）の変形例について、図１９に示す回路図を用いて説明する。 <Storage device 3>
A modification of the semiconductor device (memory device) illustrated in FIG. 15A is described with reference to a circuit diagram illustrated in FIG.
図１９に示す半導体装置は、トランジスタ４１００乃至トランジスタ４４００と、容量素子４５００および容量素子４６００と、を有する。ここでトランジスタ４１００は、上述のトランジスタ３２００と同様のトランジスタを用いることができ、トランジスタ４２００乃至４４００は、上述のトランジスタ３３００と同様のトランジスタを用いることができる。なお、図１９に示す半導体装置は、図１９では図示を省略したが、マトリクス状に複数設けられる。図１９に示す半導体装置は、配線４００１、配線４００３、配線４００５乃至４００９に与える信号又は電位に従って、データ電圧の書き込み、読み出しを制御することができる。 A semiconductor device illustrated in FIG. 19 includes transistors 4100 to 4400, a capacitor 4500, and a capacitor 4600. Here, the transistor 4100 can be a transistor similar to the above-described transistor 3200, and the transistors 4200 to 4400 can be the same transistor as the above-described transistor 3300. Note that although not shown in FIG. 19, a plurality of semiconductor devices illustrated in FIG. 19 are provided in a matrix. The semiconductor device illustrated in FIG. 19 can control writing and reading of a data voltage in accordance with a signal or a potential supplied to the wiring 4001, the wiring 4003, and the wirings 4005 to 4009.
トランジスタ４１００のソース又はドレインの一方は、配線４００３に接続される。トランジスタ４１００のソース又はドレインの他方は、配線４００１に接続される。なお図１９では、トランジスタ４１００の導電型をｐチャネル型として示すが、ｎチャネル型でもよい。 One of a source and a drain of the transistor 4100 is connected to the wiring 4003. The other of the source and the drain of the transistor 4100 is connected to the wiring 4001. Note that although the conductivity type of the transistor 4100 is shown as a p-channel type in FIG. 19, it may be an n-channel type.
図１９に示す半導体装置は、２つのデータ保持部を有する。例えば第１のデータ保持部は、ノードＦＧ１に接続されるトランジスタ４４００のソース又はドレインの一方、容量素子４６００の一方の電極、およびトランジスタ４２００のソース又はドレインの一方の間で電荷を保持する。また、第２のデータ保持部は、ノードＦＧ２に接続されるトランジスタ４１００のゲート、トランジスタ４２００のソース又はドレインの他方、トランジスタ４３００のソース又はドレインの一方、および容量素子４５００の一方の電極の間で電荷を保持する。 The semiconductor device illustrated in FIG. 19 includes two data holding units. For example, the first data holding portion holds charge between one of a source and a drain of the transistor 4400 connected to the node FG1, one electrode of the capacitor 4600, and one of the source and the drain of the transistor 4200. The second data holding portion is between the gate of the transistor 4100 connected to the node FG2, the other of the source and the drain of the transistor 4200, one of the source and the drain of the transistor 4300, and one electrode of the capacitor 4500. Holds a charge.
トランジスタ４３００のソース又はドレインの他方は、配線４００３に接続される。トランジスタ４４００のソース又はドレインの他方は、配線４００１に接続される。トランジスタ４４００のゲートは、配線４００５に接続される。トランジスタ４２００のゲートは、配線４００６に接続される。トランジスタ４３００のゲートは、配線４００７に接続される。容量素子４６００の他方の電極は、配線４００８に接続される。容量素子４５００の他方の電極は、配線４００９に接続される。 The other of the source and the drain of the transistor 4300 is connected to the wiring 4003. The other of the source and the drain of the transistor 4400 is connected to the wiring 4001. A gate of the transistor 4400 is connected to the wiring 4005. A gate of the transistor 4200 is connected to the wiring 4006. A gate of the transistor 4300 is connected to the wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of the capacitor 4500 is connected to the wiring 4009.
トランジスタ４２００乃至４４００は、データ電圧の書き込みと電荷の保持を制御するスイッチとしての機能を有する。なおトランジスタ４２００乃至４４００は、非導通状態においてソースとドレインとの間を流れる電流（オフ電流）が低いトランジスタが用いられることが好適である。オフ電流が少ないトランジスタとしては、チャネル形成領域に酸化物半導体を有するトランジスタ（ＯＳトランジスタ）であることが好ましい。ＯＳトランジスタは、オフ電流が低い、シリコンを有するトランジスタと重ねて作製できる等の利点がある。なお図１９では、トランジスタ４２００乃至１４の導電型をｎチャネル型として示すが、ｐチャネル型でもよい。 The transistors 4200 to 4400 function as switches for controlling writing of data voltages and holding of electric charges. Note that as the transistors 4200 to 4400, transistors with low current (off-state current) flowing between the source and the drain in a non-conduction state are preferably used. The transistor with low off-state current is preferably a transistor having an oxide semiconductor in a channel formation region (OS transistor). An OS transistor has advantages such as low off-state current and that it can be formed over a transistor including silicon. Note that although the conductivity types of the transistors 4200 to 14 are illustrated as n-channel types in FIG. 19, they may be p-channel types.
トランジスタ４２００およびトランジスタ４３００と、トランジスタ４４００とは、酸化物半導体を用いたトランジスタであっても別層に設けることが好ましい。すなわち、図１９に示す半導体装置は、図１９に示すように、トランジスタ４１００を有する第１の層４０２１と、トランジスタ４２００およびトランジスタ４３００を有する第２の層４０２２と、トランジスタ４４００を有する第３の層４０２３と、で構成されることが好ましい。トランジスタを有する層を積層して設けることで、回路面積を縮小することができ、半導体装置の小型化を図ることができる。 The transistor 4200, the transistor 4300, and the transistor 4400 are preferably provided in different layers even when a transistor including an oxide semiconductor is used. That is, as illustrated in FIG. 19, the semiconductor device illustrated in FIG. 19 includes a first layer 4021 including a transistor 4100, a second layer 4022 including a transistor 4200 and a transistor 4300, and a third layer including a transistor 4400. 4023. By stacking layers including transistors, the circuit area can be reduced and the semiconductor device can be downsized.
次いで、図１９に示す半導体装置への情報の書き込み動作について説明する。 Next, an operation of writing information to the semiconductor device illustrated in FIG. 19 is described.
最初に、ノードＦＧ１に接続されるデータ保持部へのデータ電圧の書き込み動作（以下、書き込み動作１とよぶ。）について説明する。なお、以下において、ノードＦＧ１に接続されるデータ保持部に書きこむデータ電圧をＶＤ１とし、トランジスタ４１００の閾値電圧をＶｔｈとする。 First, a data voltage write operation (hereinafter referred to as a write operation 1) to the data holding portion connected to the node FG1 will be described. Note that in the following description, the data voltage written to the data holding portion connected to the node FG1 is V D1, and the threshold voltage of the transistor 4100 is Vth.
書き込み動作１では、配線４００３をＶＤ１とし、配線４００１を接地電位とした後に、電気的に浮遊状態とする。また配線４００５、４００６をハイレベルにする。また配線４００７乃至４００９をローレベルにする。すると、電気的に浮遊状態にあるノードＦＧ２の電位が上昇し、トランジスタ４１００に電流が流れる。電流が流れることで、配線４００１の電位が上昇する。またトランジスタ４４００、トランジスタ４２００が導通状態となる。そのため、配線４００１の電位の上昇につれて、ノードＦＧ１、ＦＧ２の電位が上昇する。ノードＦＧ２の電位が上昇し、トランジスタ４１００でゲートとソースとの間の電圧（Ｖｇｓ）がトランジスタ４１００の閾値電圧Ｖｔｈになると、トランジスタ４１００を流れる電流が小さくなる。そのため、配線４００１、ノードＦＧ１、ＦＧ２の電位の上昇は止まり、ＶＤ１からＶｔｈだけ下がった「ＶＤ１−Ｖｔｈ」で一定となる。 In the writing operation 1, after the wiring 4003 is set to V D1 and the wiring 4001 is set to the ground potential, the wiring 4001 is electrically floated. In addition, the wirings 4005 and 4006 are set to a high level. In addition, the wirings 4007 to 4009 are set to a low level. Then, the potential of the node FG2 which is in an electrically floating state is increased, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4001 increases. In addition, the transistors 4400 and 4200 are turned on. Therefore, the potentials of the nodes FG1 and FG2 increase as the potential of the wiring 4001 increases. When the potential of the node FG2 rises and the voltage (Vgs) between the gate and the source in the transistor 4100 becomes the threshold voltage Vth of the transistor 4100, the current flowing through the transistor 4100 decreases. Therefore, the potential increase of the wiring 4001 and the nodes FG1 and FG2 stops and becomes constant at “V D1 −Vth” which is lower than V D1 by Vth.
つまり、配線４００３に与えたＶＤ１は、トランジスタ４１００に電流が流れることで、配線４００１に与えられ、ノードＦＧ１、ＦＧ２の電位が上昇する。電位の上昇によって、ノードＦＧ２の電位が「ＶＤ１−Ｖｔｈ」となると、トランジスタ４１００のＶｇｓがＶｔｈとなるため、電流が止まる。 That is, V D1 applied to the wiring 4003 is supplied to the wiring 4001 when current flows through the transistor 4100, so that the potentials of the nodes FG1 and FG2 are increased. When the potential of the node FG2 becomes “V D1 −Vth” due to the rise in potential, Vgs of the transistor 4100 becomes Vth, so that the current stops.
次に、ノードＦＧ２に接続されるデータ保持部へのデータ電圧の書き込み動作（以下、書き込み動作２とよぶ。）について説明する。なお、ノードＦＧ２に接続されるデータ保持部に書きこむデータ電圧をＶＤ２として説明する。 Next, a data voltage writing operation (hereinafter referred to as writing operation 2) to the data holding portion connected to the node FG2 will be described. Incidentally, illustrating a data voltage to be written to the data holding unit connected to the node FG2 as V D2.
書き込み動作２では、配線４００１をＶＤ２とし、配線４００３を接地電位とした後に、電気的に浮遊状態とする。また配線４００７をハイレベルにする。また配線４００５、４００６、４００８、４００９をローレベルにする。トランジスタ４３００を導通状態として配線４００３をローレベルにする。そのため、ノードＦＧ２の電位もローレベルにまで低下し、トランジスタ４１００に電流が流れる。電流が流れることで、配線４００３の電位が上昇する。またトランジスタ４３００が導通状態となる。そのため、配線４００３の電位の上昇につれて、ノードＦＧ２の電位が上昇する。ノードＦＧ２の電位が上昇し、トランジスタ４１００でＶｇｓがトランジスタ４１００のＶｔｈになると、トランジスタ４１００を流れる電流が小さくなる。そのため、配線４００３、ＦＧ２の電位の上昇は止まり、ＶＤ２からＶｔｈだけ下がった「ＶＤ２−Ｖｔｈ」で一定となる。 In the write operation 2, after the wiring 4001 is set to V D2 and the wiring 4003 is set to the ground potential, the wiring 4001 is electrically floated. Further, the wiring 4007 is set to a high level. In addition, the wirings 4005, 4006, 4008, and 4009 are set to a low level. The transistor 4300 is turned on and the wiring 4003 is set to a low level. Therefore, the potential of the node FG2 also decreases to a low level, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 increases. In addition, the transistor 4300 is turned on. Therefore, the potential of the node FG2 increases as the potential of the wiring 4003 increases. When the potential of the node FG2 rises and Vgs becomes Vth of the transistor 4100 in the transistor 4100, the current flowing through the transistor 4100 decreases. Therefore, the increase in the potentials of the wirings 4003 and FG2 stops and becomes constant at “V D2 −Vth”, which is lower than V D2 by Vth.
つまり、配線４００１に与えたＶＤ２は、トランジスタ４１００に電流が流れることで、配線４００３に与えられ、ノードＦＧ２の電位が上昇する。電位の上昇によって、ノードＦＧ２の電位が「ＶＤ２−Ｖｔｈ」となると、トランジスタ４１００のＶｇｓがＶｔｈとなるため、電流が止まる。このとき、ノードＦＧ１の電位は、トランジスタ４２００、４４００共に非導通状態であり、書き込み動作１で書きこんだ「ＶＤ１−Ｖｔｈ」が保持される。 That is, V D2 applied to the wiring 4001 is supplied to the wiring 4003 when a current flows through the transistor 4100, so that the potential of the node FG2 increases. When the potential of the node FG2 becomes “V D2 −Vth” due to the rise in potential, Vgs of the transistor 4100 becomes Vth, so that the current stops. At this time, the potential of the node FG1 is non-conductive in the transistors 4200 and 4400, and “V D1 −Vth” written in the writing operation 1 is held.
図１９に示す半導体装置では、複数のデータ保持部にデータ電圧を書きこんだのち、配線４００９をハイレベルにして、ノードＦＧ１、ＦＧ２の電位を上昇させる。そして、各トランジスタを非導通状態として、電荷の移動をなくし、書きこんだデータ電圧を保持する。 In the semiconductor device illustrated in FIG. 19, after writing data voltages to a plurality of data holding portions, the wiring 4009 is set to a high level and the potentials of the nodes FG1 and FG2 are increased. Then, each transistor is brought into a non-conducting state to eliminate the movement of electric charges and to hold the written data voltage.
以上説明したノードＦＧ１、ＦＧ２へのデータ電圧の書き込み動作によって、複数のデータ保持部にデータ電圧を保持させることができる。なお書きこまれる電位として、「ＶＤ１−Ｖｔｈ」や「ＶＤ２−Ｖｔｈ」を一例として挙げて説明したが、これらは多値のデータに対応するデータ電圧である。そのため、それぞれのデータ保持部で４ビットのデータを保持する場合、１６値の「ＶＤ１−Ｖｔｈ」や「ＶＤ２−Ｖｔｈ」を取り得る。 By the data voltage writing operation to the nodes FG1 and FG2 described above, the data voltages can be held in the plurality of data holding units. Note that although “V D1 −Vth” and “V D2 −Vth” have been described as examples of potentials to be written, these are data voltages corresponding to multi-value data. Therefore, when 4-bit data is held in each data holding unit, 16 values of “V D1 −Vth” and “V D2 −Vth” can be taken.
次いで、図１９に示す半導体装置からの情報の読み出し動作について説明する。 Next, an operation of reading information from the semiconductor device illustrated in FIG. 19 is described.
最初に、ノードＦＧ２に接続されるデータ保持部へのデータ電圧の読み出し動作（以下、読み出し動作１とよぶ。）について説明する。 First, a data voltage read operation (hereinafter referred to as a read operation 1) to a data holding portion connected to the node FG2 will be described.
読み出し動作１では、プリチャージを行ってから電気的に浮遊状態とした、配線４００３を放電させる。配線４００５乃至４００８をローレベルにする。また、配線４００９をローレベルとして、電気的に浮遊状態にあるノードＦＧ２の電位を「ＶＤ２−Ｖｔｈ」とする。ノードＦＧ２の電位が下がることで、トランジスタ４１００に電流が流れる。電流が流れることで、電気的に浮遊状態の配線４００３の電位が低下する。配線４００３の電位の低下につれて、トランジスタ４１００のＶｇｓが小さくなる。トランジスタ４１００のＶｇｓがトランジスタ４１００のＶｔｈになると、トランジスタ４１００を流れる電流が小さくなる。すなわち、配線４００３の電位が、ノードＦＧ２の電位「ＶＤ２−Ｖｔｈ」からＶｔｈだけ大きい値である「ＶＤ２」となる。この配線４００３の電位は、ノードＦＧ２に接続されるデータ保持部のデータ電圧に対応する。読み出されたアナログ値のデータ電圧はＡ／Ｄ変換を行い、ノードＦＧ２に接続されるデータ保持部のデータを取得する。 In the reading operation 1, the wiring 4003 that has been electrically floated after precharging is discharged. The wirings 4005 to 4008 are set to a low level. Further, the wiring 4009 is set to a low level, and the potential of the node FG2 in an electrically floating state is set to “V D2 −Vth”. A current flows through the transistor 4100 when the potential of the node FG2 is decreased. When the current flows, the potential of the electrically floating wiring 4003 is decreased. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, a current flowing through the transistor 4100 is reduced. That is, the potential of the wiring 4003 becomes “V D2 ” that is a value larger by Vth than the potential “V D2 −Vth” of the node FG2. The potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG2. The read data voltage of the analog value is subjected to A / D conversion, and data of a data holding unit connected to the node FG2 is acquired.
つまり、プリチャージ後の配線４００３を浮遊状態とし、配線４００９の電位をハイレベルからローレベルに切り替えることで、トランジスタ４１００に電流が流れる。電流が流れることで、浮遊状態にあった配線４００３の電位は低下して「ＶＤ２」となる。トランジスタ４１００では、ノードＦＧ２の「ＶＤ２−Ｖｔｈ」との間のＶｇｓがＶｔｈとなるため、電流が止まる。そして、配線４００３には、書き込み動作２で書きこんだ「ＶＤ２」が読み出される。 In other words, a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level. When the current flows, the potential of the wiring 4003 in the floating state is decreased to “V D2 ”. In the transistor 4100, Vgs between “V D2 −Vth” of the node FG2 becomes Vth, so that the current stops. Then, “V D2 ” written in the writing operation 2 is read out to the wiring 4003.
ノードＦＧ２に接続されるデータ保持部のデータを取得したら、トランジスタ４３００を導通状態として、ノードＦＧ２の「ＶＤ２−Ｖｔｈ」を放電させる。 When data in the data holding portion connected to the node FG2 is acquired, the transistor 4300 is turned on to discharge “V D2 −Vth” of the node FG2.
次に、ノードＦＧ１に保持される電荷をノードＦＧ２に分配し、ノードＦＧ１に接続されるデータ保持部のデータ電圧を、ノードＦＧ２に接続されるデータ保持部に移す。ここで、配線４００１、４００３をローレベルとする。配線４００６をハイレベルにする。また、配線４００５、配線４００７乃至４００９をローレベルにする。トランジスタ４２００が導通状態となることで、ノードＦＧ１の電荷が、ノードＦＧ２との間で分配される。 Next, the charge held in the node FG1 is distributed to the node FG2, and the data voltage of the data holding unit connected to the node FG1 is transferred to the data holding unit connected to the node FG2. Here, the wirings 4001 and 4003 are set to a low level. The wiring 4006 is set to a high level. In addition, the wiring 4005 and the wirings 4007 to 4009 are set to a low level. When the transistor 4200 is turned on, the charge of the node FG1 is distributed to and from the node FG2.
ここで、電荷の分配後の電位は、書きこんだ電位「ＶＤ１−Ｖｔｈ」から低下する。そのため、容量素子４６００の容量値は、容量素子４５００の容量値よりも大きくしておくことが好ましい。あるいは、ノードＦＧ１に書きこむ電位「ＶＤ１−Ｖｔｈ」は、同じデータを表す電位「ＶＤ２−Ｖｔｈ」よりも大きくすることが好ましい。このように、容量値の比を変えること、予め書きこむ電位を大きくしておくことで、電荷の分配後の電位の低下を抑制することができる。電荷の分配による電位の変動については、後述する。 Here, the potential after the charge distribution is lowered from the written potential “V D1 −Vth”. Therefore, the capacitance value of the capacitor 4600 is preferably larger than the capacitance value of the capacitor 4500. Alternatively, the potential “V D1 −Vth” written to the node FG1 is preferably higher than the potential “V D2 −Vth” representing the same data. In this way, by changing the ratio of the capacitance values and increasing the potential to be written in advance, it is possible to suppress a decrease in potential after the charge is distributed. The fluctuation of the potential due to the charge distribution will be described later.
次に、ノードＦＧ１に接続されるデータ保持部へのデータ電圧の読み出し動作（以下、読み出し動作２とよぶ。）について説明する。 Next, a data voltage read operation (hereinafter referred to as read operation 2) to the data holding portion connected to the node FG1 will be described.
読み出し動作２では、プリチャージを行ってから電気的に浮遊状態とした、配線４００３を放電させる。配線４００５乃至４００８をローレベルにする。また、配線４００９は、プリチャージ時にハイレベルとして、その後ローレベルとする。配線４００９をローレベルとすることで、電気的に浮遊状態にあるノードＦＧ２を電位「ＶＤ１−Ｖｔｈ」とする。ノードＦＧ２の電位が下がることで、トランジスタ４１００に電流が流れる。電流が流れることで、電気的に浮遊状態の配線４００３の電位が低下する。配線４００３の電位の低下につれて、トランジスタ４１００のＶｇｓが小さくなる。トランジスタ４１００のＶｇｓがトランジスタ４１００のＶｔｈになると、トランジスタ４１００を流れる電流が小さくなる。すなわち、配線４００３の電位が、ノードＦＧ２の電位「ＶＤ１−Ｖｔｈ」からＶｔｈだけ大きい値である「ＶＤ１」となる。この配線４００３の電位は、ノードＦＧ１に接続されるデータ保持部のデータ電圧に対応する。読み出されたアナログ値のデータ電圧はＡ／Ｄ変換を行い、ノードＦＧ１に接続されるデータ保持部のデータを取得する。以上が、ノードＦＧ１に接続されるデータ保持部へのデータ電圧の読み出し動作である。 In the reading operation 2, the wiring 4003 that has been electrically floated after precharging is discharged. The wirings 4005 to 4008 are set to a low level. Further, the wiring 4009 is set to a high level at the time of precharging and then set to a low level. By setting the wiring 4009 to a low level, the node FG2 in an electrically floating state is set to a potential “V D1 −Vth”. A current flows through the transistor 4100 when the potential of the node FG2 is decreased. When the current flows, the potential of the electrically floating wiring 4003 is decreased. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, a current flowing through the transistor 4100 is reduced. That is, the potential of the wiring 4003 becomes “V D1 ” that is a value larger by Vth than the potential “V D1 −Vth” of the node FG2. The potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG1. The read data voltage of the analog value performs A / D conversion, and acquires data of the data holding unit connected to the node FG1. The above is the data voltage reading operation to the data holding portion connected to the node FG1.
つまり、プリチャージ後の配線４００３を浮遊状態とし、配線４００９の電位をハイレベルからローレベルに切り替えることで、トランジスタ４１００に電流が流れる。電流が流れることで、浮遊状態にあった配線４００３の電位は低して「ＶＤ１」となる。トランジスタ４１００では、ノードＦＧ２の「ＶＤ１−Ｖｔｈ」との間のＶｇｓがＶｔｈとなるため、電流が止まる。そして、配線４００３には、書き込み動作１で書きこんだ「ＶＤ１」が読み出される。 In other words, a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level. When the current flows, the potential of the wiring 4003 in the floating state is lowered to “V D1 ”. In the transistor 4100, the current stops because Vgs between the node FG2 and “V D1 −Vth” becomes Vth. Then, “V D1 ” written in the writing operation 1 is read out to the wiring 4003.
以上説明したノードＦＧ１、ＦＧ２からのデータ電圧の読み出し動作によって、複数のデータ保持部からデータ電圧を読み出すことができる。例えば、ノードＦＧ１およびノードＦＧ２にそれぞれ４ビット（１６値）のデータを保持することで計８ビット（２５６値）のデータを保持することができる。また、図１９においては、第１の層４０２１乃至第３の層４０２３からなる構成としたが、さらに層を形成することによって、半導体装置の面積を増大させず記憶容量の増加を図ることができる。 The data voltage can be read from the plurality of data holding units by the data voltage reading operation from the nodes FG1 and FG2 described above. For example, a total of 8 bits (256 values) of data can be held by holding 4 bits (16 values) of data in the nodes FG1 and FG2, respectively. In FIG. 19, the first layer 4021 to the third layer 4023 are used. However, by forming further layers, the storage capacity can be increased without increasing the area of the semiconductor device. .
なお読み出される電位は、書きこんだデータ電圧よりＶｔｈだけ大きい電圧として読み出すことができる。そのため、書き込み動作で書きこんだ「ＶＤ１−Ｖｔｈ」や「ＶＤ２−Ｖｔｈ」のＶｔｈを相殺して読み出す構成とすることができる。その結果、メモリセルあたりの記憶容量を向上させるとともに、読み出されるデータを正しいデータに近づけることができるため、データの信頼性に優れたものとすることができる。 Note that the read potential can be read as a voltage higher than the written data voltage by Vth. Therefore, it is possible to adopt a configuration in which Vth of “V D1 −Vth” or “V D2 −Vth” written by the write operation is canceled and read. As a result, the storage capacity per memory cell can be improved and the read data can be brought close to the correct data, so that the data reliability can be improved.
また、図２０に図１９に対応する半導体装置の断面図を示す。図２０に示す半導体装置は、トランジスタ４１００乃至トランジスタ４４００と、容量素子４５００および容量素子４６００と、を有する。ここで、トランジスタ４１００は第１の層４０２１に形成され、トランジスタ４２００、４３００、および容量素子４５００は第２の層４０２２に形成され、トランジスタ４４００および容量素子４６００は第３の層４０２３に形成される。 FIG. 20 is a cross-sectional view of the semiconductor device corresponding to FIG. The semiconductor device illustrated in FIG. 20 includes transistors 4100 to 4400, a capacitor 4500, and a capacitor 4600. Here, the transistor 4100 is formed in the first layer 4021, the transistors 4200 and 4300, and the capacitor 4500 are formed in the second layer 4022, and the transistor 4400 and the capacitor 4600 are formed in the third layer 4023. .
ここで、トランジスタ４２００乃至４４００としてはトランジスタ３３００の記載を、トランジスタ４１００としてはトランジスタ３２００の記載を参酌することができる。また、その他の配線、絶縁体等についても適宜図１６の記載を参酌することができる。 Here, the description of the transistor 3300 can be referred to as the transistors 4200 to 4400, and the description of the transistor 3200 can be referred to as the transistor 4100. The description of FIG. 16 can be referred to for other wirings, insulators, and the like as appropriate.
なお、図１６に示す半導体装置の容量素子３４００では導電層を基板に対して平行に設けて容量を形成する構成としたが、容量素子４５００、４６００では、トレンチ状に導電層を設けて、容量を形成する構成としている。このような構成とすることで、同じ占有面積であっても大きい容量値を確保することができる。 Note that the capacitor 3400 in the semiconductor device illustrated in FIG. 16 has a structure in which a conductive layer is provided in parallel to the substrate to form a capacitor. However, in the capacitor elements 4500 and 4600, a conductive layer is provided in a trench shape to It is set as the structure which forms. With such a configuration, a large capacitance value can be secured even with the same occupied area.
＜ＦＰＧＡ＞
また本発明の一態様は、ＦＰＧＡ（Ｆｉｅｌｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）などのＬＳＩにも適用可能である。 <FPGA>
One embodiment of the present invention can also be applied to an LSI such as an FPGA (Field Programmable Gate Array).
図２１（Ａ）には、ＦＰＧＡのブロック図の一例を示す。ＦＰＧＡは、ルーティングスイッチエレメント５２１と、ロジックエレメント５２２とによって構成される。また、ロジックエレメント５２２は、コンフィギュレーションメモリに記憶したコンフィギュレーションデータに応じて、組み合わせ回路の機能、または順序回路の機能といった論理回路の機能を切り替えることができる。 FIG. 21A illustrates an example of a block diagram of an FPGA. The FPGA includes a routing switch element 521 and a logic element 522. The logic element 522 can switch the function of the logic circuit such as the function of the combinational circuit or the function of the sequential circuit in accordance with the configuration data stored in the configuration memory.
図２１（Ｂ）は、ルーティングスイッチエレメント５２１の役割を説明するための模式図である。ルーティングスイッチエレメント５２１は、コンフィギュレーションメモリ５２３に記憶したコンフィギュレーションデータに応じて、ロジックエレメント５２２間の接続を切り替えることができる。なお図２１（Ｂ）では、スイッチを一つ示し、端子ＩＮと端子ＯＵＴの間の接続を切り替える様子を示しているが、実際には複数あるロジックエレメント５２２間にスイッチが設けられる。 FIG. 21B is a schematic diagram for explaining the role of the routing switch element 521. The routing switch element 521 can switch the connection between the logic elements 522 according to the configuration data stored in the configuration memory 523. Note that FIG. 21B illustrates one switch and illustrates a state where the connection between the terminal IN and the terminal OUT is switched; in practice, a switch is provided between the plurality of logic elements 522.
図２１（Ｃ）には、コンフィギュレーションメモリ５２３として機能する回路構成の一例を示す。コンフィギュレーションメモリ５２３は、ＯＳトランジスタで構成されるトランジスタＭ１１と、Ｓｉトランジスタで構成されるＭ１２と、によって構成される。ノードＦＮＳＷには、トランジスタＭ１１を介してコンフィギュレーションデータＤＳＷが与えられる。このコンフィギュレーションデータＤＳＷの電位は、トランジスタＭ１１を非導通状態とすることで、保持することができる。保持したコンフィギュレーションデータＤＳＷの電位によって、トランジスタＭ１２の導通状態が切り替えられ、端子ＩＮと端子ＯＵＴの間の接続を切り替えることができる。 FIG. 21C illustrates an example of a circuit configuration that functions as the configuration memory 523. The configuration memory 523 includes a transistor M11 configured by an OS transistor and M12 configured by a Si transistor. The node FN SW, given the configuration data D SW through the transistor M11. The potential of the configuration data DSW can be held by turning off the transistor M11. The conduction state of the transistor M12 is switched by the held potential of the configuration data DSW , and the connection between the terminal IN and the terminal OUT can be switched.
図２１（Ｄ）は、ロジックエレメント５２２の役割を説明するための模式図である。ロジックエレメント５２２は、コンフィギュレーションメモリ５２７に記憶したコンフィギュレーションデータに応じて、端子ＯＵＴｍｅｍの電位を切り替えることができる。ルックアップテーブル５２４は、端子ＯＵＴｍｅｍの電位に応じて、端子ＩＮの信号を処理する組み合わせ回路の機能を切り替えることができる。またロジックエレメント５２２は、順序回路であるレジスタ５２５と、端子ＯＵＴの信号を切り替えるためのセレクタ５２６を有する。セレクタ５２６は、コンフィギュレーションメモリ５２７から出力される端子ＯＵＴｍｅｍの電位に応じて、ルックアップテーブル５２４の信号の出力か、レジスタ５２５の信号の出力か、を選択することができる。 FIG. 21D is a schematic diagram for explaining the role of the logic element 522. The logic element 522 can switch the potential of the terminal OUT mem in accordance with configuration data stored in the configuration memory 527. The look-up table 524 can switch the function of the combinational circuit that processes the signal of the terminal IN in accordance with the potential of the terminal OUT mem . The logic element 522 includes a register 525 which is a sequential circuit and a selector 526 for switching a signal of the terminal OUT. The selector 526 can select the output of the signal of the lookup table 524 or the output of the signal of the register 525 in accordance with the potential of the terminal OUT mem output from the configuration memory 527.
図２１（Ｅ）には、コンフィギュレーションメモリ５２７として機能する回路構成の一例を示す。コンフィギュレーションメモリ５２７は、ＯＳトランジスタで構成されるトランジスタＭ１３、Ｍ１４と、Ｓｉトランジスタで構成されるＭ１５、Ｍ１６と、によって構成される。ノードＦＮＬＥには、トランジスタＭ１３を介してコンフィギュレーションデータＤＬＥが与えられる。ノードＦＮＢＬＥには、トランジスタＭ１４を介してコンフィギュレーションデータＤＢＬＥが与えられる。コンフィギュレーションデータＤＢＬＥは、コンフィギュレーションデータＤＬＥの論理が反転した電位に相当する。このコンフィギュレーションデータＤＬＥ、コンフィギュレーションデータＤＢＬＥの電位は、トランジスタＭ１３、Ｍ１４を非導通状態とすることで、保持することができる。保持したコンフィギュレーションデータＤＬＥ、コンフィギュレーションデータＤＢＬＥの電位によって、トランジスタＭ１５またはトランジスタＭ１６の一方の導通状態が切り替えられ、端子ＯＵＴｍｅｍには電位ＶＤＤまたは電位ＶＳＳを与えることができる。 FIG. 21E illustrates an example of a circuit configuration that functions as the configuration memory 527. The configuration memory 527 includes transistors M13 and M14 configured by OS transistors and M15 and M16 configured by Si transistors. Configuration data D LE is supplied to the node FN LE via the transistor M13. The node FNB LE is supplied with configuration data DB LE via the transistor M14. The configuration data DB LE corresponds to a potential obtained by inverting the logic of the configuration data D LE . The potentials of the configuration data D LE and configuration data DB LE can be held by turning off the transistors M13 and M14. One conduction state of the transistor M15 or the transistor M16 is switched depending on the held configuration data D LE and configuration data DB LE , and the potential VDD or the potential VSS can be applied to the terminal OUT mem .
図２１（Ａ）乃至図２１（Ｅ）の構成に対して、上記実施の形態で説明した構成を適用することができる。例えばトランジスタＭ１２、Ｍ１５、Ｍ１６をＳｉトランジスタで構成し、トランジスタＭ１１、Ｍ１３、Ｍ１４をＯＳトランジスタで構成する。この場合、下層にあるＳｉトランジスタ間を接続する配線を低抵抗な導電材料で構成することができる。そのため、アクセス速度の向上、低消費電力化に優れた回路とすることができる。 The structure described in any of the above embodiments can be applied to the structures in FIGS. For example, the transistors M12, M15, and M16 are composed of Si transistors, and the transistors M11, M13, and M14 are composed of OS transistors. In this case, the wiring that connects the Si transistors in the lower layer can be made of a low-resistance conductive material. Therefore, a circuit excellent in improving access speed and reducing power consumption can be obtained.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態４）
本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した撮像装置の一例について説明する。 (Embodiment 4)
In this embodiment, an example of an imaging device using a transistor or the like according to one embodiment of the present invention will be described.
＜撮像装置の構成＞
図２２（Ａ）は、本発明の一態様に係る撮像装置２００の例を示す平面図である。撮像装置２００は、画素部２１０と、画素部２１０を駆動するための周辺回路２６０と、周辺回路２７０、周辺回路２８０と、周辺回路２９０と、を有する。画素部２１０は、ｐ行ｑ列（ｐおよびｑは２以上の整数）のマトリクス状に配置された複数の画素２１１を有する。周辺回路２６０、周辺回路２７０、周辺回路２８０および周辺回路２９０は、それぞれ複数の画素２１１に接続し、複数の画素２１１を駆動するための信号を供給する機能を有する。なお、本明細書等において、周辺回路２６０、周辺回路２７０、周辺回路２８０および周辺回路２９０などの全てを指して「周辺回路」または「駆動回路」と呼ぶ場合がある。例えば、周辺回路２６０は周辺回路の一部といえる。 <Configuration of imaging device>
FIG. 22A is a plan view illustrating an example of an imaging device 200 according to one embodiment of the present invention. The imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel unit 210 includes a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are connected to the plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211, respectively. Note that in this specification and the like, the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, the peripheral circuit 290, and the like are all referred to as “peripheral circuits” or “driving circuits” in some cases. For example, the peripheral circuit 260 can be said to be part of the peripheral circuit.
また、撮像装置２００は、光源２９１を有することが好ましい。光源２９１は、検出光Ｐ１を放射することができる。 The imaging apparatus 200 preferably includes a light source 291. The light source 291 can emit the detection light P1.
また、周辺回路は、少なくとも、論理回路、スイッチ、バッファ、増幅回路、または変換回路の１つを有する。また、周辺回路は、画素部２１０を形成する基板上に形成してもよい。また、周辺回路の一部または全部にＩＣチップ等の半導体装置を用いてもよい。なお、周辺回路は、周辺回路２６０、周辺回路２７０、周辺回路２８０および周辺回路２９０のいずれか一以上を省略してもよい。 The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. Further, the peripheral circuit may be formed on a substrate over which the pixel portion 210 is formed. Further, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that one or more of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be omitted from the peripheral circuit.
また、図２２（Ｂ）に示すように、撮像装置２００が有する画素部２１０において、画素２１１を傾けて配置してもよい。画素２１１を傾けて配置することにより、行方向および列方向の画素間隔（ピッチ）を短くすることができる。これにより、撮像装置２００における撮像の品質をより高めることができる。 In addition, as illustrated in FIG. 22B, in the pixel portion 210 included in the imaging device 200, the pixel 211 may be inclined. By arranging the pixels 211 at an angle, the pixel interval (pitch) in the row direction and the column direction can be shortened. Thereby, the quality of imaging in the imaging apparatus 200 can be further improved.
＜画素の構成例１＞
撮像装置２００が有する１つの画素２１１を複数の副画素２１２で構成し、それぞれの副画素２１２に特定の波長域の光を透過するフィルタ（カラーフィルタ）を組み合わせることで、カラー画像表示を実現するための情報を取得することができる。 <Pixel Configuration Example 1>
One pixel 211 included in the imaging apparatus 200 is configured by a plurality of sub-pixels 212, and a color image display is realized by combining each sub-pixel 212 with a filter (color filter) that transmits light in a specific wavelength range. Information can be acquired.
図２３（Ａ）は、カラー画像を取得するための画素２１１の一例を示す平面図である。図２３（Ａ）に示す画素２１１は、赤（Ｒ）の波長域の光を透過するカラーフィルタが設けられた副画素２１２（以下、「副画素２１２Ｒ」ともいう）、緑（Ｇ）の波長域の光を透過するカラーフィルタが設けられた副画素２１２（以下、「副画素２１２Ｇ」ともいう）および青（Ｂ）の波長域の光を透過するカラーフィルタが設けられた副画素２１２（以下、「副画素２１２Ｂ」ともいう）を有する。副画素２１２は、フォトセンサとして機能させることができる。 FIG. 23A is a plan view illustrating an example of a pixel 211 for acquiring a color image. A pixel 211 illustrated in FIG. 23A includes a sub-pixel 212 (hereinafter, also referred to as “sub-pixel 212R”) provided with a color filter that transmits light in the red (R) wavelength region, and a green (G) wavelength. A sub-pixel 212 (hereinafter also referred to as “sub-pixel 212G”) provided with a color filter that transmits light in the region and a sub-pixel 212 (hereinafter referred to as “color filter” that transmits light in the blue (B) wavelength region. , Also referred to as “sub-pixel 212B”. The sub-pixel 212 can function as a photosensor.
副画素２１２（副画素２１２Ｒ、副画素２１２Ｇ、および副画素２１２Ｂ）は、配線２３１、配線２４７、配線２４８、配線２４９、配線２５０と電気的に接続される。また、副画素２１２Ｒ、副画素２１２Ｇ、および副画素２１２Ｂは、それぞれが独立した配線２５３に接続している。また、本明細書等において、例えばｎ行目の画素２１１に接続された配線２４８および配線２４９を、それぞれ配線２４８［ｎ］および配線２４９［ｎ］と記載する。また、例えばｍ列目の画素２１１に接続された配線２５３を、配線２５３［ｍ］と記載する。なお、図２３（Ａ）において、ｍ列目の画素２１１が有する副画素２１２Ｒに接続する配線２５３を配線２５３［ｍ］Ｒ、副画素２１２Ｇに接続する配線２５３を配線２５３［ｍ］Ｇ、および副画素２１２Ｂに接続する配線２５３を配線２５３［ｍ］Ｂと記載している。副画素２１２は、上記配線を介して周辺回路と電気的に接続される。 The subpixel 212 (subpixel 212R, subpixel 212G, and subpixel 212B) is electrically connected to the wiring 231, the wiring 247, the wiring 248, the wiring 249, and the wiring 250. Further, the sub-pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 253. In this specification and the like, for example, the wiring 248 and the wiring 249 connected to the pixel 211 in the n-th row are referred to as a wiring 248 [n] and a wiring 249 [n], respectively. For example, the wiring 253 connected to the pixel 211 in the m-th column is referred to as a wiring 253 [m]. Note that in FIG. 23A, the wiring 253 connected to the subpixel 212R included in the pixel 211 in the m-th column is the wiring 253 [m] R, the wiring 253 connected to the subpixel 212G is the wiring 253 [m] G, and A wiring 253 connected to the subpixel 212B is described as a wiring 253 [m] B. The subpixel 212 is electrically connected to a peripheral circuit through the wiring.
また、撮像装置２００は、隣接する画素２１１の、同じ波長域の光を透過するカラーフィルタが設けられた副画素２１２同士がスイッチを介して電気的に接続する構成を有する。図２３（Ｂ）に、ｎ行（ｎは１以上ｐ以下の整数）ｍ列（ｍは１以上ｑ以下の整数）に配置された画素２１１が有する副画素２１２と、該画素２１１に隣接するｎ＋１行ｍ列に配置された画素２１１が有する副画素２１２の接続例を示す。図２３（Ｂ）において、ｎ行ｍ列に配置された副画素２１２Ｒと、ｎ＋１行ｍ列に配置された副画素２１２Ｒがスイッチ２０１を介して接続されている。また、ｎ行ｍ列に配置された副画素２１２Ｇと、ｎ＋１行ｍ列に配置された副画素２１２Ｇがスイッチ２０２を介して接続されている。また、ｎ行ｍ列に配置された副画素２１２Ｂと、ｎ＋１行ｍ列に配置された副画素２１２Ｂがスイッチ２０３を介して接続されている。 In addition, the imaging apparatus 200 has a configuration in which the sub-pixels 212 provided with color filters that transmit light in the same wavelength region of adjacent pixels 211 are electrically connected via a switch. In FIG. 23B, the sub-pixel 212 included in the pixel 211 arranged in n rows (n is an integer of 1 to p) and m columns (m is an integer of 1 to q) is adjacent to the pixel 211. A connection example of the sub-pixel 212 included in the pixel 211 arranged in n + 1 rows and m columns is shown. In FIG. 23B, a subpixel 212R arranged in n rows and m columns and a subpixel 212R arranged in n + 1 rows and m columns are connected via a switch 201. Further, the sub-pixel 212G arranged in n rows and m columns and the sub-pixel 212G arranged in n + 1 rows and m columns are connected via a switch 202. Further, the sub-pixel 212B arranged in n rows and m columns and the sub-pixel 212B arranged in n + 1 rows and m columns are connected via a switch 203.
なお、副画素２１２に用いるカラーフィルタは、赤（Ｒ）、緑（Ｇ）、青（Ｂ）に限定されず、それぞれシアン（Ｃ）、黄（Ｙ）およびマゼンダ（Ｍ）の光を透過するカラーフィルタを用いてもよい。１つの画素２１１に３種類の異なる波長域の光を検出する副画素２１２を設けることで、フルカラー画像を取得することができる。 Note that the color filter used for the sub-pixel 212 is not limited to red (R), green (G), and blue (B), and transmits cyan (C), yellow (Y), and magenta (M) light, respectively. A color filter may be used. A full-color image can be acquired by providing the sub-pixel 212 that detects light of three different wavelength ranges in one pixel 211.
または、それぞれ赤（Ｒ）、緑（Ｇ）および青（Ｂ）の光を透過するカラーフィルタが設けられた副画素２１２に加えて、黄（Ｙ）の光を透過するカラーフィルタが設けられた副画素２１２を有する画素２１１を用いてもよい。または、それぞれシアン（Ｃ）、黄（Ｙ）およびマゼンダ（Ｍ）の光を透過するカラーフィルタが設けられた副画素２１２に加えて、青（Ｂ）の光を透過するカラーフィルタが設けられた副画素２１２を有する画素２１１を用いてもよい。１つの画素２１１に４種類の異なる波長域の光を検出する副画素２１２を設けることで、取得した画像の色の再現性をさらに高めることができる。 Alternatively, in addition to the sub-pixel 212 provided with a color filter that transmits red (R), green (G), and blue (B) light, a color filter that transmits yellow (Y) light is provided. A pixel 211 having a sub-pixel 212 may be used. Alternatively, in addition to the sub-pixel 212 provided with a color filter that transmits cyan (C), yellow (Y), and magenta (M) light, a color filter that transmits blue (B) light is provided. A pixel 211 having a sub-pixel 212 may be used. By providing the sub-pixel 212 for detecting light of four different wavelength ranges in one pixel 211, the color reproducibility of the acquired image can be further enhanced.
また、例えば、図２３（Ａ）において、赤の波長域の光を検出する副画素２１２、緑の波長域の光を検出する副画素２１２、および青の波長域の光を検出する副画素２１２の画素数比（または受光面積比）は、１：１：１でなくても構わない。例えば、画素数比（受光面積比）を赤：緑：青＝１：２：１とするＢａｙｅｒ配列としてもよい。または、画素数比（受光面積比）を赤：緑：青＝１：６：１としてもよい。 Further, for example, in FIG. 23A, the sub-pixel 212 that detects light in the red wavelength region, the sub-pixel 212 that detects light in the green wavelength region, and the sub-pixel 212 that detects light in the blue wavelength region. The pixel number ratio (or the light receiving area ratio) may not be 1: 1: 1. For example, a Bayer array in which the pixel number ratio (light receiving area ratio) is red: green: blue = 1: 2: 1 may be used. Alternatively, the pixel number ratio (light receiving area ratio) may be red: green: blue = 1: 6: 1.
なお、画素２１１に設ける副画素２１２は１つでもよいが、２つ以上が好ましい。例えば、同じ波長域の光を検出する副画素２１２を２つ以上設けることで、冗長性を高め、撮像装置２００の信頼性を高めることができる。 Note that the number of subpixels 212 provided in the pixel 211 may be one, but two or more are preferable. For example, by providing two or more subpixels 212 that detect light in the same wavelength region, redundancy can be increased and the reliability of the imaging apparatus 200 can be increased.
また、可視光を吸収または反射して、赤外光を透過するＩＲ（ＩＲ：Ｉｎｆｒａｒｅｄ）フィルタを用いることで、赤外光を検出する撮像装置２００を実現することができる。 In addition, by using an IR (IR: Infrared) filter that absorbs or reflects visible light and transmits infrared light, the imaging device 200 that detects infrared light can be realized.
また、ＮＤ（ＮＤ：Ｎｅｕｔｒａｌ　Ｄｅｎｓｉｔｙ）フィルタ（減光フィルタ）を用いることで、光電変換素子（受光素子）に大光量光が入射した時に生じる出力飽和することを防ぐことができる。減光量の異なるＮＤフィルタを組み合わせて用いることで、撮像装置のダイナミックレンジを大きくすることができる。 Further, by using an ND (ND: Neutral Density) filter (a neutral density filter), it is possible to prevent output saturation that occurs when a large amount of light enters the photoelectric conversion element (light receiving element). By using a combination of ND filters having different light reduction amounts, the dynamic range of the imaging apparatus can be increased.
また、前述したフィルタ以外に、画素２１１にレンズを設けてもよい。ここで、図２４の断面図を用いて、画素２１１、フィルタ２５４、レンズ２５５の配置例を説明する。レンズ２５５を設けることで、光電変換素子が入射光を効率よく受光することができる。具体的には、図２４（Ａ）に示すように、画素２１１に形成したレンズ２５５、フィルタ２５４（フィルタ２５４Ｒ、フィルタ２５４Ｇおよびフィルタ２５４Ｂ）、および画素回路２３０等を通して光２５６を光電変換素子２２０に入射させる構造とすることができる。 In addition to the filters described above, a lens may be provided in the pixel 211. Here, an arrangement example of the pixel 211, the filter 254, and the lens 255 will be described with reference to the cross-sectional view of FIG. By providing the lens 255, the photoelectric conversion element can receive incident light efficiently. Specifically, as illustrated in FIG. 24A, the light 256 is transmitted to the photoelectric conversion element 220 through the lens 255, the filter 254 (filter 254R, the filter 254G, and the filter 254B) formed in the pixel 211, the pixel circuit 230, and the like. It can be set as the structure made to enter.
ただし、一点鎖線で囲んだ領域に示すように、矢印で示す光２５６の一部が配線２５７の一部によって遮光されてしまうことがある。したがって、図２４（Ｂ）に示すように光電変換素子２２０側にレンズ２５５およびフィルタ２５４を配置して、光電変換素子２２０が光２５６を効率良く受光させる構造が好ましい。光電変換素子２２０側から光２５６を光電変換素子２２０に入射させることで、検出感度の高い撮像装置２００を提供することができる。 However, as illustrated in the region surrounded by the alternate long and short dash line, part of the light 256 indicated by the arrow may be blocked by part of the wiring 257. Therefore, a structure in which a lens 255 and a filter 254 are disposed on the photoelectric conversion element 220 side as illustrated in FIG. 24B so that the photoelectric conversion element 220 receives light 256 efficiently is preferable. By making the light 256 incident on the photoelectric conversion element 220 from the photoelectric conversion element 220 side, the imaging device 200 with high detection sensitivity can be provided.
図２４に示す光電変換素子２２０として、ｐｎ型接合またはｐｉｎ型の接合が形成された光電変換素子を用いてもよい。 As the photoelectric conversion element 220 illustrated in FIG. 24, a photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used.
また、光電変換素子２２０を、放射線を吸収して電荷を発生させる機能を有する物質を用いて形成してもよい。放射線を吸収して電荷を発生させる機能を有する物質としては、セレン、ヨウ化鉛、ヨウ化水銀、ヒ化ガリウム、テルル化カドミウム、カドミウム亜鉛合金等がある。 Alternatively, the photoelectric conversion element 220 may be formed using a substance having a function of generating charges by absorbing radiation. Examples of the substance having a function of absorbing radiation and generating a charge include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.
例えば、光電変換素子２２０にセレンを用いると、可視光や、紫外光、赤外光に加えて、Ｘ線や、ガンマ線といった幅広い波長域にわたって光吸収係数を有する光電変換素子２２０を実現できる。 For example, when selenium is used for the photoelectric conversion element 220, the photoelectric conversion element 220 having a light absorption coefficient over a wide wavelength range such as X-rays and gamma rays in addition to visible light, ultraviolet light, and infrared light can be realized.
ここで、撮像装置２００が有する１つの画素２１１は、図２３に示す副画素２１２に加えて、第１のフィルタを有する副画素２１２を有してもよい。 Here, one pixel 211 included in the imaging apparatus 200 may include a sub-pixel 212 including a first filter in addition to the sub-pixel 212 illustrated in FIG.
＜画素の構成例２＞
以下では、シリコンを用いたトランジスタと、酸化物半導体を用いたトランジスタと、を用いて画素を構成する一例について説明する。 <Pixel Configuration Example 2>
Hereinafter, an example in which a pixel is formed using a transistor including silicon and a transistor including an oxide semiconductor will be described.
図２５（Ａ）および図２５（Ｂ）は、撮像装置を構成する素子の断面図である。図２５（Ａ）に示す撮像装置は、シリコン基板３００に設けられたシリコンを用いたトランジスタ３５１、トランジスタ３５１上に積層して配置された酸化物半導体を用いたトランジスタ３５２およびトランジスタ３５３、ならびにシリコン基板３００に設けられたフォトダイオード３６０を含む。各トランジスタおよびフォトダイオード３６０は、種々のプラグ３７０および配線３７１と電気的な接続を有する。また、フォトダイオード３６０のアノード３６１は、低抵抗領域３６３を介してプラグ３７０と電気的に接続を有する。 25A and 25B are cross-sectional views of elements included in the imaging device. An imaging device illustrated in FIG. 25A includes a transistor 351 using silicon provided over a silicon substrate 300, a transistor 352 and a transistor 353 using oxide semiconductors stacked over the transistor 351, and a silicon substrate. 300 includes a photodiode 360 provided. Each transistor and photodiode 360 has electrical connection with various plugs 370 and wirings 371. Further, the anode 361 of the photodiode 360 is electrically connected to the plug 370 through the low resistance region 363.
また撮像装置は、シリコン基板３００に設けられたトランジスタ３５１およびフォトダイオード３６０を有する層３１０と、層３１０と接して設けられ、配線３７１を有する層３２０と、層３２０と接して設けられ、トランジスタ３５２およびトランジスタ３５３を有する層３３０と、層３３０と接して設けられ、配線３７２および配線３７３を有する層３４０を備えている。 The imaging device is provided in contact with the layer 310 including the transistor 351 and the photodiode 360 provided over the silicon substrate 300, the layer 320 including the wiring 371, and the layer 320 including the wiring 371. A layer 330 including the transistor 353, and a layer 340 provided in contact with the layer 330 and including a wiring 372 and a wiring 373.
なお、図２５（Ａ）の断面図の一例では、シリコン基板３００において、トランジスタ３５１が形成された面とは逆側の面にフォトダイオード３６０の受光面を有する構成とする。該構成とすることで、各種トランジスタや配線などの影響を受けずに光路を確保することができる。そのため、高開口率の画素を形成することができる。なお、フォトダイオード３６０の受光面をトランジスタ３５１が形成された面と同じとすることもできる。 Note that in the example of the cross-sectional view of FIG. 25A, the light-receiving surface of the photodiode 360 is provided on the surface opposite to the surface where the transistor 351 is formed in the silicon substrate 300. With this configuration, an optical path can be secured without being affected by various transistors and wirings. Therefore, a pixel with a high aperture ratio can be formed. Note that the light receiving surface of the photodiode 360 may be the same as the surface on which the transistor 351 is formed.
なお、酸化物半導体を用いたトランジスタのみを用いて画素を構成する場合には、層３１０を、酸化物半導体を用いたトランジスタを有する層とすればよい。または層３１０を省略し、酸化物半導体を用いたトランジスタのみで画素を構成してもよい。 Note that in the case where a pixel is formed using only a transistor including an oxide semiconductor, the layer 310 may be a layer including a transistor including an oxide semiconductor. Alternatively, the layer 310 may be omitted, and the pixel may be formed using only a transistor including an oxide semiconductor.
なおシリコンを用いたトランジスタのみを用いて画素を構成する場合には、層３３０を省略すればよい。層３３０を省略した断面図の一例を図２５（Ｂ）に示す。 Note that in the case where a pixel is formed using only transistors using silicon, the layer 330 may be omitted. An example of a cross-sectional view in which the layer 330 is omitted is illustrated in FIG.
なお、シリコン基板３００は、ＳＯＩ基板であってもよい。また、シリコン基板３００に替えて、ゲルマニウム、シリコンゲルマニウム、炭化シリコン、ヒ化ガリウム、ヒ化アルミニウムガリウム、リン化インジウム、窒化ガリウムまたは有機半導体を有する基板を用いることもできる。 Note that the silicon substrate 300 may be an SOI substrate. Further, instead of the silicon substrate 300, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor substrate can be used.
ここで、トランジスタ３５１およびフォトダイオード３６０を有する層３１０と、トランジスタ３５２およびトランジスタ３５３を有する層３３０と、の間には絶縁体３８０が設けられる。ただし、絶縁体３８０の位置は限定されない。 Here, an insulator 380 is provided between the layer 310 including the transistor 351 and the photodiode 360 and the layer 330 including the transistor 352 and the transistor 353. However, the position of the insulator 380 is not limited.
トランジスタ３５１のチャネル形成領域近傍に設けられる絶縁体中の水素はシリコンのダングリングボンドを終端し、トランジスタ３５１の信頼性を向上させる効果がある。一方、トランジスタ３５２およびトランジスタ３５３などの近傍に設けられる絶縁体中の水素は、酸化物半導体中にキャリアを生成する要因の一つとなる。そのため、トランジスタ３５２およびトランジスタ３５３などの信頼性を低下させる要因となる場合がある。したがって、シリコン系半導体を用いたトランジスタの上層に酸化物半導体を用いたトランジスタを積層して設ける場合、これらの間に水素をブロックする機能を有する絶縁体３８０を設けることが好ましい。絶縁体３８０より下層に水素を閉じ込めることで、トランジスタ３５１の信頼性が向上させることができる。さらに、絶縁体３８０より下層から、絶縁体３８０より上層に水素が拡散することを抑制できるため、トランジスタ３５２およびトランジスタ３５３などの信頼性を向上させることができる。 Hydrogen in the insulator provided in the vicinity of the channel formation region of the transistor 351 has an effect of terminating the dangling bond of silicon and improving the reliability of the transistor 351. On the other hand, hydrogen in the insulator provided in the vicinity of the transistor 352, the transistor 353, and the like is one of the factors that generate carriers in the oxide semiconductor. Therefore, the reliability of the transistor 352, the transistor 353, and the like may be reduced. Therefore, in the case where a transistor including an oxide semiconductor is stacked over a transistor including a silicon-based semiconductor, an insulator 380 having a function of blocking hydrogen is preferably provided therebetween. By confining hydrogen below the insulator 380, the reliability of the transistor 351 can be improved. Further, since diffusion of hydrogen from a lower layer than the insulator 380 to an upper layer than the insulator 380 can be suppressed, reliability of the transistor 352, the transistor 353, and the like can be improved.
絶縁体３８０としては、例えば、酸素または水素をブロックする機能を有する絶縁体を用いる。 As the insulator 380, for example, an insulator having a function of blocking oxygen or hydrogen is used.
また、図２５（Ａ）の断面図において、層３１０に設けるフォトダイオード３６０と、層３３０に設けるトランジスタとを重なるように形成することができる。そうすると、画素の集積度を高めることができる。すなわち、撮像装置の解像度を高めることができる。 In the cross-sectional view in FIG. 25A, the photodiode 360 provided in the layer 310 and the transistor provided in the layer 330 can be formed to overlap with each other. Then, the integration degree of pixels can be increased. That is, the resolution of the imaging device can be increased.
また、図２６（Ａ１）および図２６（Ｂ１）に示すように、撮像装置の一部または全部を湾曲させてもよい。図２６（Ａ１）は、撮像装置を同図中の一点鎖線Ｘ１−Ｘ２の方向に湾曲させた状態を示している。図２６（Ａ２）は、図２６（Ａ１）中の一点鎖線Ｘ１−Ｘ２で示した部位の断面図である。図２６（Ａ３）は、図２６（Ａ１）中の一点鎖線Ｙ１−Ｙ２で示した部位の断面図である。 In addition, as illustrated in FIGS. 26A1 and 26B1, part or all of the imaging device may be curved. FIG. 26A1 illustrates a state where the imaging device is bent in the direction of dashed-dotted line X1-X2 in FIG. FIG. 26A2 is a cross-sectional view illustrating a portion indicated by dashed-dotted line X1-X2 in FIG. 26A3 is a cross-sectional view illustrating a portion indicated by dashed-dotted line Y1-Y2 in FIG.
図２６（Ｂ１）は、撮像装置を同図中の一点鎖線Ｘ３−Ｘ４の方向に湾曲させ、かつ、同図中の一点鎖線Ｙ３−Ｙ４の方向に湾曲させた状態を示している。図２６（Ｂ２）は、図２６（Ｂ１）中の一点鎖線Ｘ３−Ｘ４で示した部位の断面図である。図２６（Ｂ３）は、図２６（Ｂ１）中の一点鎖線Ｙ３−Ｙ４で示した部位の断面図である。 FIG. 26B1 illustrates a state in which the imaging device is curved in the direction of the alternate long and short dash line X3-X4 in the drawing and in the direction of the dashed dotted line Y3-Y4 in the same drawing. FIG. 26B2 is a cross-sectional view illustrating a portion indicated by dashed-dotted line X3-X4 in FIG. 26B3 is a cross-sectional view illustrating a portion indicated by dashed-dotted line Y3-Y4 in FIG.
撮像装置を湾曲させることで、像面湾曲や非点収差を低減することができる。よって、撮像装置と組み合わせて用いるレンズなどの光学設計を容易とすることができる。例えば、収差補正のためのレンズ枚数を低減できるため、撮像装置を用いた電子機器などの小型化や軽量化を実現することができるまた、撮像された画像の品質を向上させる事ができる。 By curving the imaging device, field curvature and astigmatism can be reduced. Therefore, optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lenses for correcting aberrations can be reduced, it is possible to reduce the size and weight of an electronic device using an imaging device, and to improve the quality of a captured image.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態５）
本実施の形態においては、本発明の一態様に係るトランジスタや上述した記憶装置などの半導体装置を含むＣＰＵの一例について説明する。 (Embodiment 5)
In this embodiment, an example of a CPU including a transistor according to one embodiment of the present invention and a semiconductor device such as the memory device described above will be described.
＜ＣＰＵの構成＞
図２７は、上述したトランジスタを一部に用いたＣＰＵの一例の構成を示すブロック図である。 <Configuration of CPU>
FIG. 27 is a block diagram illustrating a configuration example of a CPU in which some of the above-described transistors are used.
図２７に示すＣＰＵは、基板１１９０上に、ＡＬＵ１１９１（ＡＬＵ：Ａｒｉｔｈｍｅｔｉｃ　ｌｏｇｉｃ　ｕｎｉｔ、演算回路）、ＡＬＵコントローラ１１９２、インストラクションデコーダ１１９３、インタラプトコントローラ１１９４、タイミングコントローラ１１９５、レジスタ１１９６、レジスタコントローラ１１９７、バスインターフェース１１９８、書き換え可能なＲＯＭ１１９９、およびＲＯＭインターフェース１１８９を有している。基板１１９０は、半導体基板、ＳＯＩ基板、ガラス基板などを用いる。ＲＯＭ１１９９およびＲＯＭインターフェース１１８９は、別チップに設けてもよい。もちろん、図２７に示すＣＰＵは、その構成を簡略化して示した一例にすぎず、実際のＣＰＵはその用途によって多種多様な構成を有している。例えば、図２７に示すＣＰＵまたは演算回路を含む構成を一つのコアとし、当該コアを複数含み、それぞれのコアが並列で動作するような構成としてもよい。また、ＣＰＵが内部演算回路やデータバスで扱えるビット数は、例えば８ビット、１６ビット、３２ビット、６４ビットなどとすることができる。 27 includes an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. A rewritable ROM 1199 and a ROM interface 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 27 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 27 may be a single core, and a plurality of the cores may be included, and each core may operate in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.
バスインターフェース１１９８を介してＣＰＵに入力された命令は、インストラクションデコーダ１１９３に入力され、デコードされた後、ＡＬＵコントローラ１１９２、インタラプトコントローラ１１９４、レジスタコントローラ１１９７、タイミングコントローラ１１９５に入力される。 Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.
ＡＬＵコントローラ１１９２、インタラプトコントローラ１１９４、レジスタコントローラ１１９７、タイミングコントローラ１１９５は、デコードされた命令に基づき、各種制御を行なう。具体的にＡＬＵコントローラ１１９２は、ＡＬＵ１１９１の動作を制御するための信号を生成する。また、インタラプトコントローラ１１９４は、ＣＰＵのプログラム実行中に、外部の入出力装置や、周辺回路からの割り込み要求を、その優先度やマスク状態から判断し、処理する。レジスタコントローラ１１９７は、レジスタ１１９６のアドレスを生成し、ＣＰＵの状態に応じてレジスタ１１９６の読み出しや書き込みを行なう。 The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.
また、タイミングコントローラ１１９５は、ＡＬＵ１１９１、ＡＬＵコントローラ１１９２、インストラクションデコーダ１１９３、インタラプトコントローラ１１９４、およびレジスタコントローラ１１９７の動作のタイミングを制御する信号を生成する。例えばタイミングコントローラ１１９５は、基準クロック信号を元に、内部クロック信号を生成する内部クロック生成部を備えており、内部クロック信号を上記各種回路に供給する。 In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits.
図２７に示すＣＰＵでは、レジスタ１１９６に、メモリセルが設けられている。レジスタ１１９６のメモリセルとして、上述したトランジスタや記憶装置などを用いることができる。 In the CPU illustrated in FIG. 27, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the above-described transistor, memory device, or the like can be used.
図２７に示すＣＰＵにおいて、レジスタコントローラ１１９７は、ＡＬＵ１１９１からの指示に従い、レジスタ１１９６における保持動作の選択を行う。即ち、レジスタ１１９６が有するメモリセルにおいて、フリップフロップによるデータの保持を行うか、容量素子によるデータの保持を行うかを、選択する。フリップフロップによるデータの保持が選択されている場合、レジスタ１１９６内のメモリセルへの、電源電圧の供給が行われる。容量素子におけるデータの保持が選択されている場合、容量素子へのデータの書き換えが行われ、レジスタ１１９６内のメモリセルへの電源電圧の供給を停止することができる。 In the CPU shown in FIG. 27, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.
図２８は、レジスタ１１９６として用いることのできる記憶素子１２００の回路図の一例である。記憶素子１２００は、電源遮断で記憶データが揮発する回路１２０１と、電源遮断で記憶データが揮発しない回路１２０２と、スイッチ１２０３と、スイッチ１２０４と、論理素子１２０６と、容量素子１２０７と、選択機能を有する回路１２２０と、を有する。回路１２０２は、容量素子１２０８と、トランジスタ１２０９と、トランジスタ１２１０と、を有する。なお、記憶素子１２００は、必要に応じて、ダイオード、抵抗素子、インダクタなどのその他の素子をさらに有していてもよい。 FIG. 28 is an example of a circuit diagram of a memory element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized by power-off, a circuit 1202 in which stored data is not volatilized by power-off, a switch 1203, a switch 1204, a logic element 1206, and a capacitor 1207. Circuit 1220 having. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor, as necessary.
ここで、回路１２０２には、上述した記憶装置を用いることができる。記憶素子１２００への電源電圧の供給が停止した際、回路１２０２のトランジスタ１２０９のゲートにはＧＮＤ（０Ｖ）、またはトランジスタ１２０９がオフする電位が入力され続ける構成とする。例えば、トランジスタ１２０９のゲートが抵抗等の負荷を介して接地される構成とする。 Here, the memory device described above can be used for the circuit 1202. When supply of power supply voltage to the memory element 1200 is stopped, GND (0 V) or a potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 of the circuit 1202. For example, the gate of the transistor 1209 is grounded through a load such as a resistor.
スイッチ１２０３は、一導電型（例えば、ｎチャネル型）のトランジスタ１２１３を用いて構成され、スイッチ１２０４は、一導電型とは逆の導電型（例えば、ｐチャネル型）のトランジスタ１２１４を用いて構成した例を示す。ここで、スイッチ１２０３の第１の端子はトランジスタ１２１３のソースとドレインの一方に対応し、スイッチ１２０３の第２の端子はトランジスタ１２１３のソースとドレインの他方に対応し、スイッチ１２０３はトランジスタ１２１３のゲートに入力される制御信号ＲＤによって、第１の端子と第２の端子の間の導通または非導通（つまり、トランジスタ１２１３の導通状態または非導通状態）が選択される。スイッチ１２０４の第１の端子はトランジスタ１２１４のソースとドレインの一方に対応し、スイッチ１２０４の第２の端子はトランジスタ１２１４のソースとドレインの他方に対応し、スイッチ１２０４はトランジスタ１２１４のゲートに入力される制御信号ＲＤによって、第１の端子と第２の端子の間の導通または非導通（つまり、トランジスタ１２１４の導通状態または非導通状態）が選択される。 The switch 1203 is configured using a transistor 1213 of one conductivity type (eg, n-channel type), and the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type. An example is shown. Here, the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and the switch 1203 corresponds to the gate of the transistor 1213. In accordance with the control signal RD input to the second terminal, conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1213) is selected. The first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214, the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and the switch 1204 is input to the gate of the transistor 1214. The control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1214).
トランジスタ１２０９のソースとドレインの一方は、容量素子１２０８の一対の電極のうちの一方、およびトランジスタ１２１０のゲートと電気的に接続される。ここで、接続部分をノードＭ２とする。トランジスタ１２１０のソースとドレインの一方は、低電源電位を供給することのできる配線（例えばＧＮＤ線）に電気的に接続され、他方は、スイッチ１２０３の第１の端子（トランジスタ１２１３のソースとドレインの一方）と電気的に接続される。スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）はスイッチ１２０４の第１の端子（トランジスタ１２１４のソースとドレインの一方）と電気的に接続される。スイッチ１２０４の第２の端子（トランジスタ１２１４のソースとドレインの他方）は電源電位ＶＤＤを供給することのできる配線と電気的に接続される。スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）と、スイッチ１２０４の第１の端子（トランジスタ１２１４のソースとドレインの一方）と、論理素子１２０６の入力端子と、容量素子１２０７の一対の電極のうちの一方と、は電気的に接続される。ここで、接続部分をノードＭ１とする。容量素子１２０７の一対の電極のうちの他方は、一定の電位が入力される構成とすることができる。例えば、低電源電位（ＧＮＤ等）または高電源電位（ＶＤＤ等）が入力される構成とすることができる。容量素子１２０７の一対の電極のうちの他方は、低電源電位を供給することのできる配線（例えばＧＮＤ線）と電気的に接続される。容量素子１２０８の一対の電極のうちの他方は、一定の電位が入力される構成とすることができる。例えば、低電源電位（ＧＮＤ等）または高電源電位（ＶＤＤ等）が入力される構成とすることができる。容量素子１２０８の一対の電極のうちの他方は、低電源電位を供給することのできる配線（例えばＧＮＤ線）と電気的に接続される。 One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection part is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line), and the other is connected to the first terminal of the switch 1203 (the source and the drain of the transistor 1213 On the other hand). A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to a first terminal of the switch 1204 (one of the source and the drain of the transistor 1214). A second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring that can supply the power supply potential VDD. A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), a first terminal of the switch 1204 (one of a source and a drain of the transistor 1214), an input terminal of the logic element 1206, and the capacitor 1207 One of the pair of electrodes is electrically connected. Here, the connection part is referred to as a node M1. The other of the pair of electrodes of the capacitor 1207 can be configured to receive a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1207 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 can have a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.
なお、容量素子１２０７および容量素子１２０８は、トランジスタや配線の寄生容量等を積極的に利用することによって省略することも可能である。 Note that the capacitor 1207 and the capacitor 1208 can be omitted by positively using a parasitic capacitance of a transistor or a wiring.
トランジスタ１２０９のゲートには、制御信号ＷＥが入力される。スイッチ１２０３およびスイッチ１２０４は、制御信号ＷＥとは異なる制御信号ＲＤによって第１の端子と第２の端子の間の導通状態または非導通状態を選択され、一方のスイッチの第１の端子と第２の端子の間が導通状態のとき他方のスイッチの第１の端子と第２の端子の間は非導通状態となる。 A control signal WE is input to the gate of the transistor 1209. The switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.
トランジスタ１２０９のソースとドレインの他方には、回路１２０１に保持されたデータに対応する信号が入力される。図２８では、回路１２０１から出力された信号が、トランジスタ１２０９のソースとドレインの他方に入力される例を示した。スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）から出力される信号は、論理素子１２０６によってその論理値が反転された反転信号となり、回路１２２０を介して回路１２０１に入力される。 A signal corresponding to data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 28 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is an inverted signal obtained by inverting the logic value by the logic element 1206 and is input to the circuit 1201 through the circuit 1220. .
なお、図２８では、スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）から出力される信号は、論理素子１２０６および回路１２２０を介して回路１２０１に入力する例を示したがこれに限定されない。スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）から出力される信号が、論理値を反転させられることなく、回路１２０１に入力されてもよい。例えば、回路１２０１内に、入力端子から入力された信号の論理値が反転した信号が保持されるノードが存在する場合に、スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）から出力される信号を当該ノードに入力することができる。 Note that FIG. 28 illustrates an example in which a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. It is not limited to. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without inversion of the logical value. For example, when there is a node in the circuit 1201 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) An output signal can be input to the node.
また、図２８において、記憶素子１２００に用いられるトランジスタのうち、トランジスタ１２０９以外のトランジスタは、酸化物半導体以外の半導体でなる膜または基板１１９０にチャネルが形成されるトランジスタとすることができる。例えば、シリコン膜またはシリコン基板にチャネルが形成されるトランジスタとすることができる。また、記憶素子１２００に用いられるトランジスタ全てを、チャネルが酸化物半導体で形成されるトランジスタとすることもできる。または、記憶素子１２００は、トランジスタ１２０９以外にも、チャネルが酸化物半導体で形成されるトランジスタを含んでいてもよく、残りのトランジスタは酸化物半導体以外の半導体でなる層または基板１１９０にチャネルが形成されるトランジスタとすることもできる。 28, a transistor other than the transistor 1209 among the transistors used for the memory element 1200 can be a transistor whose channel is formed in a film or a substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a transistor in which a channel is formed in a silicon film or a silicon substrate can be used. Further, all the transistors used for the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor. Alternatively, the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor in addition to the transistor 1209, and the remaining transistors are formed using a semiconductor layer other than the oxide semiconductor or the substrate 1190. It can also be a transistor.
図２８における回路１２０１には、例えばフリップフロップ回路を用いることができる。また、論理素子１２０６としては、例えばインバータやクロックドインバータ等を用いることができる。 For the circuit 1201 in FIG. 28, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.
本発明の一態様に係る半導体装置では、記憶素子１２００に電源電圧が供給されない間は、回路１２０１に記憶されていたデータを、回路１２０２に設けられた容量素子１２０８によって保持することができる。 In the semiconductor device according to one embodiment of the present invention, data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.
また、酸化物半導体にチャネルが形成されるトランジスタはオフ電流が極めて小さい。例えば、酸化物半導体にチャネルが形成されるトランジスタのオフ電流は、結晶性を有するシリコンにチャネルが形成されるトランジスタのオフ電流に比べて著しく低い。そのため、当該トランジスタをトランジスタ１２０９として用いることによって、記憶素子１２００に電源電圧が供給されない間も容量素子１２０８に保持された信号は長期間にわたり保たれる。こうして、記憶素子１２００は電源電圧の供給が停止した間も記憶内容（データ）を保持することが可能である。 In addition, a transistor in which a channel is formed in an oxide semiconductor has extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 is maintained for a long time even when the power supply voltage is not supplied to the memory element 1200. In this manner, the memory element 1200 can hold stored data (data) even while the supply of power supply voltage is stopped.
また、スイッチ１２０３およびスイッチ１２０４を設けることによって、プリチャージ動作を行うことを特徴とする記憶素子であるため、電源電圧供給再開後に、回路１２０１が元のデータを保持しなおすまでの時間を短くすることができる。 Further, by providing the switch 1203 and the switch 1204, the memory element is characterized by performing a precharge operation; therefore, after the supply of power supply voltage is resumed, the time until the circuit 1201 retains the original data again is shortened. be able to.
また、回路１２０２において、容量素子１２０８によって保持された信号はトランジスタ１２１０のゲートに入力される。そのため、記憶素子１２００への電源電圧の供給が再開された後、容量素子１２０８によって保持された信号を、トランジスタ１２１０の状態（導通状態、または非導通状態）に変換して、回路１２０２から読み出すことができる。それ故、容量素子１２０８に保持された信号に対応する電位が多少変動していても、元の信号を正確に読み出すことが可能である。 In the circuit 1202, the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 is converted into the state of the transistor 1210 (a conductive state or a non-conductive state) and read from the circuit 1202 Can do. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates.
このような記憶素子１２００を、プロセッサが有するレジスタやキャッシュメモリなどの記憶装置に用いることで、電源電圧の供給停止による記憶装置内のデータの消失を防ぐことができる。また、電源電圧の供給を再開した後、短時間で電源供給停止前の状態に復帰することができる。よって、プロセッサ全体、もしくはプロセッサを構成する一つ、または複数の論理回路において、短い時間でも電源停止を行うことができるため、消費電力を抑えることができる。 By using such a storage element 1200 for a storage device such as a register or a cache memory included in the processor, loss of data in the storage device due to stop of supply of power supply voltage can be prevented. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Accordingly, power can be stopped in a short time in the entire processor or in one or a plurality of logic circuits constituting the processor, so that power consumption can be suppressed.
記憶素子１２００をＣＰＵに用いる例として説明したが、記憶素子１２００は、ＤＳＰ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｌ　Ｐｒｏｃｅｓｓｏｒ）、カスタムＬＳＩ等のＬＳＩ、ＲＦ（Ｒａｄｉｏ　Ｆｒｅｑｕｅｎｃｙ）デバイスにも応用可能である。また、ＦＰＧＡ（Ｆｉｅｌｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）やＣＰＬＤ（Ｃｏｍｐｌｅｘ　ＰＬＤ）などのプログラマブル論理回路（ＰＬＤ：Ｐｒｏｇｒａｍｍａｂｌｅ　Ｌｏｇｉｃ　Ｄｅｖｉｃｅ）等のＬＳＩ、ＲＦ（Ｒａｄｉｏ　Ｆｒｅｑｕｅｎｃｙ）デバイスにも応用可能である。 Although the memory element 1200 has been described as an example of use for a CPU, the memory element 1200 can be applied to a DSP (Digital Signal Processor), an LSI such as a custom LSI, and an RF (Radio Frequency) device. Further, it can also be applied to LSIs such as programmable logic circuits (PLD: Programmable Logic Devices) such as FPGA (Field Programmable Gate Array) and CPLD (Complex PLD), and RF (Radio Frequency) devices.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態６）
本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した表示装置について、図２９および図３０を用いて説明する。 (Embodiment 6)
In this embodiment, a display device using a transistor or the like according to one embodiment of the present invention will be described with reference to FIGS.
＜表示装置の構成＞
表示装置に用いられる表示素子としては液晶素子（液晶表示素子ともいう。）、発光素子（発光表示素子ともいう。）などを用いることができる。発光素子は、電流または電圧によって輝度が制御される素子をその範疇に含んでおり、具体的には無機ＥＬ（Ｅｌｅｃｔｒｏｌｕｍｉｎｅｓｃｅｎｃｅ）、有機ＥＬなどを含む。以下では、表示装置の一例としてＥＬ素子を用いた表示装置（ＥＬ表示装置）および液晶素子を用いた表示装置（液晶表示装置）について説明する。 <Configuration of display device>
As a display element used for the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light-emitting element (also referred to as a light-emitting display element), or the like can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electroluminescence), organic EL, and the like. Hereinafter, a display device using an EL element (an EL display device) and a display device using a liquid crystal element (a liquid crystal display device) will be described as examples of the display device.
なお、以下に示す表示装置は、表示素子が封止された状態にあるパネルと、該パネルにコントローラを含むＩＣなどを実装した状態にあるモジュールとを含む。 Note that a display device described below includes a panel in which a display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel.
また、以下に示す表示装置は画像表示デバイス、または光源（照明装置含む）を指す。また、コネクター、例えばＦＰＣ、ＴＣＰが取り付けられたモジュール、ＴＣＰの先にプリント配線板を有するモジュールまたは表示素子にＣＯＧ方式によりＩＣ（集積回路）が直接実装されたモジュールも全て表示装置に含むものとする。 The display device described below refers to an image display device or a light source (including a lighting device). The display device includes all connectors, for example, a module to which FPC and TCP are attached, a module having a printed wiring board at the end of TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by a COG method.
図２９は、本発明の一態様に係るＥＬ表示装置の一例である。図２９（Ａ）に、ＥＬ表示装置の画素の回路図を示す。図２９（Ｂ）は、ＥＬ表示装置全体を示す上面図である。また、図２９（Ｃ）は、図２９（Ｂ）の一点鎖線Ｍ−Ｎの一部に対応するＭ−Ｎ断面である。 FIG. 29 illustrates an example of an EL display device according to one embodiment of the present invention. FIG. 29A shows a circuit diagram of a pixel of an EL display device. FIG. 29B is a top view showing the entire EL display device. FIG. 29C is an MN cross section corresponding to part of the dashed-dotted line MN in FIG.
図２９（Ａ）は、ＥＬ表示装置に用いられる画素の回路図の一例である。 FIG. 29A is an example of a circuit diagram of a pixel used in the EL display device.
なお、本明細書等においては、能動素子（トランジスタ、ダイオードなど）、受動素子（容量素子、抵抗素子など）などが有するすべての端子について、その接続先を特定しなくても、当業者であれば、発明の一態様を構成することは可能な場合がある。つまり、接続先を特定しなくても、発明の一態様が明確であるといえる。そして、接続先が特定された内容が、本明細書等に記載されている場合、接続先を特定しない発明の一態様が、本明細書等に記載されていると判断することが可能な場合がある。特に、端子の接続先として複数の箇所が想定される場合には、その端子の接続先を特定の箇所に限定する必要はない。したがって、能動素子（トランジスタ、ダイオードなど）、受動素子（容量素子、抵抗素子など）などが有する一部の端子についてのみ、その接続先を特定することによって、発明の一態様を構成することが可能な場合がある。 Note that in this specification and the like, a person skilled in the art can connect all terminals of an active element (a transistor, a diode, etc.), a passive element (a capacitor element, a resistance element, etc.) without specifying connection destinations. Thus, it may be possible to constitute an aspect of the invention. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. And, when the content specifying the connection destination is described in this specification etc., it is possible to determine that one aspect of the invention that does not specify the connection destination is described in this specification etc. There is. In particular, when a plurality of locations are assumed as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, it is possible to constitute one embodiment of the present invention by specifying connection destinations of only some terminals of active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements, etc.). There is a case.
なお、本明細書等においては、ある回路について、少なくとも接続先を特定すれば、当業者であれば、発明を特定することが可能な場合がある。または、ある回路について、少なくとも機能を特定すれば、当業者であれば、発明を特定することが可能な場合がある。つまり、機能を特定すれば、発明の一態様が明確であるといえる。そして、機能が特定された発明の一態様が、本明細書等に記載されていると判断することが可能な場合がある。したがって、ある回路について、機能を特定しなくても、接続先を特定すれば、発明の一態様として開示されているものであり、発明の一態様を構成することが可能である。または、ある回路について、接続先を特定しなくても、機能を特定すれば、発明の一態様として開示されているものであり、発明の一態様を構成することが可能である。 Note that in this specification and the like, it may be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it may be possible for those skilled in the art to specify the invention when at least the function of a circuit is specified. That is, if the function is specified, it can be said that one aspect of the invention is clear. Then, it may be possible to determine that one embodiment of the invention whose function is specified is described in this specification and the like. Therefore, if a connection destination is specified for a certain circuit without specifying a function, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. Alternatively, if a function is specified for a certain circuit without specifying a connection destination, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention.
図２９（Ａ）に示すＥＬ表示装置は、スイッチ素子７４３と、トランジスタ７４１と、容量素子７４２と、発光素子７１９と、を有する。 An EL display device illustrated in FIG. 29A includes a switch element 743, a transistor 741, a capacitor 742, and a light-emitting element 719.
なお、図２９（Ａ）などは、回路構成の一例であるため、さらに、トランジスタを追加することが可能である。逆に、図２９（Ａ）の各ノードにおいて、トランジスタ、スイッチ、受動素子などを追加しないようにすることも可能である。 Note that FIG. 29A is an example of a circuit configuration, and thus transistors can be added. On the other hand, it is also possible not to add a transistor, a switch, a passive element, or the like at each node in FIG.
トランジスタ７４１のゲートはスイッチ素子７４３の一端および容量素子７４２の一方の電極と電気的に接続される。トランジスタ７４１のソースは容量素子７４２の他方の電極と電気的に接続され、発光素子７１９の一方の電極と電気的に接続される。トランジスタ７４１のソースは電源電位ＶＤＤが与えられる。スイッチ素子７４３の他端は信号線７４４と電気的に接続される。発光素子７１９の他方の電極は定電位が与えられる。なお、定電位は接地電位ＧＮＤまたはそれより小さい電位とする。 A gate of the transistor 741 is electrically connected to one end of the switch element 743 and one electrode of the capacitor 742. A source of the transistor 741 is electrically connected to the other electrode of the capacitor 742 and electrically connected to one electrode of the light-emitting element 719. The source of the transistor 741 is supplied with the power supply potential VDD. The other end of the switch element 743 is electrically connected to the signal line 744. A constant potential is applied to the other electrode of the light-emitting element 719. Note that the constant potential is set to the ground potential GND or lower.
スイッチ素子７４３としては、トランジスタを用いると好ましい。トランジスタを用いることで、画素の面積を小さくでき、解像度の高いＥＬ表示装置とすることができる。また、スイッチ素子７４３として、トランジスタ７４１と同一工程を経て作製されたトランジスタを用いると、ＥＬ表示装置の生産性を高めることができる。なお、トランジスタ７４１または／およびスイッチ素子７４３としては、例えば、上述したトランジスタを適用することができる。 As the switch element 743, a transistor is preferably used. By using a transistor, the area of a pixel can be reduced and an EL display device with high resolution can be obtained. In addition, when a transistor manufactured through the same process as the transistor 741 is used as the switch element 743, the productivity of the EL display device can be increased. Note that as the transistor 741 and / or the switch element 743, for example, the above-described transistor can be used.
図２９（Ｂ）は、ＥＬ表示装置の上面図である。ＥＬ表示装置は、基板７００と、基板７５０と、シール材７３４と、駆動回路７３５と、駆動回路７３６と、画素７３７と、ＦＰＣ７３２と、を有する。シール材７３４は、画素７３７、駆動回路７３５および駆動回路７３６を囲むように基板７００と基板７５０との間に配置される。なお、駆動回路７３５または／および駆動回路７３６をシール材７３４の外側に配置しても構わない。 FIG. 29B is a top view of the EL display device. The EL display device includes a substrate 700, a substrate 750, a sealant 734, a driver circuit 735, a driver circuit 736, a pixel 737, and an FPC 732. The sealant 734 is disposed between the substrate 700 and the substrate 750 so as to surround the pixel 737, the drive circuit 735, and the drive circuit 736. Note that the drive circuit 735 and / or the drive circuit 736 may be disposed outside the sealant 734.
図２９（Ｃ）は、図２９（Ｂ）の一点鎖線Ｍ−Ｎの一部に対応するＥＬ表示装置の断面図である。 FIG. 29C is a cross-sectional view of the EL display device corresponding to part of the dashed-dotted line MN in FIG.
図２９（Ｃ）には、トランジスタ７４１として、基板７００上の絶縁体７０１と、絶縁体７０１上の導電体７０２ａと、導電体７０２ａ上の絶縁体７０４と、絶縁体７０４上にあり導電体７０２ａと重なる絶縁体７０６ａと、絶縁体７０６ａ上の半導体７０６ｂと、半導体７０６ｂ上の絶縁体７０６ｃと、絶縁体７０６ｃおよび半導体７０６ｂに設けられた領域７０７ａおよび領域７０７ｂと、絶縁体７０６ｃ上の絶縁体７１２と、絶縁体７１２上の導電体７１４ａと、絶縁体７０６ｃ上および導電体７１４ａ上の絶縁体７１６と、を有する構造を示す。なお、トランジスタ７４１の構造は一例であり、図２９（Ｃ）に示す構造と異なる構造であっても構わない。 In FIG. 29C, the transistor 741 includes an insulator 701 over the substrate 700, a conductor 702a over the insulator 701, an insulator 704 over the conductor 702a, and a conductor 702a over the insulator 704. And the insulator 706a over the insulator 706a, the insulator 706c over the semiconductor 706b, the regions 707a and 707b provided in the insulator 706c and the semiconductor 706b, and the insulator 712 over the insulator 706c. And a conductor 714a over the insulator 712 and an insulator 716 over the insulator 706c and the conductor 714a. Note that the structure of the transistor 741 is an example, and a structure different from the structure illustrated in FIG.
したがって、図２９（Ｃ）に示すトランジスタ７４１において、導電体７０２ａはゲート電極としての機能を有し、絶縁体７１２ａおよび絶縁体７１２ｂはゲート絶縁体としての機能を有し、領域７０７ａはソースとしての機能を有し、領域７０７ｂはドレインとしての機能を有し、絶縁体７１２はゲート絶縁体としての機能を有し、導電体７１４ａはゲート電極としての機能を有する。なお、半導体７０６ｂは、光が当たることで電気特性が変動する場合がある。したがって、導電体７０２ａ、導電体７１４ａのいずれか一以上が遮光性を有すると好ましい。 Therefore, in the transistor 741 illustrated in FIG. 29C, the conductor 702a functions as a gate electrode, the insulators 712a and 712b function as gate insulators, and the region 707a serves as a source. The region 707b functions as a drain, the insulator 712 functions as a gate insulator, and the conductor 714a functions as a gate electrode. Note that electrical characteristics of the semiconductor 706b may fluctuate when exposed to light. Therefore, it is preferable that one or more of the conductor 702a and the conductor 714a have a light-shielding property.
図２９（Ｃ）には、容量素子７４２として、絶縁体７０１上の導電体７０２ｂと、導電体７０２ｂ上の絶縁体７０４と、絶縁体７０４上にあり導電体７０２ｂと重なる領域７０７ａと、領域７０７ａ上の絶縁体７１１と、絶縁体７１１上にあり領域７０７ａと重なる導電体７１４ｂと、を有する構造を示す。 In FIG. 29C, as the capacitor 742, a conductor 702b over the insulator 701, an insulator 704 over the conductor 702b, a region 707a over the insulator 704 and overlapping the conductor 702b, and a region 707a A structure including an upper insulator 711 and a conductor 714b which is over the insulator 711 and overlaps with a region 707a is illustrated.
容量素子７４２において、導電体７０２ｂおよび導電体７１４ｂは一方の電極として機能し、領域７０７ａは他方の電極として機能する。 In the capacitor 742, the conductor 702b and the conductor 714b function as one electrode, and the region 707a functions as the other electrode.
したがって、容量素子７４２は、トランジスタ７４１と共通する膜を用いて作製することができる。また、導電体７０２ａおよび導電体７０２ｂを同種の導電体とすると好ましい。その場合、導電体７０２ａおよび導電体７０２ｂは、同一工程を経て形成することができる。また、導電体７１４ａおよび導電体７１４ｂを同種の導電体とすると好ましい。その場合、導電体７１４ａおよび導電体７１４ｂは、同一工程を経て形成することができる。また、絶縁体７１２および絶縁体７１１を同種の絶縁体とすると好ましい。その場合、絶縁体７１２および絶縁体７１１は、同一工程を経て形成することができる。 Therefore, the capacitor 742 can be manufactured using a film in common with the transistor 741. The conductors 702a and 702b are preferably the same kind of conductors. In that case, the conductor 702a and the conductor 702b can be formed through the same process. The conductors 714a and 714b are preferably the same kind of conductors. In that case, the conductor 714a and the conductor 714b can be formed through the same process. The insulator 712 and the insulator 711 are preferably the same kind of insulator. In that case, the insulator 712 and the insulator 711 can be formed through the same process.
図２９（Ｃ）に示す容量素子７４２は、占有面積当たりの容量が大きい容量素子である。したがって、図２９（Ｃ）は表示品位の高いＥＬ表示装置である。 A capacitor 742 illustrated in FIG. 29C has a large capacitance per occupied area. Accordingly, FIG. 29C illustrates an EL display device with high display quality.
トランジスタ７４１および容量素子７４２上には、絶縁体７２０が配置される。ここで、絶縁体７１６および絶縁体７２０は、トランジスタ７４１のソースとして機能する領域７０７ａに達する開口部を有してもよい。絶縁体７２０上には、導電体７８１が配置される。導電体７８１は、絶縁体７２０の開口部を介してトランジスタ７４１と電気的に接続している。 An insulator 720 is provided over the transistor 741 and the capacitor 742. Here, the insulator 716 and the insulator 720 may have an opening reaching the region 707 a functioning as the source of the transistor 741. A conductor 781 is provided over the insulator 720. The conductor 781 is electrically connected to the transistor 741 through the opening of the insulator 720.
導電体７８１上には、導電体７８１に達する開口部を有する隔壁７８４が配置される。隔壁７８４上には、隔壁７８４の開口部で導電体７８１と接する発光層７８２が配置される。発光層７８２上には、導電体７８３が配置される。導電体７８１、発光層７８２および導電体７８３の重なる領域が、発光素子７１９となる。 A partition 784 having an opening reaching the conductor 781 is provided over the conductor 781. A light-emitting layer 782 that is in contact with the conductor 781 through the opening of the partition 784 is provided over the partition 784. A conductor 783 is provided over the light-emitting layer 782. A region where the conductor 781, the light emitting layer 782, and the conductor 783 overlap with each other serves as the light emitting element 719.
ここまでは、ＥＬ表示装置の例について説明した。次に、液晶表示装置の例について説明する。 Up to this point, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described.
図３０（Ａ）は、液晶表示装置の画素の構成例を示す回路図である。図３０に示す画素は、トランジスタ７５１と、容量素子７５２と、一対の電極間に液晶の充填された素子（液晶素子）７５３とを有する。 FIG. 30A is a circuit diagram illustrating a configuration example of a pixel of a liquid crystal display device. A pixel illustrated in FIG. 30 includes a transistor 751, a capacitor 752, and an element (liquid crystal element) 753 in which liquid crystal is filled between a pair of electrodes.
トランジスタ７５１では、ソース、ドレインの一方が信号線７５５に電気的に接続され、ゲートが走査線７５４に電気的に接続されている。 In the transistor 751, one of a source and a drain is electrically connected to the signal line 755 and a gate is electrically connected to the scanning line 754.
容量素子７５２では、一方の電極がトランジスタ７５１のソース、ドレインの他方に電気的に接続され、他方の電極が共通電位を供給する配線に電気的に接続されている。 In the capacitor 752, one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential.
液晶素子７５３では、一方の電極がトランジスタ７５１のソース、ドレインの他方に電気的に接続され、他方の電極が共通電位を供給する配線に電気的に接続されている。なお、上述した容量素子７５２の他方の電極が電気的に接続する配線に与えられる共通電位と、液晶素子７５３の他方の電極に与えられる共通電位とが異なる電位であってもよい。 In the liquid crystal element 753, one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential. Note that the common potential applied to the wiring to which the other electrode of the capacitor 752 is electrically connected may be different from the common potential applied to the other electrode of the liquid crystal element 753.
なお、液晶表示装置も、上面図はＥＬ表示装置と同様として説明する。図２９（Ｂ）の一点鎖線Ｍ−Ｎに対応する液晶表示装置の断面図を図３０（Ｂ）に示す。図３０（Ｂ）において、ＦＰＣ７３２は、端子７３１を介して配線７３３ａと接続される。なお、配線７３３ａは、トランジスタ７５１を構成する導電体または半導体のいずれかと同種の導電体または半導体を用いてもよい。 Note that the top view of the liquid crystal display device is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dashed-dotted line MN in FIG. 29B is illustrated in FIG. In FIG. 30B, the FPC 732 is connected to a wiring 733a through a terminal 731. Note that the wiring 733a may be formed using the same kind of conductor or semiconductor as the conductor or semiconductor included in the transistor 751.
トランジスタ７５１は、トランジスタ７４１についての記載を参照する。また、容量素子７５２は、容量素子７４２についての記載を参照する。なお、図３０（Ｂ）には、図２９（Ｃ）の容量素子７４２に対応した容量素子７５２の構造を示したが、これに限定されない。 The description of the transistor 741 is referred to for the transistor 751. For the capacitor 752, the description of the capacitor 742 is referred to. Note that FIG. 30B illustrates a structure of the capacitor 752 corresponding to the capacitor 742 in FIG. 29C; however, the structure is not limited thereto.
なお、トランジスタ７５１の半導体に酸化物半導体を用いた場合、極めてオフ電流の小さいトランジスタとすることができる。したがって、容量素子７５２に保持された電荷がリークしにくく、長期間に渡って液晶素子７５３に印加される電圧を維持することができる。そのため、動きの少ない動画や静止画の表示の際に、トランジスタ７５１をオフ状態とすることで、トランジスタ７５１の動作のための電力が不要となり、消費電力の小さい液晶表示装置とすることができる。また、容量素子７５２の占有面積を小さくできるため、開口率の高い液晶表示装置、または高精細化した液晶表示装置を提供することができる。 Note that in the case where an oxide semiconductor is used for the semiconductor of the transistor 751, a transistor with extremely low off-state current can be obtained. Therefore, the charge held in the capacitor 752 is unlikely to leak, and the voltage applied to the liquid crystal element 753 can be maintained for a long time. Therefore, when a moving image or a still image with little movement is displayed, the transistor 751 is turned off, so that power for the operation of the transistor 751 is not necessary and a liquid crystal display device with low power consumption can be obtained. In addition, since the area occupied by the capacitor 752 can be reduced, a liquid crystal display device with a high aperture ratio or a liquid crystal display device with high definition can be provided.
トランジスタ７５１および容量素子７５２上には、絶縁体７２１が配置される。ここで、絶縁体７２１は、トランジスタ７５１に達する開口部を有する。絶縁体７２１上には、導電体７９１が配置される。導電体７９１は、絶縁体７２１の開口部を介してトランジスタ７５１と電気的に接続する。 An insulator 721 is provided over the transistor 751 and the capacitor 752. Here, the insulator 721 has an opening reaching the transistor 751. A conductor 791 is provided over the insulator 721. The conductor 791 is electrically connected to the transistor 751 through the opening of the insulator 721.
導電体７９１上には、配向膜として機能する絶縁体７９２が配置される。絶縁体７９２上には、液晶層７９３が配置される。液晶層７９３上には、配向膜として機能する絶縁体７９４が配置される。絶縁体７９４上には、スペーサ７９５が配置される。スペーサ７９５および絶縁体７９４上には、導電体７９６が配置される。導電体７９６上には、基板７９７が配置される。 An insulator 792 functioning as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is provided over the insulator 792. An insulator 794 functioning as an alignment film is provided over the liquid crystal layer 793. A spacer 795 is provided over the insulator 794. A conductor 796 is provided over the spacer 795 and the insulator 794. A substrate 797 is provided over the conductor 796.
なお、液晶の駆動方式としては、ＴＮ（Ｔｗｉｓｔｅｄ　Ｎｅｍａｔｉｃ）モード、ＳＴＮ（Ｓｕｐｅｒ　Ｔｗｉｓｔｅｄ　Ｎｅｍａｔｉｃ）モード、ＩＰＳ（Ｉｎ−Ｐｌａｎｅ−Ｓｗｉｔｃｈｉｎｇ）モード、ＦＦＳ（Ｆｒｉｎｇｅ　Ｆｉｅｌｄ　Ｓｗｉｔｃｈｉｎｇ）モード、ＭＶＡ（Ｍｕｌｔｉ−ｄｏｍａｉｎ　Ｖｅｒｔｉｃａｌ　Ａｌｉｇｎｍｅｎｔ）モード、ＰＶＡ（Ｐａｔｔｅｒｎｅｄ　Ｖｅｒｔｉｃａｌ　Ａｌｉｇｎｍｅｎｔ）モード、ＡＳＶ（Ａｄｖａｎｃｅｄ　Ｓｕｐｅｒ　Ｖｉｅｗ）モード、ＡＳＭ（Ａｘｉａｌｌｙ　Ｓｙｍｍｅｔｒｉｃ　ａｌｉｇｎｅｄ　Ｍｉｃｒｏ−ｃｅｌｌ）モード、ＯＣＢ（Ｏｐｔｉｃａｌｌｙ　Ｃｏｍｐｅｎｓａｔｅｄ　Ｂｉｒｅｆｒｉｎｇｅｎｃｅ）モード、ＥＣＢ（Ｅｌｅｃｔｒｉｃａｌｌｙ　Ｃｏｎｔｒｏｌｌｅｄ　Ｂｉｒｅｆｒｉｎｇｅｎｃｅ）モード、ＦＬＣ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ）モード、ＡＦＬＣ（ＡｎｔｉＦｅｒｒｏｅｌｅｃｔｒｉｃ　Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ）モード、ＰＤＬＣ（Ｐｏｌｙｍｅｒ　Ｄｉｓｐｅｒｓｅｄ　Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ）モード、ゲストホストモード、ブルー相（Ｂｌｕｅ　Ｐｈａｓｅ）モードなどを用いることができる。ただし、これに限定されず、駆動方法として様々なものを用いることができる。 Liquid crystal drive methods include TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, and MVA (Multi-Antificent). Mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, ASM (Axial Symmetrical Aligned Micro-cell) mode, OCB (Optically Comprehensive BEC) ly Controlled Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, it can be used AFLC (AntiFerroelectric Liquid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, guest-host mode, and blue phase (Blue Phase) mode. However, the present invention is not limited to this, and various driving methods can be used.
上述した構造を有することで、占有面積の小さい容量素子を有する表示装置を提供することができる、または、表示品位の高い表示装置を提供することができる。または、高精細の表示装置を提供することができる。 With the above structure, a display device including a capacitor with a small occupied area can be provided, or a display device with high display quality can be provided. Alternatively, a high-definition display device can be provided.
例えば、本明細書等において、表示素子、表示素子を有する装置である表示装置、発光素子、および発光素子を有する装置である発光装置は、様々な形態を用いること、または様々な素子を有することができる。表示素子、表示装置、発光素子または発光装置は、例えば、白色、赤色、緑色または青色などの発光ダイオード（ＬＥＤ：Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）、トランジスタ（電流に応じて発光するトランジスタ）、電子放出素子、液晶素子、電子インク、電気泳動素子、グレーティングライトバルブ（ＧＬＶ）、プラズマディスプレイ（ＰＤＰ）、ＭＥＭＳ（マイクロ・エレクトロ・メカニカル・システム）を用いた表示素子、デジタルマイクロミラーデバイス（ＤＭＤ）、ＤＭＳ（デジタル・マイクロ・シャッター）、ＩＭＯＤ（インターフェロメトリック・モジュレーション）素子、シャッター方式のＭＥＭＳ表示素子、光干渉方式のＭＥＭＳ表示素子、エレクトロウェッティング素子、圧電セラミックディスプレイ、カーボンナノチューブを用いた表示素子などの少なくとも一つを有している。これらの他にも、電気的または磁気的作用により、コントラスト、輝度、反射率、透過率などが変化する表示媒体を有していても良い。 For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. Can do. A display element, a display device, a light emitting element, or a light emitting device is, for example, a light emitting diode (LED: Light Emitting Diode) such as white, red, green, or blue, a transistor (a transistor that emits light in response to current), an electron emitting element, a liquid crystal Element, electronic ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), display element using MEMS (micro electro mechanical system), digital micromirror device (DMD), DMS (digital Micro shutter), IMOD (interferometric modulation) element, MEMS display element of shutter type, MEMS display element of optical interference type, electrowetting element, piezoelectric ceramic display, car It has at least one such display element using nanotubes. In addition to these, a display medium in which contrast, luminance, reflectance, transmittance, or the like is changed by an electric or magnetic action may be included.
ＥＬ素子を用いた表示装置の一例としては、ＥＬディスプレイなどがある。電子放出素子を用いた表示装置の一例としては、フィールドエミッションディスプレイ（ＦＥＤ）またはＳＥＤ方式平面型ディスプレイ（ＳＥＤ：Ｓｕｒｆａｃｅ−ｃｏｎｄｕｃｔｉｏｎ　Ｅｌｅｃｔｒｏｎ−ｅｍｉｔｔｅｒ　Ｄｉｓｐｌａｙ）などがある。液晶素子を用いた表示装置の一例としては、液晶ディスプレイ（透過型液晶ディスプレイ、半透過型液晶ディスプレイ、反射型液晶ディスプレイ、直視型液晶ディスプレイ、投射型液晶ディスプレイ）などがある。電子インクまたは電気泳動素子を用いた表示装置の一例としては、電子ペーパーなどがある。なお、半透過型液晶ディスプレイや反射型液晶ディスプレイを実現する場合には、画素電極の一部、または、全部が、反射電極としての機能を有するようにすればよい。例えば、画素電極の一部または全部が、アルミニウム、銀、などを有するようにすればよい。さらに、その場合、反射電極の下に、ＳＲＡＭなどの記憶回路を設けることも可能である。これにより、さらに、消費電力を低減することができる。 An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.
なお、ＬＥＤを用いる場合、ＬＥＤの電極や窒化物半導体の下に、グラフェンやグラファイトを配置してもよい。グラフェンやグラファイトは、複数の層を重ねて、多層膜としてもよい。このように、グラフェンやグラファイトを設けることにより、その上に、窒化物半導体、例えば、結晶を有するｎ型ＧａＮ半導体などを容易に成膜することができる。さらに、その上に、結晶を有するｐ型ＧａＮ半導体などを設けて、ＬＥＤを構成することができる。なお、グラフェンやグラファイトと、結晶を有するｎ型ＧａＮ半導体との間に、ＡｌＮ層を設けてもよい。なお、ＬＥＤが有するＧａＮ半導体は、ＭＯＣＶＤで成膜してもよい。ただし、グラフェンを設けることにより、ＬＥＤが有するＧａＮ半導体は、スパッタリング法で成膜することも可能である。 In addition, when using LED, you may arrange | position graphene or graphite under the electrode and nitride semiconductor of LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Thus, by providing graphene or graphite, a nitride semiconductor such as an n-type GaN semiconductor having a crystal can be easily formed thereon. Furthermore, a p-type GaN semiconductor having a crystal or the like can be provided thereon to form an LED. Note that an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor having a crystal. Note that the GaN semiconductor included in the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor included in the LED can be formed by a sputtering method.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態７）
本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した電子機器について説明する。 (Embodiment 7)
In this embodiment, electronic devices using a transistor or the like according to one embodiment of the present invention will be described.
＜電子機器＞
本発明の一態様に係る半導体装置は、表示機器、パーソナルコンピュータ、記録媒体を備えた画像再生装置（代表的にはＤＶＤ：Ｄｉｇｉｔａｌ　Ｖｅｒｓａｔｉｌｅ　Ｄｉｓｃ等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置）に用いることができる。その他に、本発明の一態様に係る半導体装置を用いることができる電子機器として、携帯電話、携帯型を含むゲーム機、携帯データ端末、電子書籍端末、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、ナビゲーションシステム、音響再生装置（カーオーディオ、デジタルオーディオプレイヤー等）、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機（ＡＴＭ）、自動販売機などが挙げられる。これら電子機器の具体例を図３１に示す。 <Electronic equipment>
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. It is done. Specific examples of these electronic devices are shown in FIGS.
図３１（Ａ）は携帯型ゲーム機であり、筐体９０１、筐体９０２、表示部９０３、表示部９０４、マイクロフォン９０５、スピーカー９０６、操作キー９０７、スタイラス９０８等を有する。なお、図３１（Ａ）に示した携帯型ゲーム機は、２つの表示部９０３と表示部９０４とを有しているが、携帯型ゲーム機が有する表示部の数は、これに限定されない。 FIG. 31A illustrates a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 31A includes two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.
図３１（Ｂ）は携帯データ端末であり、第１筐体９１１、第２筐体９１２、第１表示部９１３、第２表示部９１４、接続部９１５、操作キー９１６等を有する。第１表示部９１３は第１筐体９１１に設けられており、第２表示部９１４は第２筐体９１２に設けられている。そして、第１筐体９１１と第２筐体９１２とは、接続部９１５により接続されており、第１筐体９１１と第２筐体９１２の間の角度は、接続部９１５により変更が可能である。第１表示部９１３における映像を、接続部９１５における第１筐体９１１と第２筐体９１２との間の角度にしたがって、切り替える構成としてもよい。また、第１表示部９１３および第２表示部９１４の少なくとも一方に、位置入力装置としての機能が付加された表示装置を用いるようにしてもよい。なお、位置入力装置としての機能は、表示装置にタッチパネルを設けることで付加することができる。または、位置入力装置としての機能は、フォトセンサとも呼ばれる光電変換素子を表示装置の画素部に設けることでも、付加することができる。 FIG. 31B illustrates a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image | video in the 1st display part 913 according to the angle between the 1st housing | casing 911 and the 2nd housing | casing 912 in the connection part 915. FIG. In addition, a display device in which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.
図３１（Ｃ）はノート型パーソナルコンピュータであり、筐体９２１、表示部９２２、キーボード９２３、ポインティングデバイス９２４等を有する。 FIG. 31C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.
図３１（Ｄ）は電気冷凍冷蔵庫であり、筐体９３１、冷蔵室用扉９３２、冷凍室用扉９３３等を有する。 FIG. 31D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.
図３１（Ｅ）はビデオカメラであり、第１筐体９４１、第２筐体９４２、表示部９４３、操作キー９４４、レンズ９４５、接続部９４６等を有する。操作キー９４４およびレンズ９４５は第１筐体９４１に設けられており、表示部９４３は第２筐体９４２に設けられている。そして、第１筐体９４１と第２筐体９４２とは、接続部９４６により接続されており、第１筐体９４１と第２筐体９４２の間の角度は、接続部９４６により変更が可能である。表示部９４３における映像を、接続部９４６における第１筐体９４１と第２筐体９４２との間の角度にしたがって切り替える構成としてもよい。 FIG. 31E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. It is good also as a structure which switches the image | video in the display part 943 according to the angle between the 1st housing | casing 941 and the 2nd housing | casing 942 in the connection part 946. FIG.
図３１（Ｆ）は自動車であり、車体９５１、車輪９５２、ダッシュボード９５３、ライト９５４等を有する。 FIG. 31F illustrates an automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
なお、以上の実施の形態において、本発明の一態様について述べた。ただし、本発明の一態様は、これらに限定されない。つまり、本実施の形態などでは、様々な発明の態様が記載されているため、本発明の一態様は、特定の態様に限定されない。例えば、本発明の一態様として、トランジスタのチャネル形成領域、ソース領域、ドレイン領域などが、酸化物半導体を有する場合の例を示したが、本発明の一態様は、これに限定されない。場合によっては、または、状況に応じて、本発明の一態様における様々なトランジスタ、トランジスタのチャネル形成領域、または、トランジスタのソース領域、ドレイン領域などは、様々な半導体を有していてもよい。場合によっては、または、状況に応じて、本発明の一態様における様々なトランジスタ、トランジスタのチャネル形成領域、または、トランジスタのソース領域、ドレイン領域などは、例えば、シリコン、ゲルマニウム、シリコンゲルマニウム、炭化シリコン、ガリウムヒ素、アルミニウムガリウムヒ素、インジウムリン、窒化ガリウム、または、有機半導体などの少なくとも一つを有していてもよい。または例えば、場合によっては、または、状況に応じて、本発明の一態様における様々なトランジスタ、トランジスタのチャネル形成領域、または、トランジスタのソース領域、ドレイン領域などは、酸化物半導体を有していなくてもよい。 Note that one embodiment of the present invention has been described in the above embodiment. Note that one embodiment of the present invention is not limited thereto. In other words, in the present embodiment and the like, various aspects of the invention are described, and thus one embodiment of the present invention is not limited to a particular embodiment. For example, although an example in which the channel formation region, the source region, the drain region, and the like of the transistor include an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. In some cases or depending on circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source region, a drain region, and the like of the transistor may include various semiconductors. Depending on circumstances or circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source region, a drain region, and the like of the transistor can be formed using, for example, silicon, germanium, silicon germanium, or silicon carbide. Gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, depending on circumstances or circumstances, various transistors, channel formation regions of the transistors, source regions and drain regions of the transistors do not include an oxide semiconductor in one embodiment of the present invention. May be.
本実施例では、トランジスタなどの導電体として用いる、Ｗ−Ｓｉ膜の結晶性を調査した結果について説明する。 In this embodiment, the results of examining the crystallinity of a W-Si film used as a conductor such as a transistor will be described.
試料は、Ｓｉウェハ上に厚さが５０ｎｍの酸化シリコン（ＳｉＯｘ）を熱酸化法によって形成し、その後、スパッタリング装置により、Ｗ−Ｓｉ膜を５０ｎｍの厚さで形成して作製した。 A sample was formed by forming silicon oxide (SiOx) having a thickness of 50 nm on a Si wafer by a thermal oxidation method, and then forming a W-Si film with a thickness of 50 nm by a sputtering apparatus.
Ｗ−Ｓｉ膜の成膜は、Ｗ−Ｓｉ（Ｗ：Ｓｉ＝１：２．７（原子数比））ターゲットを用いたスパッタリング装置によって、アルゴンガス５０ｓｃｃｍを含む雰囲気にて圧力を０．４Ｐａに制御し、基板温度は室温、ターゲットにＤＣ電源により出力１ｋＷを印加して行った。 The W-Si film is formed using a sputtering apparatus using a W-Si (W: Si = 1: 2.7 (atomic ratio)) target at a pressure of 0.4 Pa in an atmosphere containing argon gas 50 sccm. The substrate temperature was controlled at room temperature, and an output of 1 kW was applied to the target from a DC power source.
以上のようにして作製した試料を、ＸＲＤにより測定した結果を図３２（Ａ）に示す。なお、比較のため、Ｗ−Ｓｉ膜の代わりにＷ膜を厚さ５０ｎｍ形成して作製した試料をＸＲＤにより測定した結果を図３２（Ｂ）に示す。 FIG. 32A shows the result of measuring the sample manufactured as described above by XRD. For comparison, FIG. 32B shows the result of XRD measurement of a sample manufactured by forming a W film with a thickness of 50 nm instead of the W—Si film.
図３２（Ａ）より、Ｗ−Ｓｉ膜は、ＸＲＤ測定により結晶構造を示すピークが無く、非晶質であることがわかった。また、図３２（Ｂ）より、Ｗ膜はＸＲＤ測定により４０°付近にα—Ｗ構造起因の結晶を示すピークが見られた。 FIG. 32A shows that the W—Si film is amorphous with no peak indicating a crystal structure by XRD measurement. In addition, from FIG. 32B, the W film showed a peak showing crystals due to the α-W structure in the vicinity of 40 ° by XRD measurement.
この結果より、Ｗ−Ｓｉ膜は、非晶質な膜であることがわかった。 From this result, it was found that the W—Si film was an amorphous film.
以上の結果より、Ｗ−Ｓｉ膜をトランジスタのゲート電極に用いることによって、イオン注入などにおいて注入されるイオンがゲート電極を突き抜けることを抑制し、良好な電気特性を有するトランジスタを作製することができることがわかった。 From the above results, by using the W-Si film as the gate electrode of the transistor, it is possible to suppress the ions implanted in the ion implantation or the like from penetrating the gate electrode and to manufacture a transistor having favorable electrical characteristics. I understood.
１０　　トランジスタ
１１　　トランジスタ
１２　　トランジスタ
１３　　トランジスタ
１４　　トランジスタ
１００　　基板
１０１　　絶縁体
１０２　　導電体
１０３　　絶縁体
１０４　　絶縁体
１０５　　絶縁体
１０６　　絶縁体
１０６ａ　　絶縁体
１０６ｂ　　半導体
１０６ｃ　　絶縁体
１０７ａ　　低抵抗領域
１０７ｂ　　低抵抗領域
１０８ａ　　導電体
１０８ｂ　　導電体
１０９ａ　　導電体
１０９ｂ　　導電体
１１２　　絶縁体
１１４　　導電体
１１５　　絶縁体
１１６　　絶縁体
１１８　　絶縁体
１１９　　ドーパント
１２６ａ　　領域
１２６ｂ　　領域
１２６ｃ　　領域
１２６ｄ　　領域
１２６ｅ　　領域
１２７ｃ　　領域
１４０　　絶縁体
１４２　　絶縁体
１４４　　領域
２００　　撮像装置
２０１　　スイッチ
２０２　　スイッチ
２０３　　スイッチ
２１０　　画素部
２１１　　画素
２１２　　副画素
２１２Ｂ　　副画素
２１２Ｇ　　副画素
２１２Ｒ　　副画素
２２０　　光電変換素子
２３０　　画素回路
２３１　　配線
２４７　　配線
２４８　　配線
２４９　　配線
２５０　　配線
２５３　　配線
２５４　　フィルタ
２５４Ｂ　　フィルタ
２５４Ｇ　　フィルタ
２５４Ｒ　　フィルタ
２５５　　レンズ
２５６　　光
２５７　　配線
２６０　　周辺回路
２７０　　周辺回路
２８０　　周辺回路
２９０　　周辺回路
２９１　　光源
３００　　シリコン基板
３１０　　層
３２０　　層
３３０　　層
３４０　　層
３５１　　トランジスタ
３５２　　トランジスタ
３５３　　トランジスタ
３６０　　フォトダイオード
３６１　　アノード
３６３　　低抵抗領域
３７０　　プラグ
３７１　　配線
３７２　　配線
３７３　　配線
３８０　　絶縁体
４５０　　半導体基板
４５２　　絶縁体
４５４　　導電体
４５６　　領域
４６０　　領域
４６２　　絶縁体
４６４　　絶縁体
４６６　　絶縁体
４６８　　絶縁体
４７２ａ　　領域
４７２ｂ　　領域
４７４ａ　　導電体
４７４ｂ　　導電体
４７４ｃ　　導電体
４７６ａ　　導電体
４７６ｂ　　導電体
４７８ａ　　導電体
４７８ｂ　　導電体
４７８ｃ　　導電体
４８０ａ　　導電体
４８０ｂ　　導電体
４８０ｃ　　導電体
４８９　　絶縁体
４９０　　絶縁体
４９１　　絶縁体
４９２　　絶縁体
４９３　　絶縁体
４９４　　絶縁体
４９５　　絶縁体
４９６ａ　　導電体
４９６ｂ　　導電体
４９６ｃ　　導電体
４９６ｄ　　導電体
４９８ａ　　導電体
４９８ｂ　　導電体
４９８ｃ　　導電体
５０４　　導電体
５０７ａ　　領域
５０７ｂ　　領域
５１１　　絶縁体
５１４　　導電体
５２１　　ルーティングスイッチエレメント
５２２　　ロジックエレメント
５２３　　コンフィギュレーションメモリ
５２４　　ルックアップテーブル
５２５　　レジスタ
５２６　　セレクタ
５２７　　コンフィギュレーションメモリ
７００　　基板
７０１　　絶縁体
７０２ａ　　導電体
７０２ｂ　　導電体
７０４　　絶縁体
７０６ａ　　絶縁体
７０６ｂ　　半導体
７０６ｃ　　絶縁体
７０７ａ　　領域
７０７ｂ　　領域
７１１　　絶縁体
７１２　　絶縁体
７１２ａ　　絶縁体
７１２ｂ　　絶縁体
７１４ａ　　導電体
７１４ｂ　　導電体
７１６　　絶縁体
７１９　　発光素子
７２０　　絶縁体
７２１　　絶縁体
７３１　　端子
７３２　　ＦＰＣ
７３３ａ　　配線
７３４　　シール材
７３５　　駆動回路
７３６　　駆動回路
７３７　　画素
７４１　　トランジスタ
７４２　　容量素子
７４３　　スイッチ素子
７４４　　信号線
７５０　　基板
７５１　　トランジスタ
７５２　　容量素子
７５３　　液晶素子
７５４　　走査線
７５５　　信号線
７８１　　導電体
７８２　　発光層
７８３　　導電体
７８４　　隔壁
７９１　　導電体
７９２　　絶縁体
７９３　　液晶層
７９４　　絶縁体
７９５　　スペーサ
７９６　　導電体
７９７　　基板
９０１　　筐体
９０２　　筐体
９０３　　表示部
９０４　　表示部
９０５　　マイクロフォン
９０６　　スピーカー
９０７　　操作キー
９０８　　スタイラス
９１１　　筐体
９１２　　筐体
９１３　　表示部
９１４　　表示部
９１５　　接続部
９１６　　操作キー
９２１　　筐体
９２２　　表示部
９２３　　キーボード
９２４　　ポインティングデバイス
９３１　　筐体
９３２　　冷蔵室用扉
９３３　　冷凍室用扉
９４１　　筐体
９４２　　筐体
９４３　　表示部
９４４　　操作キー
９４５　　レンズ
９４６　　接続部
９５１　　車体
９５２　　車輪
９５３　　ダッシュボード
９５４　　ライト
１１８９　　ＲＯＭインターフェース
１１９０　　基板
１１９１　　ＡＬＵ
１１９２　　ＡＬＵコントローラ
１１９３　　インストラクションデコーダ
１１９４　　インタラプトコントローラ
１１９５　　タイミングコントローラ
１１９６　　レジスタ
１１９７　　レジスタコントローラ
１１９８　　バスインターフェース
１１９９　　ＲＯＭ
１２００　　記憶素子
１２０１　　回路
１２０２　　回路
１２０３　　スイッチ
１２０４　　スイッチ
１２０６　　論理素子
１２０７　　容量素子
１２０８　　容量素子
１２０９　　トランジスタ
１２１０　　トランジスタ
１２１３　　トランジスタ
１２１４　　トランジスタ
１２２０　　回路
２１００　　トランジスタ
２２００　　トランジスタ
３００１　　配線
３００２　　配線
３００３　　配線
３００４　　配線
３００５　　配線
３２００　　トランジスタ
３３００　　トランジスタ
３４００　　容量素子
４００１　　配線
４００３　　配線
４００５　　配線
４００６　　配線
４００７　　配線
４００８　　配線
４００９　　配線
４０２１　　層
４０２２　　層
４０２３　　層
４１００　　トランジスタ
４２００　　トランジスタ
４３００　　トランジスタ
４４００　　トランジスタ
４５００　　容量素子
４６００　　容量素子 10 transistor 11 transistor 12 transistor 13 transistor 14 transistor 100 substrate 101 insulator 102 conductor 103 insulator 104 insulator 105 insulator 106 insulator 106a insulator 106b semiconductor 106c insulator 107a low resistance region 107b low resistance region 108a conductor 108b Conductor 109a Conductor 109b Conductor 112 Insulator 114 Conductor 115 Insulator 116 Insulator 118 Insulator 119 Dopant 126a Region 126b Region 126c Region 126d Region 126e Region 127c Region 140 Insulator 142 Insulator 144 Region 200 Imaging device 201 Switch 202 switch 203 switch 210 pixel portion 211 pixel 212 subpixel 212B subpixel 212G subpixel 212R Pixel 220 Photoelectric conversion element 230 Pixel circuit 231 wiring 247 wiring 248 wiring 249 wiring 250 wiring 253 wiring 254 filter 254B filter 254G filter 254R filter 255 lens 256 light 257 wiring 260 peripheral circuit 270 peripheral circuit 280 peripheral circuit 290 peripheral circuit 291 light source 300 silicon Substrate 310 layer 320 layer 330 layer 340 layer 351 transistor 352 transistor 353 transistor 360 photodiode 361 anode 363 low resistance region 370 plug 371 wiring 372 wiring 373 wiring 380 insulator 450 semiconductor substrate 452 insulator 454 conductor 456 region 460 region 462 insulation Body 464 insulator 466 insulator 468 insulator 472a region 472b region 474 Conductor 474b conductor 474c conductor 476a conductor 476b conductor 478a conductor 478b conductor 478c conductor 480a conductor 480b conductor 480c conductor 489 insulator 490 insulator 491 insulator 492 insulator 493 insulator 494 insulator 495 insulator 496a conductor 496b conductor 496c conductor 496d conductor 498a conductor 498b conductor 498c conductor 504 conductor 507a region 507b region 511 insulator 514 conductor 521 routing switch element 522 logic element 523 configuration memory 524 look Uptable 525 Register 526 Selector 527 Configuration memory 700 Substrate 701 Insulator 702a Conductor 702 Conductor 704 Insulator 706a Insulator 706b Semiconductor 706c Insulator 707a Region 707b Region 711 Insulator 712 Insulator 712a Insulator 712b Insulator 714a Conductor 714b Conductor 716 Insulator 719 Light emitting element 720 Insulator 721 Insulator 731 Terminal 732 FPC
733a wiring 734 sealant 735 drive circuit 736 drive circuit 737 pixel 741 transistor 742 capacitor element 743 switch element 744 signal line 750 substrate 751 transistor 752 capacitor element 753 liquid crystal element 754 scan line 755 signal line 781 conductor 782 light emitting layer 783 conductor 784 Partition 791 Conductor 792 Insulator 793 Liquid crystal layer 794 Insulator 795 Spacer 796 Conductor 797 Substrate 901 Housing 902 Housing 903 Display portion 904 Display portion 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display portion 914 Display unit 915 Connection unit 916 Operation key 921 Case 922 Display unit 923 Keyboard 924 Pointing device 931 Case 932 Refrigerated room Door 933 a freezer door 941 housing 942 housing 943 display unit 944 operation keys 945 lens 946 connecting portions 951 body 952 wheel 953 dashboard 954 Light 1189 ROM interface 1190 substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1200 Memory element 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic element 1207 Capacitor element 1208 Capacitor element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Capacitor 3400 Capacitor Element 4001 Wiring 4003 Wiring 4005 Wiring 4006 Wiring 4007 Wiring 4008 Wiring 4009 Wiring 4021 Layer 4022 Layer 4023 Layer 4100 Transistor 4200 Transistor 4300 Transistor 4400 Transistor 4500 Capacitance element 4600 Capacitance element

Claims (8)

  1. 　第１乃至第３の部分を有する半導体と、
    　前記半導体上の第１の絶縁体と、
    　前記第１の絶縁体上の第１の導電体と、を有し、
    　前記第１の導電体は、前記第１の部分と重なる領域を有し、
    　前記第１の導電体は、タングステンと、シリコン、炭素、ゲルマニウム、スズ、アルミニウムまたはニッケルから選ばれた一以上の元素と、を有する領域を有し、
    　前記第２の部分は、リン、ホウ素、窒素、アルゴンまたはキセノンのいずれか一以上を有し、
    　前記第３の部分は、リン、ホウ素、窒素、アルゴンまたはキセノンのいずれか一以上を有し、
    　前記第１の導電体は、非晶質である領域を有することを特徴とする半導体装置。     A semiconductor having first to third portions;
    A first insulator on the semiconductor;
    A first conductor on the first insulator;
    The first conductor has a region overlapping the first portion;
    The first conductor has a region having tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, or nickel;
    The second portion has one or more of phosphorus, boron, nitrogen, argon or xenon,
    The third portion has one or more of phosphorus, boron, nitrogen, argon or xenon,
    The semiconductor device, wherein the first conductor has an amorphous region.
  2. 　請求項１において、
    　前記第１の導電体は、ラザフォード後方散乱分析により得られるシリコン濃度が５ａｔｏｍｉｃ％以上７０ａｔｏｍｉｃ％以下である領域を有することを特徴とする半導体装置。     In claim 1,
    The semiconductor device, wherein the first conductor has a region where a silicon concentration obtained by Rutherford backscattering analysis is 5 atomic% or more and 70 atomic% or less.
  3. 　請求項１において、
    　前記第１の導電体は、表面にシリコンおよび酸素を有する領域を有し、該領域の厚さは０．２ｎｍ以上２０ｎｍ以下であることを特徴とする半導体装置。     In claim 1,
    The first conductor has a region containing silicon and oxygen on the surface, and the thickness of the region is not less than 0.2 nm and not more than 20 nm.
  4. 　請求項１において、
    　前記半導体は、酸化物半導体を有することを特徴とする半導体装置。     In claim 1,
    The semiconductor device includes an oxide semiconductor.
  5. 　半導体を形成し、
    　前記半導体上に第１の絶縁体を形成し、
    　前記第１の絶縁体上に第１の導電体を形成し、
    　前記第１の導電体をマスクにして、前記半導体にリン、ホウ素、窒素、アルゴンまたはキセノンのいずれか一以上を添加し、
    　前記第１の導電体は、タングステンと、シリコン、炭素、ゲルマニウム、スズまたはニッケルから選ばれた一以上の元素と、を有し、
    　前記第１の導電体は、非晶質である領域を有することを特徴とする半導体装置の作製方法。     Forming a semiconductor,
    Forming a first insulator on the semiconductor;
    Forming a first conductor on the first insulator;
    Using the first conductor as a mask, adding one or more of phosphorus, boron, nitrogen, argon, or xenon to the semiconductor;
    The first conductor includes tungsten and one or more elements selected from silicon, carbon, germanium, tin, or nickel,
    The method for manufacturing a semiconductor device, wherein the first conductor includes an amorphous region.
  6. 　請求項５において、
    　前記添加は、イオン注入により行うことを特徴とする半導体装置の作製方法。     In claim 5,
    A method for manufacturing a semiconductor device, wherein the addition is performed by ion implantation.
  7. 　請求項５または請求項６において、
    　前記第１の導電体は、スパッタリング法を用いて形成することを特徴とする半導体装置の作製方法。     In claim 5 or claim 6,
    The method for manufacturing a semiconductor device, wherein the first conductor is formed by a sputtering method.
  8. 　請求項５または請求項６において、
    　前記第１の導電体は、金属ＣＶＤ法を用いて形成することを特徴とする半導体装置の作製方法。     In claim 5 or claim 6,
    The method for manufacturing a semiconductor device, wherein the first conductor is formed by a metal CVD method.
PCT/IB2016/054012 2015-07-14 2016-07-05 Semiconductor device and method for manufacturing same WO2017009738A1 (en)

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