JPH03280471A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03280471A
JPH03280471A JP7995890A JP7995890A JPH03280471A JP H03280471 A JPH03280471 A JP H03280471A JP 7995890 A JP7995890 A JP 7995890A JP 7995890 A JP7995890 A JP 7995890A JP H03280471 A JPH03280471 A JP H03280471A
Authority
JP
Japan
Prior art keywords
oxide film
gate oxide
film
gate
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7995890A
Other languages
Japanese (ja)
Inventor
Shigeaki Ide
繁章 井手
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP7995890A priority Critical patent/JPH03280471A/en
Publication of JPH03280471A publication Critical patent/JPH03280471A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a gate oxide film of high quality which is excellent in dielectric breakdown strength and oxide film defect density even if a low temperature treatment is employed by a method wherein fluorine ions are implanted into the gate oxide film after or before a gate electrode film is formed on the gate oxide film through a CVD method. CONSTITUTION:A semiconductor substrate 1 is thermally oxidized at a comparatively low temperature by the use of an oxidizing agent to form a gate oxide film 2. Then, a polysilicon film 3 is deposited as a gate electrode film through a vacuum CVD method. In succession, ions of <19>F<+> are implanted into the gate oxide film 2 through the intermediary of the polysilicon film 3 so as to enable their concentration peak to be located in an SiO2 film. Then, the substrate 1 is annealed in an atmosphere of N2 for 30 minutes to combine Si of unsaturated bond with F to saturate for the formation of a gate oxide film 2a doped with fluorine. A process follows, where the polysilicon film 3 is doped with impurities to be lessened in resistance, and the impurity doped film 3 is patterned into a required shape for the formation of a gate electrode 3a.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明は半導体装置の製造方法に関し、さらに詳しく
はMOS LSIなどの半導体装置におけるゲート酸化
膜の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a gate oxide film in a semiconductor device such as a MOS LSI.

(ロ)従来の技術 従来の技術におけるゲート酸化膜の製造方法は、一般的
に半導体基板を熱酸化することにより熱酸化膜を形成し
ているが、半導体装置の高集積化に伴い、このゲート酸
化膜の薄膜化、高品質化が要求されている。また、ゲー
ト酸化膜については、高温で形成する高温酸化処理の方
が良好な膜質を得ることができることは一般的に知られ
ているが、高集積化に必要な薄膜を形成するには、比較
的低温である具体的には1000℃以下の温度下による
酸化処理いわゆる低温酸化処理による膜形成の方が適し
ているため、その低温処理による高品質ゲート酸化膜の
形成が考えられている。
(b) Conventional technology In the conventional technology, a gate oxide film is generally manufactured by thermally oxidizing a semiconductor substrate to form a thermal oxide film. There is a demand for thinner oxide films and higher quality. Regarding gate oxide films, it is generally known that high-temperature oxidation treatment can provide better film quality, but in order to form the thin films necessary for high integration, Since it is more suitable to form a film by oxidation treatment at a low temperature, specifically, at a temperature of 1000° C. or lower, so-called low-temperature oxidation treatment, formation of a high-quality gate oxide film by such low-temperature treatment is being considered.

(ハ)発明が解決しようとする課題 しかしながら、従来の低温酸化処理、例えば950℃の
温度下でHCIガスとO,ガスの混合ガスを酸化剤とし
て用いて形成したゲート酸化膜は、高温酸化処理に比べ
ると絶縁破壊耐圧強度、酸化膜欠陥密度の面で劣ってい
た。
(c) Problems to be Solved by the Invention However, the gate oxide film formed by conventional low-temperature oxidation treatment, for example, at a temperature of 950°C using a mixed gas of HCI gas and O gas as an oxidizing agent, cannot be processed by high-temperature oxidation treatment. It was inferior in terms of dielectric breakdown strength and oxide film defect density.

この発明は以上の事情を考慮してなされた乙ので、上記
の問題を解消し、低温処理を用いても絶縁破壊耐圧強度
、酸化膜欠陥密度に優れた高品質なゲート酸化膜を形成
しうる方法を提供するものである。
This invention has been made in consideration of the above circumstances, so it is possible to solve the above problems and form a high-quality gate oxide film with excellent dielectric breakdown strength and oxide film defect density even using low-temperature processing. The present invention provides a method.

(ニ)課題を解決するための手段 この発明は、半導体基板を任温酸什1fゲート酸化膜を
形成し、次いでそのゲート酸化股上にCVD法によりゲ
ート電極膜の形成を行う前か後に、ゲート酸化膜にフッ
素イオ、ンを注入することを特徴とする半導体装置の製
造方法である。
(d) Means for Solving the Problems This invention provides a method for forming a 1f gate oxide film on a semiconductor substrate using a controlled oxidation film, and then forming a gate electrode film on the gate oxide film by CVD method before or after the gate oxide film is formed. This method of manufacturing a semiconductor device is characterized by implanting fluorine ions and ions into an oxide film.

この発明において低温酸化とは、tooo℃以下の比較
的低温の温度下で半導体表面層を酸化剤を用いた酸化性
雰囲気下で熱酸化することを意味し、例えばSi基板表
面層においては熱酸化膜として50〜200人の薄膜化
したStow膜が形成される。
In this invention, low-temperature oxidation refers to thermally oxidizing a semiconductor surface layer in an oxidizing atmosphere using an oxidizing agent at a relatively low temperature of 100° C. or less. For example, in the surface layer of a Si substrate, thermal oxidation A thin Stow film of 50 to 200 people is formed as a film.

そして低温酸化として特に好ましい温度とは950℃で
ある。
A particularly preferable temperature for low-temperature oxidation is 950°C.

また、熱酸化法としては周知のものが用いられ、具体的
には(1)ドライO1酸化法、(2)酸化炉に入る前の
酸素を高純度の脱イオン水の容器に通過させるウェット
ら酸化法、(3)キャリアガスを用いず、容器に収納さ
れた高純度の脱イオン水を沸騰した状態にして酸化剤と
して用いろスチーム酸化法、あるいは(4)ドライ0.
に数%のHCI、C1,。
In addition, well-known thermal oxidation methods are used, specifically (1) dry O1 oxidation method, (2) wet method in which oxygen is passed through a container of high-purity deionized water before entering the oxidation furnace. oxidation method, (3) steam oxidation method in which high-purity deionized water stored in a container is boiled and used as an oxidizing agent without using a carrier gas, or (4) dry 0.
and several percent HCI, C1,.

C,HCl、等を混ぜた雰囲気中で酸化するIIcII
c法、さらには(4)酸素を水素、窒素等で希釈して酸
化する方法か挙げられる。
IIcII oxidizes in an atmosphere containing C, HCl, etc.
Examples include method c, and method (4) in which oxygen is diluted with hydrogen, nitrogen, etc. and then oxidized.

この発明において、フッ素イオンを(a)ゲート電極膜
の形成を行った後に注入するイオン注入条件としては、
イオン種として11F°を用い、注入エネルギー(加速
電圧)を好ましくは50〜70keYに、より好ましく
は60keVに設定して、Foのドーズ量がto”〜t
o”am−”になるよう、より好ましくは1〜2X 1
0”cm−”になるまでゲート酸化膜中にピークを持た
せて注入する。その後のアニール処理によって、ゲート
酸化膜、例えば5ins膜の結晶欠陥の回復、並びにF
oの拡散が決定される。
In this invention, the ion implantation conditions for implanting fluorine ions after (a) forming the gate electrode film are as follows:
Using 11F as the ion species, the implantation energy (acceleration voltage) is preferably set to 50 to 70 keY, more preferably 60 keV, and the Fo dose is to'' to t.
o"am-", more preferably 1 to 2X 1
It is implanted into the gate oxide film with a peak until it reaches 0"cm-". The subsequent annealing process recovers crystal defects in the gate oxide film, for example, the 5ins film, and
The spread of o is determined.

すなわち、F原子がSi基板とその表面層に形成された
ゲート酸化膜としての5ins膜との界面のSiの不飽
和結合を飽和させ、上記界面状態を安定化するためには
、アニール温度が800〜1000℃でかつアニール時
間が30〜90分に設定されるのが好ましい。その際、
N、ガスや不活性ガス等のキャリアガスが用いられる。
That is, in order for F atoms to saturate the unsaturated bonds of Si at the interface between the Si substrate and the 5ins film as a gate oxide film formed on its surface layer, and to stabilize the above interface state, the annealing temperature must be 800°C. Preferably, the temperature is ~1000°C and the annealing time is set to 30 to 90 minutes. that time,
A carrier gas such as N, gas, or inert gas is used.

なお、アニール温度は必ずしも酸化温度と一致させる必
要はない。
Note that the annealing temperature does not necessarily have to match the oxidation temperature.

この発明において、フッ素イオンを(b)ゲート電極膜
の形成前に注入するイオン注入条件としては、イオン注
入として19F°を用い、イオン注入によりSi0g膜
がダメージを受けない程度の5〜10keVの注入エネ
ルギーが好ましく、tols〜10110l7”のFo
のドーズ量が好ましい。その後のアニール処理は、不飽
和結合のSiをFと結合させて飽和させ得るに足りるア
ニール温度およびアニール時間の適性な調整により、上
記(a)の場合と同様のアニール効果が得られる。アニ
ール温度およびアニール時間は具体的には1000℃以
上、60分以上の高温長時間アニールである。なお、こ
のアニール温度は必ずしも酸化温間と一致させる必要は
ない。
In this invention, the ion implantation conditions for implanting fluorine ions before forming the gate electrode film (b) are as follows: 19 F° is used for ion implantation, and the implantation is at 5 to 10 keV to the extent that the Si0g film is not damaged by ion implantation. Energy is preferred, tols ~ 10110l7” Fo
A dose of . In the subsequent annealing treatment, the same annealing effect as in case (a) above can be obtained by appropriately adjusting the annealing temperature and annealing time to be sufficient to combine unsaturated Si with F and saturate it. Specifically, the annealing temperature and the annealing time are high-temperature and long-time annealing at 1000° C. or more and 60 minutes or more. Note that this annealing temperature does not necessarily have to match the oxidation temperature.

この発明における半導体基板としてはSi基板が最も好
ましいものとして挙げられる。
As the semiconductor substrate in this invention, a Si substrate is most preferred.

この際、フッ素をゲート酸化膜としてのSiOx膜に注
入する方法により、フッ素原子がSiO,/Si界面の
Siの不飽和結合を飽和でき、5iOt/St界面状態
を安定化でき、それによって5rOtの絶鰻碑總耐午論
管本白ト六仕^ルλt1じ−鯵什睡ケ陥密度を低減させ
ることができる。これは、Si −0の結合エネルギー
が369.OKJmol−’  一方SiFの結合エネ
ルギーが541.01[Jmol−’と両結合エネルギ
ーがほぼ等しいことから、F原子がSiと結合して安定
化するからである。
At this time, by implanting fluorine into the SiOx film as the gate oxide film, fluorine atoms can saturate the unsaturated bonds of Si at the SiO, /Si interface, stabilizing the 5iOt/St interface state, thereby stabilizing the 5rOt It is possible to reduce the density of horse mackerel sleep. This means that the binding energy of Si-0 is 369. OKJmol-' On the other hand, since the bond energy of SiF is 541.01[Jmol-' and both bond energies are almost equal, the F atom is stabilized by bonding with Si.

(ホ)作用 半導体基板上に低温酸化によってゲート酸化膜を形成し
た後、ゲート酸化膜上にCVD法によりゲート電極膜の
形成を行う前か後に、ゲート酸化膜にフッ素イオンを注
入し、その後公知の技術としてCVD法によりゲート電
極を形成し、該ゲート電極を所望の影状にパターニング
し、さらに半導体基板上にソース、ドレインとしての不
純物拡散領域を形成するようにしたので、低温酸化処理
を用いても薄膜のゲート酸化膜における絶縁耐圧強度の
低下、酸化膜欠陥密度の増加をそれぞれ防止できる。
(e) After forming a gate oxide film on the working semiconductor substrate by low-temperature oxidation, before or after forming a gate electrode film on the gate oxide film by CVD method, fluorine ions are implanted into the gate oxide film, and then fluorine ions are implanted into the gate oxide film. As a technique for forming a gate electrode using the CVD method, patterning the gate electrode into a desired shadow shape, and further forming impurity diffusion regions as a source and drain on the semiconductor substrate, low-temperature oxidation treatment is used. However, it is possible to prevent a decrease in dielectric strength and an increase in oxide film defect density in a thin gate oxide film.

(へ)実施例 以下図に示す実施例に基づいてこの発明を詳述ガス −
r? 松   ″ 刺 1− ) −ツー−/n にト
n日1者胆中士 刺 2、ものではない。
(f) Examples This invention will be described in detail based on the examples shown in the following figures.
r? Pine ``Thorn 1-) -Two-/n to n days 1 person in the middle of the day 2, it's not a thing.

第1図において、高集積の半導体装置は、以下の製造方
法によって形成される。すなわち、半導体基板lを比較
的低い温度950℃で、酸化剤HCl10.を用いて熱
酸化により酸化し、ゲート酸化膜(SiOx 200人
)2を形成する。次に減圧CVD法によりゲート電極膜
としてのポリシリコン膜(poly Si 1500人
)3を堆積する。次にこのポリシリコン膜3を介し、ゲ
ート酸化膜2中にイオンインプランテーションにより、
イオン11F°を注入エネルギー60 key 、  
ドーズ量1.78X 10”1ons/cm″の条件下
で5ift中にピークを持たせて注入する。次いで80
0℃〜1000℃の温度範囲、この実施例では950℃
でN、ガス雰囲気中に30分間アニールすることにより
、不飽和結合のSiをFと結合させ飽和させる。ゲート
酸化膜における結晶欠陥の回復、フッ素の拡散は、前述
したようにアニール温度と時間によって決まる。第1図
すに示す2aは、フッ素が注入されたゲート酸化膜であ
る。
In FIG. 1, a highly integrated semiconductor device is formed by the following manufacturing method. That is, the semiconductor substrate l is heated to a relatively low temperature of 950° C. and treated with an oxidizing agent HCl 10. A gate oxide film (200 layers of SiOx) 2 is formed by thermal oxidation. Next, a polysilicon film (1500 polysilicon) 3 is deposited as a gate electrode film by low pressure CVD. Next, by ion implantation into the gate oxide film 2 through this polysilicon film 3,
Ions are implanted at 11 F° with an energy of 60 key,
It is implanted at a dose of 1.78×10"1 ounce/cm" with a peak within 5 ift. Then 80
Temperature range from 0°C to 1000°C, in this example 950°C
By annealing for 30 minutes in a N gas atmosphere, the unsaturated bonds of Si are combined with F and saturated. Recovery of crystal defects in the gate oxide film and diffusion of fluorine are determined by the annealing temperature and time, as described above. 2a shown in FIG. 1 is a gate oxide film into which fluorine is implanted.

次にポリシリコン膜3中に低抵抗化のための不純物をド
ープし、これを所望の形状にパターニングし、ゲート電
極3aを形成する(第1図C参照)。
Next, impurities are doped into the polysilicon film 3 to lower the resistance, and this is patterned into a desired shape to form a gate electrode 3a (see FIG. 1C).

なお、フッ素の注入は、ポリシリコン膜3を介せず、直
接酸化膜2上から行っても良いが、ゲート酸化膜2がイ
オン注入によるダメージを受けて劣化する危険性がある
。この場合は、注入エネルギーの適性化、注入後のアニ
ール条件の適性化等によりゲート酸化膜を回復できる可
能性がある。次に半導体基板l上に、公知の方法により
不純物拡散領域すなわち、ソース、ドレインを形成して
半導体装置を完成する。
Although fluorine may be implanted directly onto the oxide film 2 without intervening the polysilicon film 3, there is a risk that the gate oxide film 2 will be damaged and deteriorated by the ion implantation. In this case, there is a possibility that the gate oxide film can be recovered by optimizing the implantation energy, optimizing the post-implantation annealing conditions, etc. Next, impurity diffusion regions, that is, a source and a drain are formed on the semiconductor substrate l by a known method to complete a semiconductor device.

次に、このようにして得られたゲート酸化膜について絶
縁破壊耐圧強度、酸化膜欠陥密度の測定結果を第2図に
ヒストグラムで示す。同様に、従来方法で形成したゲー
ト酸化膜についての測定結果を比較例として第3図に示
す。第2図および第3図において、横軸はBREAKD
OfN FIELD(絶縁破壊電圧)を示し、縦軸はウ
ェハ面内の各測定点においてBREAKDOIN FI
ELDがどれほどであったかを表すFREQUENCY
(割合)を示す。なお、測定は4ma+”のパターンで
行い、判定電流は 1μAとした。
Next, the measurement results of the dielectric breakdown strength and oxide film defect density of the gate oxide film thus obtained are shown in a histogram in FIG. Similarly, the measurement results for a gate oxide film formed by the conventional method are shown in FIG. 3 as a comparative example. In Figures 2 and 3, the horizontal axis is BREAKD
OfN FIELD (dielectric breakdown voltage) is shown, and the vertical axis is BREAKDOIN FI at each measurement point within the wafer surface.
FREQUENCY indicating how much ELD was
(percentage). Note that the measurement was performed using a 4ma+'' pattern, and the judgment current was 1 μA.

また、欠陥密度は8 MY/cs以上の耐圧があったも
のをPa5sとして、以下の方法により求めた。
Further, the defect density was determined by the following method, with Pa5s being those with a breakdown voltage of 8 MY/cs or more.

P:Pa5s率 S:測定面積 第2図のAと第3図のBとを比較すると、Aの方がBよ
りもFREQOENCYが高((Pass率が高く)、
また、CとDはそれぞれ1回目の測定でI  MY/c
m以下で破壊したものを示しており、CはDよりFRE
QUENCYか低く(低電界破壊が低く)なっている。
P: Pa5s rate S: Measurement area Comparing A in Figure 2 and B in Figure 3, A has a higher FREQOENCY (higher pass rate) than B.
In addition, C and D are each I MY/c at the first measurement.
It shows the one destroyed at less than m, and C is FRE than D.
QUENCY is low (low electric field breakdown is low).

また、実施例におけるゲート酸化膜の欠陥密度が0.5
9cm−”に対して従来例のそれは2.76cm−”で
あった。したがってこの実施例の方が従来のゲート酸化
膜よりも良好な膜質を有するゲート酸化膜に形成されて
いることが分かる。
In addition, the defect density of the gate oxide film in the example was 0.5
9 cm-'', whereas that of the conventional example was 2.76 cm-''. Therefore, it can be seen that the gate oxide film of this example has better film quality than the conventional gate oxide film.

(ト)発明の効果 この発明によれば、半導体基板上に低温酸化によってゲ
ート酸化膜を形成した後、該ゲート酸化膜中にフッ素を
注入するようにしたので、低温酸化処理を用いてら絶縁
破壊耐圧強度および酸化膜欠陥密度に優れた高品質のゲ
ート酸化膜を得ることができる。したがってゲート酸化
膜の薄膜化が実現され、半導体装置の高集積化を図るこ
とができる。
(G) Effects of the Invention According to the present invention, after forming a gate oxide film on a semiconductor substrate by low-temperature oxidation, fluorine is implanted into the gate oxide film, so that dielectric breakdown can be prevented by using low-temperature oxidation treatment. A high-quality gate oxide film with excellent pressure resistance and oxide film defect density can be obtained. Therefore, the gate oxide film can be made thinner, and the semiconductor device can be highly integrated.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例の半導体装置の製造方法を
説明する工程説明図、第2図は上記実施例におけるゲー
ト酸化膜の絶縁耐圧破壊の程度を示す特性図、第3図は
上記実施例と比較するための従来例の第2図相当図であ
る。 l・・・・・・半導体基板、 2・・・・・・ゲート酸
化膜、2a−・・・・・フッ素注入ゲート酸化膜、3・
・・・・・ポリシリコン膜、3a・・・・・・ゲート電
極。 第1図 a 第1図 す 第1図 第3図 M九MズNJr度 =2.76c貫2
FIG. 1 is a process explanatory diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a characteristic diagram showing the degree of dielectric breakdown voltage breakdown of the gate oxide film in the embodiment described above, and FIG. FIG. 2 is a diagram corresponding to FIG. 2 of a conventional example for comparison with the embodiment. l...Semiconductor substrate, 2...Gate oxide film, 2a-...Fluorine implantation gate oxide film, 3.
...Polysilicon film, 3a...Gate electrode. Fig. 1 a Fig. 1 Fig. 1 Fig. 3 M9Ms NJr degree = 2.76c through 2

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板を低温酸化してゲート酸化膜を形成し、
次いでそのゲート酸化膜上にCVD法によりゲート電極
膜の形成を行う前か後に、ゲート酸化膜にフッ素イオン
を注入することを特徴とする半導体装置の製造方法。
1. Form a gate oxide film by oxidizing the semiconductor substrate at low temperature,
A method for manufacturing a semiconductor device, which comprises implanting fluorine ions into the gate oxide film before or after forming a gate electrode film on the gate oxide film by CVD.
JP7995890A 1990-03-28 1990-03-28 Manufacture of semiconductor device Pending JPH03280471A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7995890A JPH03280471A (en) 1990-03-28 1990-03-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7995890A JPH03280471A (en) 1990-03-28 1990-03-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03280471A true JPH03280471A (en) 1991-12-11

Family

ID=13704818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7995890A Pending JPH03280471A (en) 1990-03-28 1990-03-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03280471A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04157765A (en) * 1990-10-20 1992-05-29 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type field effect transistor and manufacture thereof
KR100514581B1 (en) * 1998-08-19 2005-11-24 도 영 김 A method for manufacturing insulator for TFT
KR100622812B1 (en) * 2004-12-29 2006-09-18 동부일렉트로닉스 주식회사 Method for fabricating the gate structure of semiconductor device
JP2007335784A (en) * 2006-06-19 2007-12-27 Renesas Technology Corp Semiconductor device and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04157765A (en) * 1990-10-20 1992-05-29 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type field effect transistor and manufacture thereof
KR100514581B1 (en) * 1998-08-19 2005-11-24 도 영 김 A method for manufacturing insulator for TFT
KR100622812B1 (en) * 2004-12-29 2006-09-18 동부일렉트로닉스 주식회사 Method for fabricating the gate structure of semiconductor device
JP2007335784A (en) * 2006-06-19 2007-12-27 Renesas Technology Corp Semiconductor device and manufacturing method thereof

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