JP4076725B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of a high voltage MOS transistor having a process of forming two layers of polycrystalline silicon and a method of manufacturing a semiconductor device structure using the high voltage MOS transistor.
[0002]
[Prior art]
Conventionally, the following steps have been used to form a capacitive element and a heterogeneous MOS transistor together with a DDD (Double-Difused-Drain) type MOS transistor using two layers of polycrystalline silicon on a semiconductor substrate.
First, as shown in FIG. 3A, an element isolation film 24 and an oxide film 25 are formed on a silicon substrate 23 by a known technique.
[0003]
Next, as shown in FIG. 3B, after the first polycrystalline silicon is formed by a known technique, the lower electrode 26 of the capacitive element is formed by patterning and etching. Next, as shown in FIG. 3C, an insulating oxide film 27 (a) and a gate oxide film 27 (b) of the capacitive element are formed on the lower electrode 26 by thermal oxidation.
Next, as shown in FIG. 3D, after the second polycrystalline silicon is formed by a known technique, the upper electrode 28 (a) of the capacitive element and the gate electrode 28 (b) of the transistor are formed by patterning and etching away. Form.
Next, as shown in FIG. 3E, a resist material 29 is patterned by a known technique, and an impurity layer 30 (a) that becomes a DDD is selectively formed by a known technique in a transistor region to be formed into a DDD structure. To do.
[0004]
Next, as shown in FIG. 3F, a DDD diffusion layer 30 (b) is formed by a thermal diffusion process in order to obtain a diffusion width in which the impurity layer 30 (a) functions as DDD.
Next, as shown in FIG. 3G, a source / drain layer 31 is formed in the transistor region by a known technique, and a DDD transistor and a capacitor or another type of transistor are formed.
[0005]
[Problems to be solved by the invention]
In the conventional manufacturing method, the gate electrodes of the DDD transistor and other types of transistors are formed from the same polycrystalline silicon, and thus there are problems described below.
1. Since a thermal diffusion process for sufficiently diffusing the DDD diffusion layer is necessary, there are many manufacturing processes.
2. Since the thermal diffusion process is a relatively high temperature process, the quality of the insulating oxide film, the gate oxide film, and the like formed before the thermal diffusion process is deteriorated.
3. It is difficult to change the gate oxide film thickness of the DDD transistor and other types of transistors, and more steps are required to do so.
It is an object of the present invention to improve the conventional structure and manufacturing method and eliminate the above-mentioned problems.
[0006]
[Means for Solving the Problems]
In the structure and the manufacturing method of the present invention, after the gate of the DDD transistor and the lower electrode of the capacitor element are formed from the first polycrystalline silicon, the DDD impurity layer is formed, the insulating oxide film formation of the capacitor element and the second Since the DDD transistor is formed by using both the thermal oxidation process for forming the gate oxide film of the transistor having polycrystalline silicon as the gate electrode and the DDD impurity layer diffusion process, it has the following operations.
1. The manufacturing process is reduced.
2. Since the number of heat treatment steps is reduced, the quality of the insulating oxide film and the gate oxide film is improved.
3. Since the gate oxidation of the DDD transistor and other types of transistors can be performed separately, it is easy to change the thickness of each gate oxide.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment of the present invention will be described below.
First, as shown in FIG. 1A, an element isolation film 2, a first gate oxide film 3, a lower electrode 4 (a) of a capacitor element by a first polycrystalline silicon, The gate electrode 4 (b) of one transistor is formed by a known technique.
Next, as shown in FIG. 1B, the resist material 5 is patterned by a known technique, and an impurity layer 6 (a) to be DDD is selectively formed in the first transistor region by, for example, ion implantation. .
[0008]
Next, as shown in FIG. 1C, if necessary, after removing the first gate oxide film on the second transistor region, the insulating oxide film 7 (a) of the capacitor element and the first oxide film are thermally oxidized. A second gate oxide film 7 (b) of the second transistor is formed.
The impurity layer 6 (a) previously formed by the thermal oxidation process at this time is diffused to form the DDD diffusion layer 6 (b).
Next, as shown in FIG. 1D, the upper electrode 8 (a) of the capacitor and the gate electrode 8 (b) of the second transistor are formed by a known technique using the second polycrystalline silicon.
[0009]
Next, as shown in FIG. 1E, the source and drain diffusion layers 9 are formed in the first and second transistor regions by a known technique, and a DDD transistor and a capacitor element or another type of transistor are formed. To do.
Since the DDD transistor formed as described above uses the first polycrystalline silicon as the gate electrode, the gate oxidation of the second transistor using the second polycrystalline silicon as the gate electrode and the formation of the insulating film of the capacitor element This oxidation process can also be used as a heat treatment process for DDD diffusion, thereby reducing the DDD thermal diffusion process.
Here, the first embodiment has the same operation and effect not only when forming a DDD transistor, another type of transistor, and a capacitive element using two layers of polycrystalline silicon, but also when described below. It goes without saying that it is obtained.
1. When a DDD transistor and other types of transistors are formed using two layers of polycrystalline silicon.
2. When a DDD transistor and a capacitor element are formed using two layers of polycrystalline silicon.
[0010]
A second embodiment in which the first embodiment of the present invention is applied to an EEPROM will be described below.
The EEPROM has a peripheral circuit section that only needs to operate satisfactorily in a power supply voltage range of, for example, 10 V or less, an EEPROM cell array section, and a voltage necessary for writing to the EEPROM cell, usually under a voltage of, for example, 14 V to 30 V higher than the power supply voltage range. It has a high-voltage drive circuit part that operates sufficiently.
[0011]
Therefore, an EEPROM cell to which a high voltage is applied for writing and a high voltage transistor are required in the high voltage drive circuit section.
In order to achieve a high breakdown voltage, it is desirable that the source and drain portions of the transistor have a DDD structure and that the gate oxide film thickness of the transistor be relatively thick.
[0012]
On the other hand, in the peripheral circuit portion, a high voltage transistor is not particularly required, and considering the driving capability and leakage, the performance of the EEPROM increases when the gate oxide film thickness of the peripheral circuit transistor is made as thin as possible.
That is, it is desirable to change the source and drain structures and the gate oxide film thickness between the high voltage transistor and the peripheral circuit transistor.
[0013]
In addition, the EEPROM cell has a tunnel oxide film region as a carrier moving port for writing, and its oxide film thickness is considerably smaller than the gate oxide film thickness of a normal transistor. Therefore, the film quality deteriorates as the heat treatment after formation increases. Insulation withstand voltage drops due to an increase in traps and interface order. Therefore, it is desirable that the number of heat treatment steps be as small as possible.
[0014]
First, as shown in FIG. 2A, a well region 11, an element isolation film 12, a tunnel drain diffusion layer 13, a first gate oxide film 14, a tunnel oxide film region 15 on a silicon substrate 10; The gate electrode 16 (a) of the first polycrystalline silicon floating gate transistor, the gate electrode 16 (b) of the first polycrystalline silicon select gate transistor, the gate electrode 16 (c) of the high breakdown voltage transistor, etc. The resist layer 17 is formed by a known technique and patterned, and an impurity layer 18 (which becomes a DDD by an ion implantation method or the like is selectively formed in an area where a high breakdown voltage is required, such as an EEPROM cell array region or a high voltage driving circuit portion. a) is formed.
[0015]
Here, it goes without saying that the impurity layer 18 (a) to be the DDD may be formed at least on the drain side of the select gate transistor of the EEPROM cell in consideration of the write application voltage condition of the EEPROM cell. At this time, for example, the silicon substrate 10 is P-type, the well region 11 is N-type, the tunnel drain 13 is N-type, and the thickness of the first gate oxide film 14 is in the range of 300 to 1200 mm. The film 15 is formed in the range of 50 to 150 mm.
[0016]
The first polycrystalline silicon is used not only as a floating gate electrode but also as a select gate electrode and a gate electrode and wiring of a high breakdown voltage transistor, so that the film thickness is 2500 to 6000 mm, and the sheet resistance is 10 to 500Ω. It is good to form with / sq.
The impurity layer 18 (a) is preferably formed by implanting phosphorus at 1E13 to 8E14 atms / cm @ 2 in the case of ion implantation.
[0017]
Next, as shown in FIG. 2 (b), if necessary, the first gate oxide film on the peripheral circuit transistor region using the second polycrystalline silicon as the gate electrode is removed and then formed by thermal oxidation. An insulating oxide film 19 (a) for capacitively coupling the control gate electrode and the floating gate electrode 16 (a), and a second gate used for a peripheral circuit transistor using the second polycrystalline silicon as a gate electrode An oxide film 19 (b) is formed.
[0018]
At the same time, the impurity layer 18 (a) previously formed is diffused by the thermal oxidation process to form the DDD diffusion layer 18 (b).
As described above, it is desirable that the thickness of the gate oxide film 19 (a) of the peripheral circuit transistor is as thin as possible, and the insulating oxide film 19 (b) for capacitively coupling the floating gate electrode and the control gate electrode is used. Since a high voltage is applied when writing to the EEPROM, a high quality oxide film formed by thermal oxidation at a relatively high temperature is desirable.
[0019]
Therefore, in the embodiment of the present invention, after the first gate oxide film 14 on the peripheral circuit transistor is removed, the insulating oxide film 19 (a) of the capacitive element and the second gate oxide film 19 (b). The thermal oxidation to form the above is performed in a dry oxygen atmosphere at 1000 to 1100 ° C., for example, only oxygen or a mixed atmosphere of oxygen and nitrogen, and the thickness of the gate oxide film 19 (a) of the peripheral transistor is The gate oxide film thickness of the high breakdown voltage transistor is preferably smaller, for example, in the range of 150 to 400 mm.
[0020]
Under the above-described thermal oxidation conditions, a diffusion width can be obtained in which the impurity layer 18 (a) functions sufficiently as a DDD.
Next, as shown in FIG. 2 (c), the control gate electrode 20 (a) of the EEPROM cell and the gate electrode 19 (b) of the peripheral circuit transistor are formed from the second polycrystalline silicon by a known technique.
[0021]
At this time, since the second polycrystalline silicon is also used as a control gate electrode, a gate electrode of a peripheral circuit transistor, and a wiring, the film thickness is 2500 to 6000 mm and the sheet resistance value is 10 to 500 Ω / sq. good.
Next, as shown in FIG. 2D, a first conductivity type, for example, P-type source / drain diffusion layer 21, and a second conductivity type, for example, N-type arsenic source / drain diffusion layer 22, are known. An EEPROM cell formed by technology and using a DDD transistor as a select gate and various circuits are formed.
[0022]
At this time, when a C-MOS circuit having a DDD structure is formed in the high breakdown voltage drive circuit portion in the structure of FIG. 2, the second gate oxide film 19 (a) shown in FIG. Before forming the insulating film 19 (b), a transistor region having a gate electrode of a first polycrystalline silicon layer having an impurity layer having a conductivity type opposite to that of the impurity layer 18 (a) is formed in the well region, It goes without saying that the DDD diffusion layer may be formed by thermal oxidation for forming the oxide film 19 (a) and the oxide film 19 (b).
[0023]
Conventionally, only the floating gate electrode is formed of the first polycrystalline silicon, and the peripheral circuit transistor, the DDD transistor, and the control gate electrode are formed of the second polycrystalline silicon. In order to change the oxide film thickness of the high voltage transistor and the peripheral circuit transistor if necessary, each gate oxidation step is required.
[0024]
However, in the EEPROM formed as described above, since the DDD transistor uses the first polycrystalline silicon as the gate electrode and the second polycrystalline silicon as the gate electrode of the peripheral circuit transistor, the second polycrystalline silicon is used as the gate. The gate oxidation process of the peripheral circuit transistor used as an electrode and the thermal oxidation process of forming an insulating film between the floating gate electrode and the control gate electrode can be performed in one thermal oxidation process, and can also be used as a thermal process for DDD diffusion. Therefore, the two steps of the peripheral transistor gate oxidation step and the DDD thermal diffusion step can be reduced.
[0025]
【The invention's effect】
In the present invention, as described above, since the DDD transistor uses the first polycrystalline silicon as the gate electrode, the gate oxidation of the second transistor using the second polycrystalline silicon as the gate electrode or the insulating oxidation of the capacitor element. The thermal oxidation process for film formation and the heat treatment for DDD diffusion can be combined, and the manufacturing cost can be reduced by reducing the number of processes.
[0026]
In particular, in the EEPROM, the DDD transistor uses the first polycrystalline silicon as the gate electrode and the second polycrystalline silicon as the gate electrode of the peripheral circuit transistor, so that the peripheral circuit transistor using the second polycrystalline silicon as the gate electrode is used. Since the gate oxidation process and the thermal oxidation process for forming an insulating oxide film between the floating gate electrode and the control gate electrode can be performed in one thermal oxidation process and can also be used as a heat treatment process for DDD diffusion, the gate of the peripheral transistor Since the oxidation process and the DDD thermal diffusion process are reduced by two processes, transistors having different gate oxide film thicknesses can be easily formed in the high voltage drive circuit part and the peripheral circuit part.
[0027]
Therefore, the manufacturing cost can be reduced by reducing the number of processes, the performance of the EEPROM can be improved, and the number of traps in the tunnel oxide film and the increase in the interface level can be suppressed by reducing the two thermal oxidation processes, improving the quality of the oxide film. In addition, the rewrite life of the EEPROM cell is increased, and the reliability is improved.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a first embodiment of the present invention.
FIG. 2 is an explanatory diagram of a second embodiment of the present invention.
FIG. 3 is an explanatory diagram of a conventional technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 10 Silicon substrate 23 Silicon substrate 11 Well area | region 2, 12, 24 Element isolation film 3, 7 (b), 14, 19 (b), 27 (b) Gate oxide film 25 Oxide film 4 (a) Capacitance element Lower electrode 26 Lower electrode 4 (b), 8 (b), 16 (c), 20 (b), 28 (b), gate electrode 16 (a) floating gate electrode 16 (b) select gate electrode 5, 17, 29 Resist material 6 (a), 18 (a), 30 (a) Impurity layer 6 (b), 18 (b), 30 (b) DDD diffusion layer 7 (a) Insulating oxide film of capacitor element 19 (a), 27 (a) Capacitor element insulating oxide films 8 (a), 28 (a) Capacitor element upper electrode 20 (a) Control gate electrodes 9, 21, 22, 31 Source, drain diffusion layers

Claims (5)

A high breakdown voltage transistor having a DDD structure having a breakdown voltage of 14 V or more , formed on a silicon substrate having at least two polycrystalline silicon layers and having the first polycrystalline silicon layer as a gate electrode ; A transistor having a second polycrystalline silicon layer provided on the same silicon substrate as a gate electrode, and a capacitor element having the first polycrystalline silicon layer and the second polycrystalline silicon layer as electrodes are formed. the method of manufacturing a semiconductor device, said first polysilicon layer is formed, forming after then patterned etched away, forming an impurity layer serving as a DDD diffusion layer, said second polycrystalline silicon layer A gate oxide film of the transistor having the second polycrystalline silicon layer as a gate electrode, and the first and second polycrystalline silicon layers; And a step of diffusing the impurity layer simultaneously with a thermal oxidation process for forming an insulating oxide film of the capacitive element using the capacitor as an electrode .   2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity layer is formed by a phosphorus ion implantation method. The method according to claim 1, wherein the thermal oxidation treatment is at a temperature of 1000 ° C. or higher 1100 ° C. or less. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the thermal oxidation treatment is performed in a dry oxygen atmosphere. A high breakdown voltage transistor having a DDD structure having a breakdown voltage of 14 V or more, provided on a silicon substrate having at least two polycrystalline silicon layers and having the first polycrystalline silicon layer as a gate electrode; A transistor having a second polycrystalline silicon layer provided on the same silicon substrate as a gate electrode, and the first polycrystalline silicon layer and the second polycrystalline silicon layer as first and second gate electrodes, respectively. In the method of manufacturing a semiconductor device for forming the EEPROM element, the first polycrystalline silicon layer is formed, patterned, etched and removed, and then an impurity layer to be a DDD diffusion layer is formed; A gate oxide film of the transistor having the second polycrystalline silicon layer as a gate electrode, and The impurity layer is diffused simultaneously with a thermal oxidation process for forming an insulating oxide film for capacitive coupling of the EEPROM element using the first and second polycrystalline silicon layers as first and second gate electrodes, respectively. A method of manufacturing a semiconductor device.

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