JP3216705B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, SOI (Silicon On Insulato)
r) relates to an insulated gate field effect transistor formed on an element substrate having a structure.

[0002]

2. Description of the Related Art A MOSF using an SOI substrate having a thin-film single-crystal silicon layer (SOI layer) formed on an insulator is used.
Research is underway to form ET. It is known that the merit thereof is that the source / drain parasitic capacitance is greatly reduced as compared with the conventional bulk substrate.

A MOSFET using a thin film SOI substrate is:
When the thickness of the SOI layer is larger than the maximum depletion layer width of the channel region of the MOSFET, it is called a partially depleted MOSFET, and when the thickness of the SOI layer is smaller than the maximum depletion layer width of the channel region of the MOSFET. Is a fully depleted MOS
It is called FET.

A fully depleted MOSFET has an advantage that a parasitic bipolar effect is less likely to occur than a partially depleted MOSFET. In addition, fully depleted MOSFET
Since the depletion layer formed under the inversion layer at the time of transistor operation reaches the buried oxide film, the width of the depletion layer is apparently large, and the depletion layer capacitance Cd becomes very small.
Therefore, I _ds - sub-threshold coefficient S decreases in (drain source current) -V _g (gate voltage) characteristics, there is the advantage that the rising characteristics of the transistor can be improved.

However, fully depleted MOSFETs
In the above, an N-channel MOSFET using an N ⁺ polysilicon gate electrode has a threshold voltage of 0 to 0.1 V, but it is difficult to increase the threshold voltage while maintaining a fully depleted state. is there. This is because if the channel concentration is increased to increase the threshold voltage, the maximum depletion layer width of the channel region is reduced and does not reach the thickness of the SOI layer, resulting in a partially depleted type. Similarly,
P-channel type MO using P ⁺ polysilicon gate electrode
It is difficult to increase the threshold voltage even with an SFET.

On the other hand, when a P ⁺ polysilicon gate electrode is used for an N-channel MOSFET in a fully depleted MOSFET, the threshold voltage is 0.7 to 1.0.
V. This is because the P ⁺ polysilicon gate electrode and N ⁺
This is due to the difference in work function difference between the polysilicon gate electrode and the P-type channel region. The difference in the work function from the channel region depends on the impurity concentration in the channel region, but generally has a difference of 0.7 to 0.9 V. However, when used at a power supply voltage of 3 V or less, the threshold voltage of 0.7 to 1.0 V is too high, so that sufficient on-current cannot be obtained. Similarly, when an N ⁺ polysilicon gate electrode is used for a P-channel MOSFET, the absolute value of the threshold voltage is 0.7 to 1.0 V, which is too high.

As a conventional example for solving such a problem, Japanese Patent Application Laid-Open No. 8-18015 has been proposed. This conventional example will be described with reference to FIG. In FIG. 6, a buried insulator layer 11 is formed on a silicon substrate 10, and SOI layers 12 and 13 are separately formed on the buried insulator layer 11.

In order to form an N-channel MOSFET 20 ′, a P-type channel region 14 is formed in the SOI layer 12, and an N ⁺ polysilicon gate is formed on the P-type channel region 14 via a gate oxide film 15. An electrode 16 is formed. N ⁺ source / drain regions 17 are formed on both sides of the P-type channel region 14 of the SOI layer 12. N ⁺ source / drain region 17 is formed in via hole 1
8 is connected to a metal wiring 19.

On the other hand, in order to form a P-channel MOSFET 30 ', an N-type channel region 2 is formed in the SOI layer 13.
1 is formed, and an N ⁺ polysilicon gate electrode 23 is formed on the N-type channel region 21 via a gate oxide film 22.
Are formed. On both sides of the N-type channel region 21,
A P ⁺ source / drain region 27 is formed, and the P ⁺ source / drain region 27 is connected to a metal wiring 25 via a via hole 24.

A high-concentration impurity diffusion region 31 of the same conductivity type as the silicon substrate 10 is formed on the surface of the silicon substrate 10 as an electrode common to both MOSFETs, and an ohmic contact is made. Since the metal wiring 33 is connected to the high-concentration impurity diffusion region 31 via the via hole 32, a negative substrate bias supplied from a separately prepared bias generation circuit is supplied through the high-concentration impurity diffusion region 31. Is applied to the silicon substrate 10.

FIG. 7 is a circuit diagram of FIG.

FIG. 8 shows an N-channel MOSFET 20 '.
The threshold voltage of the P-channel MOSFET is V _TN
In a case where the threshold voltage of the 30 'and the V _TP, showing the substrate bias dependence applied to the silicon substrate 10.

The N-channel MOSFET 20 'uses the N ⁺ polysilicon gate electrode 16 on the P-type channel region 14 via the gate oxide film 15, so that when the substrate bias is 0V, the threshold voltage V _TN Has a value of 0.1V. On the other hand, the P-channel MOSFET 30 ′ uses the N ⁺ polysilicon gate electrode 23 on the N-type channel region 21 via the gate oxide film 22, so that when the substrate bias is 0 V, the threshold voltage V _TP becomes It has a value of -0.8V. This is because the concentration of the P-type channel region 14 is 1 × 1
0 ¹⁷ cm ⁻³ , the concentration of the N-type channel region 21 is 1 × 10 ¹⁷
cm ^-3 , the thickness of the SOI layers 12 and 13 is 60 nm, and the thickness of the buried insulator layer 11 is 110 nm. When a substrate bias is applied in minus, the N-channel type MO
The threshold voltage V _{TN of the} SFET 20 ′ increases, and the absolute value of the threshold voltage V _TP of the P-channel MOSFET 30 ′ decreases. As a result, if an appropriate negative voltage, for example, −3 V is applied to the silicon substrate 10, V _TN becomes 0.4 V, V
_TP becomes -0.5 V, and a threshold voltage suitable for operation at a power supply voltage of 3 V or less can be obtained.

[0014]

In the case of the above conventional example,
A new substrate bias generation circuit for applying a negative bias to the semiconductor substrate is required. Since the substrate bias generation circuit is formed on the same semiconductor substrate, an increase in cost becomes a problem.

An object of the present invention is to provide an insulated gate field effect transistor formed on an SOI structure element substrate without newly installing a substrate bias generation circuit for applying a negative bias to a semiconductor substrate. An object of the present invention is to provide a semiconductor device capable of setting a threshold voltage to an appropriate value.

[0016]

According to the present invention, an N-channel MOSFET and a P-channel MOSFET are provided on a plurality of single crystal semiconductor layers formed on a semiconductor substrate via an insulator layer.
In a semiconductor device having an FET formed thereon, an electrode common to both MOSFETs is disposed on the semiconductor substrate facing the N-channel MOSFET region and the P-channel MOSFET region, and a bias voltage having a positive polarity is applied to the electrode. A gate electrode of the N-channel MOSFET;
The gate electrodes of the P-channel MOSFET are respectively
A semiconductor device characterized by comprising P ⁺ polysilicon is provided.

[0017]

Preferably, the bias voltage having a positive polarity is a power supply voltage.

Further, the electrode common to both MOSFETs is
The N-channel MOSFET region and the P-channel MO
The semiconductor substrate is disposed on the semiconductor substrate facing the region between the SFET region.

According to the present invention, the two MOSFETs
A common electrode, a P ⁺ -type high concentration impurity diffusion region, the N-channel MOSFET region and the P-channel MO
An N-type substrate well region is formed in a region of the P-type semiconductor substrate opposite to the N-channel MOSFET region and the P-channel MOSFET region. And a semiconductor device configured to apply the power supply voltage via the diode.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment of the present invention.
In FIG. 1, the same parts as those in FIG. 6 are denoted by the same reference numerals. A buried insulator layer 11 is formed on a silicon substrate 10, and SOI layers 12 and 13 are formed on the buried insulator layer 11.
Are formed.

In order to form an N-channel type MOSFET 20, a P-type channel region 14 is formed in the SOI layer 12. In this embodiment, P ⁺ is formed on the P-type channel region 14 via a gate oxide film 15. A polysilicon gate electrode 6 is formed. N ⁺ source / drain regions 17 are formed on both sides of the P-type channel region 14 of the SOI layer 12, and the N ⁺ source / drain regions 17
8 is connected to a metal wiring 19.

On the other hand, in order to form a P-channel MOSFET 30, an N-type channel region 21 is formed in the SOI layer 13.
Is formed, but a P ⁺ polysilicon gate electrode 3 is formed on the N-type channel region 21 via a gate oxide film 22. On both sides of the N-type channel region 21, P ⁺
A source / drain region 27 is formed, and P ⁺ source / drain region 27 is connected to metal wiring 2 through via hole 24.
5 is connected.

A high-concentration impurity diffusion region 31 of the same conductivity type as the silicon substrate 10 is formed on the surface of the silicon substrate 10 as an electrode common to both MOSFETs, and an ohmic contact is established. A metal wiring 33 is connected to the high-concentration impurity diffusion region 31 via a via hole 32. In this embodiment, a positive substrate bias supplied from a power supply V _dd (also representing a voltage) is applied to the silicon substrate 10 through the high-concentration impurity diffusion region 13.

FIG. 2 is a circuit diagram of the present invention.

FIG. 3 shows an N-channel MOSFET 20.
Has a threshold voltage of V _TN and a P-channel MOSFET 3
0 when the threshold voltage is V _TP of, shows a substrate bias dependence applied to the silicon substrate 10.

Since the N-channel MOSFET 20 uses the P ⁺ polysilicon gate electrode 6 on the P-type channel region 14 via the gate oxide film 15, when the substrate bias is 0 V, the threshold voltage V _TN is It has a value of 0.8V. On the other hand, the P-channel MOSFET 30 uses the P ⁺ polysilicon gate electrode 3 on the N-type channel region 21 via the gate oxide film 22, so that when the substrate bias is 0 V, the threshold voltage V _TP becomes It has a value of -0.1V. This is because the concentration of the P-type channel region 14 is 1 × 10 ¹⁷
cm ⁻³ , the concentration of the N-type channel region 21 is 1 × 10 ¹⁷ cm
^-3 , the SOI layers 12 and 13 have a thickness of 60 nm, and the buried insulator layer 11 has a thickness of 110 nm.

When a positive substrate bias is applied, N
The threshold voltage V _TN of the channel MOSFET 20 decreases, and the threshold voltage V _TP of the P-channel MOSFET 30 decreases.
The absolute value of increases. As a result, when a power supply voltage, for example, 3 V is applied to the silicon substrate 10, the threshold voltage V _TN becomes 0.5 V, the threshold voltage V _TP becomes −0.4 V, and the power supply voltage V _dd (= 3 V), Alternatively, a threshold voltage suitable for operation at a lower voltage or lower can be obtained.

Next, a second embodiment of the present invention will be described with reference to FIG. The difference between the second embodiment and the first embodiment shown in FIG.
0, that is, an N-type substrate well region 40 in the silicon substrate 10 region facing the region where the N-channel type MOSFET 20 and the P-channel type MOSFET 30 are formed, and P ⁺ adjacent to the N-type substrate well region 40.
Type high concentration impurity diffusion region 41 is formed, and P ⁺ /
It has an N diode. A power supply voltage having a positive polarity is applied via the P ⁺ / N diode.

FIG. 5 is a circuit diagram composed of MOSFETs formed on the N-type substrate well region 40 in FIG. A P ⁺ / N diode D is provided in the N-type substrate well region 40.
Of the power supply voltage V _F (about 0.8 V)
potential of _dd -V _F) is applied. As a result, the power supply voltage V _dd 3V is applied to the MOSFET on the N-type substrate well region 40.
In this case, a substrate bias of 2.2 V is applied. FIG.
(A) shows that the N-channel MOSFET 20 at this time is
The threshold voltage V _TN 0.58V, P-channel type MOS
The threshold voltage V _TP of FET30 will be -0.32V.

As described above, only the MOSFET formed on the N-type substrate well region 40 can selectively control the threshold voltage. In such a semiconductor device, for example, in a 6-transistor cell of an SRAM, a higher threshold voltage of an N-channel MOSFET improves data retention characteristics. Provided by law.

[0032]

As described above, both the N-channel MOSFET and the P-channel MOSFET use the P ⁺ polysilicon gate electrode and further apply a positive power supply voltage to the silicon substrate to thereby provide an N-channel MOSFET.
The threshold voltages of the ET and P-channel MOSFETs can be set to appropriate values. Further, there is no need for a substrate bias generating circuit for applying a negative substrate bias to the substrate as in the conventional example.

Further, by forming a substrate well region on a silicon substrate below a specific MOSFET and applying a power supply voltage via a diode, a threshold voltage suitable for a circuit configuration to be used can be set.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram according to the first embodiment of the present invention.

FIG. 3 is a MOSFE for explaining the operation principle of the present invention;
FIG. 4 is a characteristic diagram showing the substrate bias dependence of T.

FIG. 4 is a longitudinal sectional view showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram according to a second embodiment of the present invention.

FIG. 6 is a longitudinal sectional view of a conventional example.

FIG. 7 is a circuit diagram of the conventional example of FIG.

FIG. 8 is a MOSFE for explaining the operation principle of the conventional example.
FIG. 4 is a characteristic diagram showing the substrate bias dependence of T.

[Explanation of symbols]

3, 6 P ⁺ polysilicon gate electrode 11 buried insulator layer 12, 13 SOI layer 15, 22 gate oxide film 17 N ⁺ source / drain region 20 N-channel type MOSFET 21 N-type channel region 27 P ⁺ source / drain region 30 P channel type MOSFET 31 High concentration impurity diffusion region 40 N type substrate well region 41 P ⁺ type high concentration impurity diffusion region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 27/08 331

Claims (4)

(57) [Claims] An N-channel MOSFET is formed on a plurality of single crystal semiconductor layers formed on a semiconductor substrate via an insulator layer.
A N-channel MOSFET region and a P-channel MOSFET.
Both MOSFETs are provided on the semiconductor substrate facing the FET region.
An electrode common to T is disposed, a bias voltage having a positive polarity is applied to the electrode, and the gate electrode of the N-channel MOSFET and the P-channel
Each gate electrode of Yaneru MOSFET, P ⁺ poly
A semiconductor device comprising silicon . 2. A semiconductor device according to claim 1, before
A semiconductor device, wherein the bias voltage having the positive polarity is a power supply voltage . 3. A semiconductor device according to claim 1, before
The electrode common to both MOSFETs is the N-channel MOS.
Between the FET region and the P-channel MOSFET region
A semiconductor device which is arranged on the semiconductor substrate facing a region . The semiconductor device 4. The method of claim 1, wherein, prior to
The electrode common to both MOSFETs is expanded with P ⁺ type high concentration impurity.
The N-channel MOSFET region and the front region
Facing the region outside the P-channel MOSFET region.
Placed on the semiconductor substrate, and the N-channel MOSFET
P facing the T region and the region of the P-channel MOSFET
Forming an N-type substrate well region in the region of the semiconductor substrate
And a power supply voltage via the diode.
A semiconductor device characterized by applying a voltage .