JPH02129960A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve device characteristics and assure high integration by providing a low concentration impurity area of a second conductive type on a channel side of a high concentration impurity area of a first conductive type in source and drain regions of a load MOS transistor. CONSTITUTION:When gate voltage is grounded potential, the conductivity type of a channel formation area 1a is a p-type impurity area and hence the device takes an n<+>p<->n<+> structure. Therefore, drain voltage is all applied on a pn junction located in the vicinity of the drain to cause tunnel leakage and hence produce a current. Further, when the gate voltage is power supply voltage, an inversion layer is formed on the tunnel formation area 19 and hence the device takes an n<+>p<->np<->n<+> structure. Thus, two reversely-biased pn junctions are formed. Therefore, an electric field exerted on the one pn junction is halved. Hereby, device characteristics are improved and high integration is assured.

Description

Detailed Description of the Invention [Industrial Field of Application] [Summary of the Invention] The present invention provides a semiconductor memory in which a flip-flop circuit of a memory cell is composed of a load MOS transistor and a drive transistor. It is formed using a semiconductor layer containing impurities, and its source and
The drain region has a structure in which a low concentration impurity region of the second conductivity type is formed near the gate of the high concentration impurity region of the first conductivity type, thereby enabling direct connection with a bulk MOS transistor or the like. This is to realize high integration.

[Conventional technology]

In general, two types of SRAM memory cell structures are known: one using a high resistance load and the other using a full CMO3 configuration. At present, devices using a high resistance load are becoming popular because integration can be achieved by forming a high resistance load above the transistor section.

However, as the degree of integration of SRAM increases, for example, the width of 0
．． It is necessary to form a polysilicon resistance layer having a size of about 5 μm and a length of about 3 μm. For this reason, integration becomes difficult with the extension of current technology, and instead of the type using a high resistance load, memory cells with a full CMO3 configuration are attracting attention.

Figure 3 shows a memory cell circuit with a full CMO3 configuration.
pMO3l-transistors 31 and 32 are load MOS transistors. nMO3l-Rangis.

3334 is a drive transistor. These transistors 31 to 34 constitute a flip-flop circuit. In addition, its input/output terminal has a gate connected to the word line WL.
Switching transistors 35 and 36 are provided and connected to bit lines bit and bit, respectively.

A structure shown in FIG. 4 is a structure that can be used to realize highly integrated memory cells of such a circuit.

In the structure of the memory cell shown in FIG. 4, a thin film PMOS transistor 41 is stacked on a bulk nMOS transistor 40, and their gate 42 is shared.

Since it is stacked, high integration is possible. The nMOS transistor 40 is a drive transistor, and its source
The drain regions 43.43 are n0 type high concentration impurity regions. The pMOS transistor 41 is a load transistor, and the source/drain region 44 of the thin film semiconductor layer 45
．． Reference numeral 44 denotes a p'' type high concentration impurity region.

[Problem to be solved by the invention]

However, when a memory cell structure having a full CMO3 configuration as described above is used, a problem with electrical connection arises.

That is, in FIG. 4, a P9 type high concentration impurity region which becomes the source/drain region 44 of the thin film PMOS transistor, and a source/drain region 4 of the drive transistor.
Since a junction occurs when the n-type high-concentration impurity region No. 3 is directly connected, it is necessary to connect it with a connection layer 46 such as an n4-type doped polysilicon layer or a metal layer. Therefore, forming such a connection layer 46 complicates the process, making it difficult to achieve high integration.Furthermore, if the connection layer 46 is a polysilicon layer,
Connection between polysilicon layers of opposite conductivity types is required,
The device characteristics are not favorable.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory which enables direct connection of a load MOS transistor to a drive transistor and achieves high integration.

[Means to solve the problem]

In order to achieve the above object, the semiconductor memory of the present invention has the following features:
A memory cell is constituted by a flip-flop circuit formed by a pair of load MOS transistors and a pair of drive transistors, and a pair of switching transistors, and the load MOS transistor is formed in a semiconductor layer containing impurities of a first conductivity type. A channel of the load MOS transistor is formed, and the source/drain region of the load MOS transistor is
It is characterized by comprising a conductivity type high concentration impurity region and a second conductivity type low concentration impurity region provided on the channel side of the high concentration impurity region.

Here, the semiconductor layer has a structure formed on an insulating substrate or in contact with an insulating layer, and a region that becomes a channel of a load MOS transistor has a second conductivity type when turned off by a gate voltage; 1st when turned on
It can be made into a conductive type.

[Effect]

By making the structure of the source/drain region of the load MOS transistor into a first conductivity type high concentration impurity region and a second conductivity type low concentration impurity region provided on the channel side of the high concentration impurity region, the high concentration impurity region can be reduced. The doped impurity region can be made to have the same conductivity type as the bulk drive transistor.

To explain this with reference to FIG. 1, for example, if the first conductivity type is n type and the second conductivity type is p type, the load MOS transistor 1 has a structure of the semiconductor layer 2 with n''p -n (or p-)p-n' type.The conductivity type of the channel 3 changes depending on the gate voltage applied to the gate electrode 4.First, when the gate voltage is the ground voltage GND (for example, OV) , the conductivity type of the channel is p-, and the drain voltage is P near the drain.
All of the current is applied to the N junction, and current flows due to tunnel leakage. Also, the gate electrode is at the power supply voltage ■. .

(for example, 5V), the conductivity type of the channel is n
Thus, two reverse bias states of the PN junction are formed, and the leakage current becomes sufficiently small. Therefore, its resistance value changes greatly depending on the value of the gate voltage, and it functions as a load. In this case, the load MOS transistor has 9 MOs depending on the gate voltage.
Although it functions similarly to an S transistor, the high concentration impurity region is of n' type. Therefore, for example, the bulk n
Direct connection is also possible to a drive transistor made of a MOS transistor.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

In this embodiment, the load MOS transistor is a thin film n″p-
It is formed on an n (or p-)p-n'' type semiconductor layer, and has a structure in which a load MOS transistor is stacked on a bulk MOS transistor that serves as a drive transistor. The circuit configuration has the circuit configuration shown in FIG.

The cross section of the main parts of the load MOS transistor and drive transistor has a structure shown in FIG. First, a gate insulator 1 is placed on the surface of a bulk p-type silicon substrate 11.
Gate electrode 13 is formed via 1112. The p-type silicon substrate 11 under the gate electrode 13 becomes the channel formation region 14 of the drive transistor IO, and n-type high concentration impurity regions 15 and 15 are formed opposite to each other with the channel formation region 14 in between. Ru.

On this drive transistor 10, the same gate electrode 14
A load MO3I-transistor 16 using .

This load MOS transistor 16 uses a semiconductor layer 18 containing impurities formed on the insulator N17, and this semiconductor layer 18 is, for example, a silicon layer. The region above the gate electrode 14 of this semiconductor layer 18 is connected to the MOS
This is a channel forming region 19 of the transistor 16, which becomes a P- type impurity region when the gate voltage is the ground voltage GND, and becomes an N-type impurity region when the gate voltage is the power supply voltage VDD. A p-type low concentration impurity region 20.degree. 20 of the second conductivity type is formed in the semiconductor layer 18 in the vicinity of the gate 1i pole across the channel forming region 9. The concentration of these p-type low concentration impurity regions 20 and 20 is, for example, about 1 to 2×10'Ca+-'. Also,
The width of these p-type low concentration impurity regions 20, 20 in the direction of current flow is approximately 0.3 to 0.4 μm. And those p-type low concentration impurity regions 20.2
High concentration impurity regions 21 and 22 of the n' type, which is the first conductivity type, are formed in the semiconductor layer 18 further outside of the semiconductor layer 18.

One of the n° type high concentration impurity regions 21 and 22 extends along the surface of the insulating layer 17, and serves as the source/drain region of the bulk MOS transistor. It is directly connected to impurity region 15 through connection portion 23 . Since the high concentration impurity region 22 and the high concentration impurity region 15 are of the same n° type, there is no problem of junction occurring.

Here, to briefly explain the operation of a semiconductor memory having such a memory cell structure, the above-mentioned [action]
As explained above, the current flowing through the load MO3I transistor 16 varies depending on the voltage applied to the gate electrode 14, so that it can fully function as an element constituting an SRAM memory cell. First, when the gate voltage is the ground voltage GND (for example, OV), the conductivity type of the channel forming region l6 becomes a p- type impurity region, and the element is n
'p-n' structure. Therefore, the drain voltage is applied entirely to the p-n junction near the drain, causing l-channel leakage and current flowing. Also, the gate voltage is set to the power supply voltage Vow (e.g. 5V), an inversion layer is formed in the channel forming region 16, and the device is n″p
-np-n+ structure, and two reverse-biased pn junctions are formed. Therefore, the electric field applied to each pn junction is halved. In general, tunnel leakage has an exponential dependence on electric field, so when the electric field is halved, tunnel leakage becomes sufficiently small. Therefore, the current between the source and the drain is dominated by the generated current, and when converted into resistance, for example, a resistance value of about 150 teraohms is obtained. In this way, the load M
In the OS transistor 16, a conductance on/off ratio of about 10 to 1000 times can be obtained depending on the voltage applied to the gate electrode 14.

As described above, the semiconductor memory of this embodiment is provided with the load MOS transistor 16 that fully functions as a load element, and the high concentration impurity region 22 in a part of the source/drain region is of n type. The connection of the bulk drive transistor IO6 can be made directly. Therefore, the manufacturing process can be simplified and device characteristics can be improved. It is also suitable for highly integrated elements.

Note that in the above embodiment, the load MOS transistor 16
Although the structure has been described in which the common gate electrode 14 is used for the drive transistors 10, the gate electrodes of each transistor may be separate.

〔Effect of the invention〕

In the semiconductor memory of the present invention, the source/drain regions of the load MOS transistors have a structure in which a low concentration impurity region of the second conductivity type is provided on the channel side of the high concentration impurity region of the first conductivity type. The high concentration impurity region can be made to have the same conductivity type as the drive transistor. Therefore, the source/drain regions of the load MO5 transistor can be directly connected to the source/drain regions of the drive transistor, and it is possible to simplify the process, improve device characteristics, and achieve high integration.

21.22...N-type high concentration impurity area patent applicant Akira Koike, patent attorney representing Sony Corporation (and 2 others)

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing an example of the structure of a load MOS transistor in a semiconductor memory of the present invention, FIG. 2 is a cross-sectional view of a main part of an example of a semiconductor memory of the present invention, and FIG. FIG. 4, which is a circuit diagram of a memory cell having a full CMO3 configuration, is a sectional view of a main part of an example of a conventional semiconductor memory. O...Drive transistor 6...Load MOS transistor 8...Semiconductor layer 9...Channel formation region O...P-type low concentration impurity 8I region 1 Fig. 2 Fig. 3 Fig. 4 figure

Claims (1)

[Claims] In a semiconductor memory in which a memory cell is constituted by a flip-flop circuit formed by a pair of load MOS transistors and a pair of drive transistors, and a pair of switching transistors, a channel of the load MOS transistor is formed in a semiconductor layer containing impurities, A semiconductor characterized in that the source/drain regions of the load MOS transistor are comprised of a first conductivity type high concentration impurity region and a second conductivity type low concentration impurity region provided on the channel side of the high concentration impurity region. memory.