JPH0232791B2 - - Google Patents
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- Publication number
- JPH0232791B2 JPH0232791B2 JP54168529A JP16852979A JPH0232791B2 JP H0232791 B2 JPH0232791 B2 JP H0232791B2 JP 54168529 A JP54168529 A JP 54168529A JP 16852979 A JP16852979 A JP 16852979A JP H0232791 B2 JPH0232791 B2 JP H0232791B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- type
- field effect
- effect transistor
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 12
- 230000005669 field effect Effects 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 230000010354 integration Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
この発明は、素子を立体的に集積して高集積化
を図つた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that achieves high integration by three-dimensionally integrating elements.
半導体集積回路の高集積化は半導体基板面上で
の素子の微細化を通じて行われてきた。例えば電
界効果トランジスタ（FET）では、チヤネル幅、
チヤネル長の縮少を微細加工技術により達成する
ことで高密度回路が実現されてきた。 High integration of semiconductor integrated circuits has been achieved through miniaturization of elements on the surface of a semiconductor substrate. For example, in a field effect transistor (FET), the channel width,
High-density circuits have been realized by reducing the channel length using microfabrication technology.
しかしながら、素子寸法は限りなく縮少できる
ものではなく、当然物理的限界により制限され
る。MOS型FETではチヤネル幅、チヤネル長共
に0.5μｍ程度が限界と考えられており、この限界
に近づくにつれて短チヤネル効果、狭チヤネル効
果等の特性上の不都合が生じてきている。それに
も拘らず、メモリ等においては更なる高密度化に
対する要求が依然として強い。 However, the element size cannot be reduced infinitely, and is naturally limited by physical limits. It is thought that the limit for both the channel width and channel length of MOS type FETs is about 0.5 μm, and as this limit is approached, disadvantages in characteristics such as short channel effects and narrow channel effects occur. Despite this, there is still a strong demand for higher density in memories and the like.
この発明は上記の点に鑑み、半導体基板上に立
体的に素子を堆積することでより一層の高集積化
を可能とした半導体装置を提供するものである。 In view of the above-mentioned points, the present invention provides a semiconductor device that enables higher integration by three-dimensionally depositing elements on a semiconductor substrate.
この発明においては、例えば通常のプロセスで
所望の素子が形成された半導体基板上に、絶縁膜
を介して設けた導体膜をゲート電極とし、この導
体膜上にこれと交差して設けた多結晶半導体膜に
ソース、ドレインおよびチヤネル領域を有する
FETを堆積することを基本とする。この場合、
堆積するFETは、ゲート電極となる導体膜を一
導電型の多結晶半導体膜とし、その上に交差する
多結晶半導体膜をこれと逆導電型としてその間に
pn接合を形成することで接合型FETとしてもよ
いし、また導体膜を金属膜または金属硅化物膜と
してその上に交差する多結晶半導体膜との間に金
属−半導体接合を形成したMES型FETとしても
よいし、更に半導体膜上に絶縁膜を介して多結晶
半導体膜を設けることでMOS型FETとしてもよ
い。またこれらの場合、半導体基板上に堆積する
FETのゲート電極となる導体膜を、半導体基板
内にソース、ドレインおよびチヤネル領域を有す
るMOS型あるいはMES型FETのゲート電極と兼
用させれば、一層の高集積化が可能となる。 In this invention, for example, a conductor film provided through an insulating film on a semiconductor substrate on which a desired element is formed by a normal process is used as a gate electrode, and a polycrystalline film is provided on the conductor film to intersect with the gate electrode. Semiconductor film has source, drain, and channel regions
The basic method is to deposit FETs. in this case,
The FET to be deposited uses a polycrystalline semiconductor film of one conductivity type as the conductive film that becomes the gate electrode, and a polycrystalline semiconductor film of the opposite conductivity type that intersects with this film, and a polycrystalline semiconductor film of the opposite conductivity type.
It can be used as a junction type FET by forming a pn junction, or it can be an MES type FET in which the conductor film is a metal film or metal silicide film and a metal-semiconductor junction is formed between it and a polycrystalline semiconductor film intersecting thereon. Alternatively, a MOS type FET may be formed by further providing a polycrystalline semiconductor film on the semiconductor film with an insulating film interposed therebetween. Also in these cases, deposited on the semiconductor substrate
If the conductive film serving as the gate electrode of the FET is also used as the gate electrode of a MOS or MES type FET that has a source, drain, and channel region within a semiconductor substrate, even higher integration becomes possible.
以下図面を参照してこの発明の実施例を説明す
る。第１図ａは一実施例の模式的平面パターンを
示し、同図ｂはそのＡ−A′断面を示している。
１はｐ型Si基板であつて、そのフイールド酸化膜
２で囲まれた領域にn+型のソース領域３、ドレ
イン領域４を設け、これら両領域間の基板表面に
例えば2000Åのシリコン酸化膜５を介してヒ素を
ドープしたｎ型多結晶シリコン膜６からなるゲー
ト電極を設けて通常のｎチヤネルMOS型FETが
形成されている。そのソース領域３、ドレイン領
域４上にはシリコン酸化膜７が設けられており、
この上に多結晶シリコン膜６に接触してこれに交
差するようにＰ型多結晶シリコン膜８を設けて
pn接合を形成し、その接合面上の部分をチヤネ
ル領域、その両側をソース、ドレイン領域とする
ｐチヤネル接合型FETが形成されている。更に
全体はシリコン酸化膜９でおおわれ、これにコン
タクトホールをあけて接合型FETのソース、ド
レイン電極となるAl膜１０1，１０2が配設されて
いる。Al膜１０2は別のコンタクトホールを介し
てMOS型FETのドレイン領域４にも接触させて
おり、またMOS型FETのソース電極として別の
Al膜１０3が設けられている。 Embodiments of the present invention will be described below with reference to the drawings. FIG. 1a shows a schematic planar pattern of one embodiment, and FIG. 1b shows a cross section taken along the line A-A'.
1 is a p-type Si substrate, in which an n + type source region 3 and a drain region 4 are provided in a region surrounded by a field oxide film 2, and a silicon oxide film 5 of, for example, 2000 Å is formed on the substrate surface between these regions. An ordinary n-channel MOS type FET is formed by providing a gate electrode made of an n-type polycrystalline silicon film 6 doped with arsenic through the gate electrode. A silicon oxide film 7 is provided on the source region 3 and drain region 4,
A P-type polycrystalline silicon film 8 is provided on this so as to contact and cross the polycrystalline silicon film 6.
A p-channel junction FET is formed in which a p-n junction is formed, and a portion on the junction surface is a channel region, and both sides thereof are source and drain regions. Further, the entire structure is covered with a silicon oxide film 9, and contact holes are formed in this to form Al films 10 1 and 10 2 which will become the source and drain electrodes of the junction FET. The Al film 102 is also in contact with the drain region 4 of the MOS FET through another contact hole, and is also used as the source electrode of the MOS FET.
An Al film 10 3 is provided.
このような構造は例えば次のようにして作られ
る。MOS型FETは通常のシリコンゲートプロセ
スで形成されるので説明を省略するが、多結晶シ
リコン膜６をマスクとしてソース領域３、ドレイ
ン領域４を形成した後、全面にシリコン窒化膜を
被着する。このシリコン窒化膜を多結晶シリコン
膜６の上にのみ残してエツチング除去し、酸化性
雰囲気中で熱酸化してソース領域３、ドレイン領
域４上にシリコン酸化膜７を形成する。その後、
シリコン窒化膜を除去してｐ型多結晶シリコン膜
８を堆積してパターニングし、その上にCVD法
によりシリコン酸化膜９を堆積し、コンタクトホ
ールをあけてAl膜１０1〜１０3を配設する。 For example, such a structure is created as follows. Since the MOS type FET is formed by a normal silicon gate process, the explanation will be omitted, but after forming the source region 3 and drain region 4 using the polycrystalline silicon film 6 as a mask, a silicon nitride film is deposited on the entire surface. This silicon nitride film is removed by etching leaving only on polycrystalline silicon film 6, and then thermally oxidized in an oxidizing atmosphere to form silicon oxide film 7 on source region 3 and drain region 4. after that,
The silicon nitride film is removed, a p-type polycrystalline silicon film 8 is deposited and patterned, a silicon oxide film 9 is deposited on top of it by CVD, and contact holes are made to form Al films 10 1 to 10 3 . do.
こうして通常のMOS型FET上にそのゲート電
極を共用して接合型FETを堆積した構造を等価
回路で示すと第２図のようになる。いま、MOS
型FET Q1のしきい値電圧を0.2Vとし、接合型
FET Q2はその基板となる多結晶シリコン膜８の
膜厚を、ゲート電極である多結晶シリコン膜６と
多結晶シリコン膜８との間の接触電位差により多
結晶シリコン膜８中に伸びる空乏層が表面に達す
るように選び、しきい値を−0.2Vとする。また
電源VBを例えば0.5Vとする。そうすると、共通
ゲート電極を入力端とし、Al膜１０2で共通接続
されたドレインを出力端として、例えば入力端が
0Vのときは、MOS型FET Q1のゲート、ソース
間電圧が0VであるのでFET Q1はオフし、接合
型FET Q2のゲートが0Vであるのに対しソース
がVB（＝0.5V）であるので、相対的にはゲートに
−0.5Vが印加されたのと等価になつてFET Q2が
オンする。この結果、出力端にはVB＝0.5Vが出
力される。一方、入力端が0.5Vのときは、MOS
型FET Q1のゲート、ソース間電圧が0.5Vとなる
のでFET Q1はオンし、接合型FET Q2のゲー
ト、ソース間電圧が0VであるのでFET Q2はオ
フする。これによつて、出力端は0Vとなる。つ
まり第２図の回路は相補型FETを組合せたイン
バータとなる。 An equivalent circuit diagram of a structure in which a junction FET is deposited on a normal MOS FET by sharing its gate electrode is shown in FIG. 2. Now, M.O.S.
The threshold voltage of type FET Q 1 is 0.2V, and the junction type
FET Q 2 has a depletion layer that extends into the polycrystalline silicon film 8 due to the contact potential difference between the polycrystalline silicon film 6 and the polycrystalline silicon film 8 that are the gate electrodes. is chosen so that it reaches the surface, and the threshold is set to −0.2V. Further, the power supply V B is assumed to be 0.5V, for example. In this case, the common gate electrode is used as the input end, and the drains connected in common through the Al film 102 are used as the output end.
When the voltage is 0V, the voltage between the gate and source of MOS type FET Q 1 is 0V, so FET Q 1 is turned off, and while the gate of junction type FET Q 2 is 0V, the source is VB (= 0.5V ), so it is relatively equivalent to applying -0.5V to the gate, and FET Q 2 turns on. As a result, V B =0.5V is output at the output terminal. On the other hand, when the input terminal is 0.5V, the MOS
The voltage between the gate and source of junction type FET Q 1 is 0.5V, so FET Q 1 is turned on, and the voltage between the gate and source of junction type FET Q 2 is 0V, so FET Q 2 is turned off. As a result, the output terminal becomes 0V. In other words, the circuit shown in FIG. 2 is an inverter that combines complementary FETs.
このインバータを組合せてフリツプフロツプを
構成すれば、第３図のようなメモリセルを構成す
ることができる。第３図でQ11，Q21がｎチヤネ
ルMOS型FET、Q12，Q22がｐチヤネル接合型
FETであり、（Q11，Q12）の対、（Q21，Q22）の
対がそれぞれ第１図の構造をもつものとする。フ
リツプフロツプの各ノードは例えばｎチヤネル
MOS型FET Q3，Q4を介してそれぞれデイジツ
ト線Ｄ，に接続され、MOS FET Q3，Q4のゲ
ートは共通にワード線Ｗに接続される。 If these inverters are combined to form a flip-flop, a memory cell as shown in FIG. 3 can be formed. In Figure 3, Q 11 and Q 21 are n-channel MOS FETs, and Q 12 and Q 22 are p-channel junction types.
It is assumed that the device is a FET, and the pair (Q 11 , Q 12 ) and the pair (Q 21 , Q 22 ) each have the structure shown in FIG. Each node of a flip-flop is, for example, an n-channel
The MOS FETs Q 3 and Q 4 are connected to the digit line D, respectively, and the gates of the MOS FETs Q 3 and Q 4 are commonly connected to the word line W.
この実施例によれば、第１図からわかるように
FETが立体的に集積されたことになり、第２図
に示すインバータ、更にこれを組合せた第３図に
示すメモリセル等を従来に比べて約２倍に高密度
化することができる。 According to this embodiment, as can be seen from FIG.
Since the FETs are integrated three-dimensionally, the inverter shown in FIG. 2 and the memory cell shown in FIG. 3 in which the inverter is combined can be made approximately twice as dense as in the past.
第４図は別の実施例の第１図ｂに対応する断面
図である。先の実施例と異なる点は、共通ゲート
電極となるｎ型多結晶シリコン膜６の部分にMo
膜６′を用いたことである。この場合、MOS型
FETに重ねられるのは接合型FETではなく、い
わゆるMES型FETである。Mo膜６′の代りに他
の金属膜あるいは金属硅化物膜を用いてもよい。
製造プロセス上は、特にMo、Ｗ、Pt等の高融点
金属またはその硅化物を用いるのが望ましい。 FIG. 4 is a sectional view corresponding to FIG. 1b of another embodiment. The difference from the previous embodiment is that Mo
This is because the membrane 6' was used. In this case, MOS type
What is superimposed on the FET is not a junction type FET, but a so-called MES type FET. Other metal films or metal silicide films may be used in place of the Mo film 6'.
In terms of the manufacturing process, it is particularly desirable to use high-melting point metals such as Mo, W, and Pt, or silicides thereof.
第５図は更に別の実施例の第１図ｂに対応する
断面図である。この実施例ではｎ型多結晶シリコ
ン膜６の上にシリコン酸化膜１１を介してｐ型多
結晶シリコン膜８を堆積しており、MOS型FET
にゲート電極を共通にしてMOS型FETを堆積し
た構造としている。この構造は、第１図の実施例
において多結晶シリコン膜８をつける前に熱酸化
を行うことで形成される。 FIG. 5 is a sectional view corresponding to FIG. 1b of yet another embodiment. In this embodiment, a p-type polycrystalline silicon film 8 is deposited on an n-type polycrystalline silicon film 6 via a silicon oxide film 11, and the MOS type FET is
It has a structure in which MOS FETs are deposited with a common gate electrode. This structure is formed by performing thermal oxidation before depositing the polycrystalline silicon film 8 in the embodiment shown in FIG.
これら第４図、第５図の実施例によつても先の
実施例と同様の効果が得られる。 The embodiments shown in FIGS. 4 and 5 also provide the same effects as the previous embodiments.
なお以上の実施例では、通常のｎチヤネル
MOS FETの上にゲート電極を共用して接合型、
MES型、MOS型のｐチヤネルFETを堆積した
が、この発明はその他種々変形実施できる。例え
ばチヤネルの導電型は任意に選択することができ
るし、また回路構成によつてはゲート電極を共用
せず、通常のMOS型FETのソースあるいはドレ
インの取出し電極配線をゲート電極として用いて
上記各実施例で説明したような接合型、MES型
あるいはMOS型FETを堆積する構造とすること
もできる。また上記実施例ではMOS型FETの直
上にFETを重ねているが、フイールド領域上に
重ねるようにしても勿論よいし、更に基板内に形
成する素子はバイポーラトランジスタであつても
よい。 In the above embodiment, a normal n-channel
Junction type with shared gate electrode on top of MOS FET,
Although MES type and MOS type p-channel FETs have been deposited, the present invention can be implemented in various other variations. For example, the conductivity type of the channel can be arbitrarily selected, and depending on the circuit configuration, the gate electrode may not be shared, and the source or drain lead electrode wiring of a normal MOS FET may be used as the gate electrode. It is also possible to have a structure in which junction type, MES type, or MOS type FETs are deposited as described in the embodiments. Further, in the above embodiment, the FET is stacked directly on top of the MOS type FET, but it is of course possible to stack the FET on the field region, and furthermore, the element formed in the substrate may be a bipolar transistor.
以上説明したようにこの発明によれば、通常の
プロセスで素子が形成された半導体基板上に更に
FETを堆積することによつて、各種半導体集積
回路の大幅な高集積化を実現することができる。 As explained above, according to the present invention, on a semiconductor substrate on which elements are formed by a normal process,
By depositing FETs, it is possible to significantly increase the integration density of various semiconductor integrated circuits.
第１図ａ，ｂはこの発明の一実施例の模式的平
面パターンとそのＡ−A′断面図、第２図はこの
実施例の等価回路図、第３図は同じくこの実施例
をメモリセルに適用した場合の等価回路図、第４
図、第５図はそれぞれ別の実施例の第１図ｂに対
応する断面図である。
１……ｐ型Si基板、２……フイールド酸化膜、
３……n+型ソース領域、４……n+型ドレイン領
域、５……シリコン酸化膜、６……ｎ型多結晶シ
リコン膜、７……シリコン酸化膜、８……ｐ型多
結晶シリコン膜、９……シリコン酸化膜、１０1
〜１０3……Al膜、６′……Mo膜、１１……シリ
コン酸化膜。
1A and 1B are schematic planar patterns and their A-A' sectional views of an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of this embodiment, and FIG. 3 is a memory cell diagram of this embodiment. Equivalent circuit diagram when applied to 4th
5 are sectional views corresponding to FIG. 1b of different embodiments, respectively. 1...p-type Si substrate, 2...field oxide film,
3...n + type source region, 4...n + type drain region, 5...silicon oxide film, 6...n type polycrystalline silicon film, 7...silicon oxide film, 8...p type polycrystalline silicon Film, 9...Silicon oxide film, 10 1
~10 3 ... Al film, 6' ... Mo film, 11 ... Silicon oxide film.
Claims (1)
縁膜を介して設けた導体膜をゲート電極とし、こ
の導体膜上にこれと交差して設けた多結晶半導体
をソース、ドレインおよびチヤネル領域とする電
界効果トランジスタを備え、前記ソース、ドレイ
ンおよびチヤネル領域は同一導電型であることを
特徴とする半導体装置。 ２ 電界効果トランジスタは、導体膜を一導電型
の多結晶半導体膜とし、この上に設ける多結晶半
導体膜をこれと逆導電型としてこれら多結晶半導
体膜間にpn接合を形成した接合型電界効果トラ
ンジスタである前記特許請求の範囲第１項記載の
半導体装置。 ３ 電界効果トランジスタは、導体膜を金属膜ま
たは金属硅化物膜としてこの上に設ける多結晶半
導体膜との間に金属−半導体接合を形成した
MES型電界効果トランジスタである前記特許請
求の範囲第１項記載の半導体装置。 ４ 電界効果トランジスタは、導体膜とその上に
設ける多結晶半導体膜との間に絶縁膜を有する
MOS型電界効果トランジスタである前記特許請
求の範囲第１項記載の半導体装置。 ５ 導体膜は、半導体基板内にソース、ドレイン
およびチヤネル領域を有するMOS型またはMES
型電界効果トランジスタのゲート電極を兼ねるも
のである前記特許請求の範囲第１項記載の半導体
装置。[Claims] 1. A conductive film provided on a semiconductor substrate on which a desired element is formed, with an insulating film interposed therebetween, is used as a gate electrode, and a polycrystalline semiconductor provided on this conductive film, intersecting with this, is used as a source. 1. A semiconductor device comprising a field effect transistor having a drain and a channel region, the source, the drain and the channel region being of the same conductivity type. 2. A field effect transistor is a junction field effect transistor in which the conductor film is a polycrystalline semiconductor film of one conductivity type, the polycrystalline semiconductor film provided thereon is of the opposite conductivity type, and a pn junction is formed between these polycrystalline semiconductor films. The semiconductor device according to claim 1, which is a transistor. 3. A field effect transistor has a metal-semiconductor junction formed between a conductor film made of a metal film or a metal silicide film and a polycrystalline semiconductor film provided thereon.
The semiconductor device according to claim 1, which is a MES field effect transistor. 4 A field effect transistor has an insulating film between a conductive film and a polycrystalline semiconductor film provided thereon.
The semiconductor device according to claim 1, which is a MOS field effect transistor. 5 The conductor film is a MOS type or MES type that has a source, drain, and channel region within the semiconductor substrate.
The semiconductor device according to claim 1, which also serves as a gate electrode of a type field effect transistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16852979A JPS5691470A (en) | 1979-12-25 | 1979-12-25 | Semiconductor |
| JP2055080A JPH02263475A (en) | 1979-12-25 | 1990-03-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16852979A JPS5691470A (en) | 1979-12-25 | 1979-12-25 | Semiconductor |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2055080A Division JPH02263475A (en) | 1979-12-25 | 1990-03-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5691470A JPS5691470A (en) | 1981-07-24 |
| JPH0232791B2 true JPH0232791B2 (en) | 1990-07-23 |
Family
ID=15869704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16852979A Granted JPS5691470A (en) | 1979-12-25 | 1979-12-25 | Semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5691470A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02263475A (en) * | 1979-12-25 | 1990-10-26 | Toshiba Corp | Semiconductor device |
| JPS5760868A (en) * | 1980-09-29 | 1982-04-13 | Seiko Epson Corp | Cmos memory cell |
| JPH0815157B2 (en) * | 1984-07-27 | 1996-02-14 | 株式会社日立製作所 | Method for manufacturing thin film transistor |
| JPS62131573A (en) * | 1985-12-04 | 1987-06-13 | Hitachi Ltd | Semiconductor device |
| JPH07120805B2 (en) * | 1987-10-12 | 1995-12-20 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JPH06101563B2 (en) * | 1988-07-19 | 1994-12-12 | 工業技術院長 | Thin film field effect transistor and manufacturing method thereof |
| JP2782333B2 (en) * | 1995-11-24 | 1998-07-30 | セイコーエプソン株式会社 | Method for manufacturing thin film transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5951146B2 (en) * | 1977-02-25 | 1984-12-12 | 沖電気工業株式会社 | Method for manufacturing insulated gate semiconductor integrated circuit |
| JPS5457969A (en) * | 1977-10-18 | 1979-05-10 | Sony Corp | Electric field effect transistor |
-
1979
- 1979-12-25 JP JP16852979A patent/JPS5691470A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5691470A (en) | 1981-07-24 |
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