JPS58116760A - Complementary mos semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a latchup phenomenon from occurring by forming a reverse conductive type well region on the surface layer of the partial region of a semiconductor substrate and Schottky contacting a drain with the surfaces of the substrate and well region respectively. CONSTITUTION:The surface of a silicon substrate 11 is oxidized as a field insulating film 13, a V-shaped groove is formed at the intermediate, and an insulating isolation region 14 is formed therein. Then, a dioxidized silicon film 15 is formed, a window is opened, ions are implanted, thereby sequentially forming an n type well 17, an n<+> type region 19 and a p<+> type region 21. Subsequently, a polycrystalline silicon film 23 is formed, and is partly oxidized to convert it into a dioxidized silicon layer 23', thereby forming a gate. Thereafter, ground electrode wirings 24, power source electrode wirings 25 and output electrode wirings 26 are formed, thereby completing a Schottky drain type complementary MOS semiconductor device.

Description

[Detailed description of the invention] (1) Technical field of the invention The present invention relates to improvements in complementary MO8 semiconductor devices.

More particularly, the present invention relates to a highly integrated complementary MO8 conductor housing without latch-up phenomenon.

(2nd Technology Background P-channel type MOB transistor and N-channel type MOB transistor) A transistor is formed on the same semiconductor chip, and the gates and drains of these two transistors are connected, respectively, and the input A voltage is applied between the sources of the two transistors, and the output terminal 1'-o NJ or l'-OF corresponds to positive or negative changes in the input voltage.
A semiconductor device that transforms into an FJ is called a complementary MO8 semiconductor device, and is mainly used as a high-speed, low-power-required logic circuit.

On the other hand, each of the source and drain electrodes is made of metal electrodes that are connected to the semiconductor nose plate with solid contact.
It has been known for some time that it is possible to manufacture an O8) transistor, which is called a Schottky source-drain M08 transistor.

(3) Prior art and problems The complementary MO8 conductor device in the prior art is generally
It has a configuration whose conceptual cross-sectional view is shown in the figure.

In the figure, it is a l#'iP type silicon (8-layer) substrate, 2 has an n-type well region 1, and 3.3 is a high-temperature fii n WIl [bin] which constitutes the source region and drain region of the leg-channel transistor. There is Te, 4.4'HaP? There is an elevated Wp type region constituting a source region and a drain region of a Jannel type transistor, and reference numeral 5 denotes a source electrode 1 of an N channel type transistor, to which a ground potential is applied in this example. Reference numeral 6 denotes a source electrode ffiiaiJ of a P-channel transistor, to which a power supply voltage is applied in this example. 7.8 are the gate electrodes of the N-channel transistor and the P-channel transistor, respectively, which are connected to each other and a common input signal voltage is applied. 09 is the gate electrode of the N-channel transistor and the P-channel transistor, respectively. They are drain electrodes and are connected to each other to form output electrodes. When the input signal has a positive voltage 1 above a certain value, the N-channel transistor goes to rONJ L, and the P-channel transistor goes to "0'F".
IP”, the output electrode is electric! The output of this complementary MC1B hand conductor device is 0 because it is insulated from the 1li11t voltage.

In addition, when the input signal is a negative voltage below a certain value, the P-channel transistor turns OFF, and the LN-channel transistor turns OFF, and the multiplexed potential is output through the output electrode, resulting in the output of this phase amMO8 semiconductor device. becomes a high potential.

By the way, as the degree of integration of the complementary MO8 semiconductor device having the above configuration increases and each element becomes finer, floating carriers are generated due to some stimulus such as block noise.
This causes what is called a latch-up phenomenon. This latch amplifier phenomenon is based on the premise that a PNPN junction or NPNP junction exists, and the above junction functions as a thyristor due to the generation of floating carriers, and there is no forced interruption of current or application of a reverse bias voltage. This is a phenomenon in which a conductive state continues and the complementary MOB becomes unable to function as a conductor device. Fig. 1 shows a conceptual cross-sectional view of the complementary MOB conductor device in the prior art.
In the eight conductor device, (a) between the power supply electrode 6 and the ground electrode 5, that is, between each source 3.4, and (b) the power supply electrode 6
and the drain 3 connected to the output electrode 9, and e
There is a possibility that the occurrence occurs between the drain 4' which is connected to the output voltage 1k10 and the source 3 which is connected to the ground electrode 5, but the probability of occurrence of ←) is the highest because they are close to each other. It is most necessary to prevent this occurrence.

As mentioned above, the occurrence of the latch-up phenomenon requires the dual conditions of the existence of the same junction as the thyristor and the existence or occurrence of floating carriers.If either or both of these conditions are eliminated, the latch-up phenomenon can be prevented. It should be possible to prevent the occurrence of

Therefore, in the prior art, as a means to prevent the latch-up phenomenon by eliminating floating carriers,
As shown in FIG. 2, high impurity regions 31.41 are formed in parallel to each source 3.4, and pm! Silicon (Sl)
If floating carriers are generated in either the substrate 1 or the n-type well region 2, these high impurity regions 31 and 41, respectively.
Floating carriers are caused to flow into either the ground electrode 5 or the power supply electrode through either the ground electrode 5 or the power supply electrode, and the potentials of both the p-type silicon (SL) substrate l and the n-type well region 2 are fluctuated by stimulation such as noise. Complementary Kei M with a configuration that does not have to be done
There is an O51 cow conductor pupil, and it has been confirmed that this configuration is effective in preventing the double amplifier phenomenon.

However, in this prior art, the complementary MO8 semiconductor device having a configuration that can prevent the latch-up phenomenon is
As shown in the figure, since the structure is complicated, it is not necessarily easy to miniaturize the element, and the manufacturing process is also complicated, leaving room for improvement in terms of process and characteristics.

(4) Purpose of the Invention The purpose of the present invention is to realize this improvement (2) to have a simple structure suitable for miniaturization without any characteristic disadvantages such as leakage current, and also to have a manufacturing method thereof. Complementary W with simple f, preventing latch-up phenomenon
The purpose of the present invention is to provide an MO8 conductor device.

(5) Structure of the invention The structure of the present invention is p-type or n! A semiconductor substrate of one conductivity type lj is formed in a part of the surface layer of the semiconductor substrate of the opposite conductivity type, that is, n! having a well area of it or pm;
A pair of MOB field effect transistors each having a different conductivity type of channel are formed on the semiconductor substrate and the query region, and the gate electrode of the pair of MOB field effect transistors is provided. are connected to each other and collectively function as input electrodes, the drain electrodes of the above pair of transistors are connected to each other and collectively function as output electrodes, and the sources of the above pair of transistors are connected to positive and negative power supply terminals, respectively. complementary 1ii
j In the MO8 semiconductor device, the drains of the pair of transistors are in direct contact with the semiconductor substrate and the well region, respectively.
This is because it is considered to be a drain type.

Furthermore, an additional configuration of the present invention, in addition to the above-mentioned basic configuration, is such that at least one of The reason is that the insulating barrier ribs are formed at a depth equal to or greater than the depth of the well region.

The idea of the present invention is that the latch-up phenomenon occurs when pmpai or 1iPNP! The goal is to eliminate the I coupling, and in order to embody this idea, we created an MO8 field effect transistor that does not require a PH8 coupling at the drain! There is a problem using a field-effect transistor with a drain MO8 field effect transistor. As a result, of the three cases in which the latch-up phenomenon may occur, the most important possibility (b) is eliminated, and at the same time, the possibility that the latch-up phenomenon occurs is also eliminated. However, depending on this configuration, the possibility of occurrence of 0) cannot be eliminated.1 If the channel of the element transistor is partially isolated using a partition wall as an additional structure, the possibility of occurrence of (a) can also be effectively eliminated. The structure is relatively simple and does not have the characteristic disadvantage of leakage current which is contrary to the purpose of the present invention.
Complementary type M is suitable for miniaturization, has a simple manufacturing method, and prevents latch-up phenomenon.
It is possible to realize an O8 semiconductor device.

(6) Embodiment of the invention Hereinafter, with reference to the drawings, an embodiment of the invention will be described.
The main steps in the manufacturing method of a complementary MOB conductor device of the shut-off drain type will be explained to further clarify the structure and unique effects of the present invention.

- As an example, an n-well is formed on a p-type silicon (81) substrate, and the gate electrode of each element transistor, that is, the input electrode and wiring of a complementary semiconductor device are made of polycrystalline silicon (81), and the source and drain of each element transistor are The electrodes, that is, the power supply electrodes/wirings and the output electrodes/wirings of the complementary semiconductor device are made of platinum (PT), and each source electrode is connected to a high concentration impurity region by an ohmic contact, while each drain electrode is made of silicon carbon. Complementary type M of the shut-off drain type that is contacted and turned into shut-down drain
Let's take an O8 semiconductor device.

Refer to Fig. 3 101 @ /,, The surface of the silicon (Sl) substrate 11 containing PM impurities is oxidized to a thickness of about 6,000 x silicon dioxide except for the area where the complementary semiconductor device is to be formed. (810,) Form a film to feel P insulating film 1
Set it to 3. Next, this complementary semiconductor device formation area 1
V@ with a width and depth of approximately 1 μm so as to roughly divide 2 into two.
Then, the inside of the trench is filled with silicon dioxide (Sin) to form an insulating isolation region 14.

This barrier rib forming step can be performed using selective etching using KOH followed by selective oxidation.

Refer to FIG. 4. Region 12 where the entire surface of the substrate is oxidized to form a complementary semiconductor device.
A silicon dioxide (S10□) film 15 with a thickness of about 250 mm is formed on top to prevent autodoping in post-processing.
Preparing for n-well formation using the normal photolingtuphy method 7! Territory#
Open the window of 216. Next, silicon dioxide (EII
After implanting ions of an n-type impurity such as arsenic (^1) into the n-well formation area 16 using the resist (indicated by the broken line) as a mask, the resist was removed and 3L of nitrogen was added at approximately 1,050°C. (N,) After heat treatment for about 1 minute in an atmosphere, about 1
Search for voice m 1 Form an n-well 17 containing rsm impurities at an effective concentration of 1o17α1.

Referring to FIG. 5, after uniformly oxidizing the entire surface of the substrate for about 250 μm, an opening 18 is formed by a conventional photolithography method in the region where the source of one N-channel MOS transistor is to be formed. Mua)
After ion implantation of n-type impurities, nitrogen (N
An n+ region 19 containing n-type impurities is formed at a depth of about 2000X and a concentration of "I'10"/α3 by heat treatment for about 10 minutes in an atmosphere.

After oxidizing the entire surface of the substrate (see Figure 6), an aperture is formed in the region where the source of the P-channel MOB transistor is to be formed by ordinary photolithography, and ion implantation of monoron (B)lpJ impurity is performed, followed by further heating at approximately 1000°C. P+ containing pal impurities to a concentration of 10/cIR was heat treated in a nitrogen (N) atmosphere for about 10 minutes to a depth of about 2000 H.
Form the territory 21.

Referring to FIG. 7, after the silicon dioxide (8102) film 15 is removed from the area 12 where the complementary conductor device is to be formed, the substrate is oxidized again and silicon dioxide (stop) is deposited on the same area to a thickness of about soo ) A film n is formed to serve as a gate insulating film. Further, using the OVD method, a polycrystalline silicon (81) film portion containing phosphorus (CP) having a thickness of about λ000X is formed.

Refer to FIG. 8. Both I! of polycrystalline silicon (81) film. It remains only on the gate region of the multilayer transistor and the wiring region connected to these and is removed from other regions, and is thoroughly oxidized to oxidize the surface layer of the remaining polycrystalline silicon (81) film. A silicon (810,) layer n' is converted to form the gate of each element transistor.

These gates are interconnected to form the input electrodes of a parallel MOEI conductor device. At this time, polycrystalline silicon containing phosphorus has a
Oxidation is easy because it is oxidized more than twice as fast as 1.

Refer to FIG. 9 After removing the gate insulating film n from the source region and drain region of both element transistors, forming openings for attaching source and drain electrodes, and forming a platinum (PT) layer on the entire surface of the substrate. If desired, this platinum (PT) layer is left on each source electrode and the wiring region connected to these, on each drain electrode and the wiring region connecting these, and on the wiring region connected to these. Remove from other areas and arrange the ground electrode/wiring U, power electrode/wiring 6, and output electrode! 26 to complete a complementary MO8 semiconductor device of the drain type. Note that the input electrode of this complementary gMO13 semiconductor device is formed by interconnecting the gate fields of each element transistor.

In the complementary ffMO8 conductor device having the queen configuration, there is a PNPN junction between the power supply electrode 6 and the ground electrode, but there is also a connection between the output electrode and the ground electrode between the power supply electrode part and the output electrode U. Since there is no PMPN connection between them, there is no possibility in principle of a latch-up phenomenon occurring outside the board between the power supply electrode 5 and the ground electrode. However, although there is a possibility that a latch-up phenomenon may occur between the power supply electrode and the ground electrode, the existence of the partition wall 14 will prevent the inflow of minority carriers that cause thyristor operation.
, Bs, 24. Note that in the above embodiment, an N-well is formed on a P-type substrate to form a parallel MO8 semiconductor. Although the case where a device is formed is shown, the present invention is not limited to this, and can also be applied to a complementary MO8 semiconductor device 1 in which a P well is formed on an N type substrate.

(7) As described in detail, according to the present invention, the structure is simple and suitable for miniaturization without characteristic disadvantages such as leakage current, and the manufacturing method is also simple. It is possible to provide a complementary MO8 conductor device in which the occurrence of the up phenomenon is prevented.

[Brief explanation of the drawing]

FIG. 1 is a conceptual cross-sectional view of a complementary ff1M08 semiconductor device in the prior art, and FIG. 2 is a conceptual sectional view of a complementary ff1M08 semiconductor device in the prior art.
There is a conceptual cross-sectional view 1 of a complementary MO8 semiconductor device in which measures are taken to prevent latch-up phenomenon. Section 3.4.5.6.7.
FIG. 8.9 shows the system according to the embodiment of the present invention.
There is a conceptual cross-sectional view 1 of a wafer showing the state after completion of each main process in a method for manufacturing a drain type complementary MO84 conductor device.

Claims (1)

[Claims] (11- Having a well region of an opposite conductivity type on the surface layer of a partial region of a semiconductor substrate of a conductivity type, and a pair of MO8s having different conductivity formed on the substrate and the well region, respectively)
field effect transistors, the gates of the pair of transistors are connected to each other to form an input terminal, the drains of the pair of transistors are connected to each other to form an output terminal, and the sources of the pair of transistors are connected to each other to form an output terminal. are phase-shaped MO8 conductor devices, which constitute positive and negative power supply terminals, respectively, and the drain is connected to the substrate surface and the well@
Complementary MOB conductor casting equipment, characterized in that it is in close contact with the clay surface.