JPS5957470A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive improvement in the degree of integration of the titled semiconductor device by a method wherein one transistor is replaced with a semiconductor element formed on an insulating film, and also an insulating film for element isolation is utilized as an insulating film thereof. CONSTITUTION:A selective etching is performed on a polycrystalline Si film 46 using an optical etching method, and polycrystalline Si films 47 and 48 are left on thermal oxide films 44 and 45 respectively. Then, a photoresist is applied on the whole surface, a part of the thermal oxide film 45 located on an Si thin film 43 is exposed by performing exposure and developing processes on said resist, and boron is implanted therein. Another photoresist 51 is applied on the whole surface again, the thermal oxide films 44 and 45 are partially exposed by performing exposure and developing processes on the resist 51, and phosphorus is ion-implanted. Then, an N<+> region 52, a source region 53 and a drain region 54 are exposed by performing a wet etching, and then the resist 51 is removed. Lastly, a source electrode 55, a drain electrode 56 and an anode electrode 57 are formed respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device using a transistor based on a new operating principle.

[Technical background of the invention and its problems]

The C-MO8 type semiconductor device has excellent features such as low power consumption and a large margin against electrical noise, and is therefore used in many semiconductor circuits. When manufacturing a C-MOB type semiconductor device, an n-channel MOB8) transistor and a p
It is necessary to create the f Yarnel MOS transistor on the same semiconductor substrate, but in this case, in order to electrically insulate the nf Yarnel MOB) transistor and the p channel MOB transistor, one of them must be formed using an insulating film region. Must be surrounded. Then, a region made of this insulating film,
Since no element can be formed in the so-called element isolation region, the area of the semiconductor substrate is not effectively utilized, which poses a major problem in improving the degree of integration.

Figure 1 is for explaining the above problem.
FIG. 2 is a cross-sectional view showing the element structure of an inverter. l in the diagram is n
2 is a p-well, 3 is an insulating film for element isolation, 4a and 4b are gate oxide films, 5a and 5b are gate electrodes, and 6a.

Reference numeral 6b indicates a source region, and 7a and 7b indicate drain regions. As can be seen from this figure, p-well 2
and p-channel MOS) transistor source region 6b
An element isolation insulating film 3 (for example, 5000× thick) for electrically isolating the elements.

5 μm in length), which is a factor that hinders miniaturization and high integration of elements.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device which has the same functions as conventional C-MOS semiconductor devices and which can improve the fj density.

[Summary of the invention]

The gist of the present invention is to replace one transistor of a conventional C-MO8 semiconductor device with a semiconductor element formed on an insulating film based on a new operating principle, and to use an element isolation insulating film as the insulating film. It is in.

Here, the semiconductor device will be explained based on the above-mentioned new operating principle. This semiconductor device is described in the literature (Technical Report of Institute of Electrical Communication Engineers, 5SI)-81-131°P1-5), and the structure of the device is shown in FIG. Insulator substrate 1
A semiconductor layer 15 having a thickness of approximately 0.1 to 0.5 [μ77+] and having an n+ type region 12, an n type region 13, and a p+ type region 14 is formed on the semiconductor layer 1. A control electrode 17 is formed on the n-type region 13 via an insulating film 16 with a thickness of approximately 0.02 to 0.05 Cμm, and a control electrode 17 is formed in the n++ region I2 (cathode) and the p++ region 14 (anode), respectively. Electrodes 18,19 are connected. Potential f VGX of control electrode 17 with reference to cathode electrode 18, anode electrode 19
This semiconductor element has electrical characteristics as shown in FIG. 3. That is, the current flowing through the p-n junction formed at the boundary between the anode 14 and the n-type region 13 is controlled by VGx, and even if, for example, 5 [V] is applied in the forward direction to both ends of the p-n junction, VOK is about 4.5 (V)
If this is the case, no current will flow through this p-n junction.

FIG. 4 shows equivalent symbols for the above elements used in the following explanation. Terminals 2'l and 28.29 are electrodes 1 in FIG.
7.18.19 respectively.

When this semiconductor element and an n-channel MO8) transistor are connected as shown in FIG.
It will be explained that the same signal processing as the stage can be realized. In Fig. 5, the input voltage of the C1 input terminal 31 is, for example, 5 [V].
At this time, the element 32 is in the OFF state as described above. At this time, the Sn channel MO8) transistor 33 is turned on, so the output terminal 34 becomes 0 [v].

Also, when the input voltage is 0 (V), the n-channel MO8
) The transistor 33 turns OFF, and the element 32 turns ON.
state, the output terminal 34 is the same as the power supply terminal 35.
It becomes [v]. That is, it operates in the same way as a C-MOS inverter. In the above description, the element structure of a semiconductor element (transistor) based on a new operating principle is n''-n-p+, but the same function can be obtained with an n''-p-p+ structure.

The present invention focuses on these points, and forms a first transistor with an MO8 type structure on the element formation region of the semiconductor substrate, and also forms the above-mentioned lateral p+-p-n+ on the element isolation insulation crotch of the semiconductor substrate. Alternatively, a second transistor having a p"-n-n+ tank structure is formed, and the first and second transistors are connected between the power supply and the ground terminal, and the gate electrode of the first transistor and the second transistor are connected between the power supply and the ground terminal. The control electrodes of the transistors are connected to the same input terminal, and one of the source or drain of the first transistor and one of the p+ region or the n region of the second transistor are connected to the same output terminal. It is something.

[Effects of the Invention] According to the present invention, it is possible to realize low power consumption similar to the C-MO8 semiconductor device due to the characteristics of the second transistor described above. Since transistors are formed, it is possible to achieve high density, that is, high integration, which is difficult to achieve with a C-MO8 semiconductor device.

[Embodiments of the invention]

FIGS. 6(a) to 6(g) are sectional views showing a semiconductor device manufacturing process according to an embodiment of the present invention. First, the 6th
As shown in Figure (a), p-type S1 substrate (semiconductor substrate) 4
After partially forming a field oxide film (insulating film for element isolation) 42 with a thickness of 6,000 to 8,000 mm on top of 1,
Using CVD method, the entire surface is coated with n-type S with a thickness of 4000 [A].
An i thin film (semiconductor thin film) 43 was formed, and then the Sl thin film 43 on the top of the field oxide film 42 was left and the rest was removed.

Next, as shown in FIG. 6(b), the entire surface is thermally oxidized,
An oxide film 54,55 with a thickness of about 300 mm was formed, and then a polycrystalline St 2 film 46 with a thickness of about 5 mm was deposited on the entire surface using the CVD method.

In this state, the polycrystalline St film 46 is selectively etched using a photoetching method as shown in FIG. 6(C), and the thermal oxide film 44 is etched.
．． Polycrystalline St 2 films 47 and 48 were left on 45, respectively.

Next, a photoresist 49 is applied to the entire surface as shown in FIG.
A part of the thermal oxide film 45 on the thin film 43 was exposed, and then boron ions were implanted using the resist 49 as a mask.

By this ion implantation, a p+ region anode 50 is formed in a part of the Sl thin film 43. In addition, the conditions for ion implantation are an acceleration voltage of 40 (KV) and a dose of 3 X l O
"(cm-'). Next, after removing the exposed portion of the thermal oxide film 45 by wet etching, a photoresist 51 is again applied to the entire surface as shown in FIG. 6(e), and this resist 51 is exposed to light. The resist 51 was developed to expose a portion of the thermal oxide film 44 and a portion of the thermal oxide film 45.
As a mask, the acceleration voltages 40 (KV, l and 80 (KV
)-C' Two ions of phosphorus were implanted. The reason why the ion implantation is performed twice is that the peak concentration of phosphorus must be formed at a relatively shallow location in the thin film 43 and relatively deep in the substrate 41. With this ion implantation,
An n+ region (cathode) 52 is formed in a part of the St thin film 43.
A source region 53 and a drain region 54 are also formed in the substrate 41. Thus, to the left in the figure]
A transistor (first transistor) (f-Yarnel MO8) is created, and a transistor (second transistor) based on a new operating principle is created on the field oxide film 42 on the right side of the figure.

Next, wet etching is performed as shown in Figure 6(f).
+ region 52, source region 53, and drain region 54 were exposed, and then resist 51 was removed. Finally, the 6th
As shown in figure (g), a source electrode 55 and a drain electrode 56
And the anode electrode 57 was completely formed. At this time, the drain electrode 56 also serves as a cathode electrode.Although not shown in the figure, the gates of the two transistors made of polycrystalline Si films 47 and 48 are electrically connected outside the illustrated cross section. The semiconductor device formed in this way has the same function as a conventional C-MOS inverter, as described above.

In this case, the second transistor, which replaces the p-channel MO transistor (8), is formed on the field oxide film 42, so that the overall occupied area can be significantly reduced. In other words, it is possible to improve the degree of integration.

Furthermore, since the n-channel MO8) transistor and the second transistor are electrically conductive only in the n-region, they are of a single carrier type, and can eliminate the latch-up phenomenon that has been a problem with the C-MO8.

Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, the second transistor is n
It is not limited to the +-n-p+ structure, but may be an n,"-p-p+ structure.

Similarly, it is also possible to use a combination with a p-channel MO8 transistor instead of the n-channel MO8 transistor. Also, as the impurity doping step, a solid phase diffusion method may be used instead of thermal diffusion. Furthermore, it goes without saying that reactive ion etching may be used instead of wet etching for etching the thermal oxide film.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view showing the elementary F structure of a conventional C-MOS inverter, Figs. 2 to 5 are for explaining the present invention in detail, and Fig. 2 is a semiconductor based on a new operating principle. Figure 3 is a cross-sectional view showing the element structure of the element, Figure 3 is a characteristic diagram showing its operating characteristics, Figure 4 is a diagram showing its equivalent symbol, and Figure 5 is a circuit that combines the above element and a conventional MOS transistor. The equivalent circuit diagrams shown in FIGS. 6(a) to 6(g) are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. 41...p-type Si substrate (semiconductor substrate), 42...
・Field oxide film (insulating film for element isolation), 43...
n-type 3i thin film (semiconductor thin film), 44.45...thermal oxide film, 46,47.48...polycrystalline St film, 4
9.61...Photoresist, 50...p+ region (anode), 52...n+ region (cando), 53
...11+ region (source region), b4...n+ region (drain region), 55... source electrode, 56...
Drain electrode, 57... anode electrode. Applicant's representative Patent attorney Takehiko Nishikie Figure 1 Figure 2 Figure 4 Figure 6 Figure fJ6 Figure 341-

Claims (1)

[Claims] A first transistor with an MO8 type structure provided on an element formation region of a semiconductor substrate, and a lateral p+-p-n+ or p+-n-n+ semiconductor film provided on an element isolation insulating film of the semiconductor substrate. and a second transistor formed by forming a tank structure and a control electrode formed on the p-region lid or the n-region via an insulating film, and the first and second transistors are connected to a power supply and a ground. the gate electrode of the first transistor and the control electrode of the second transistor are connected to the same input terminal, and one of the source or drain of the first transistor and the control electrode of the second transistor p+ region cover of transistor No. 2 or r
A semiconductor device characterized in that one of the regions is connected to the same output terminal.