JPH11317526A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a leakage current from flowing between a semiconductor layer and a support substrate by a method wherein a shallow isolation layer is provided to an SOI substrate as deep as a halfway point in a semiconductor layer through the primary surface of the semiconductor layer, and a deep isolation layer is selectively provided so as to reach an insulating layer through the primary surface. SOLUTION: A deep isolation layer 4A and a shallow isolation layer 4B are provided on the semiconductor layer of an SOI substrate 1A. The deep isolation layer 4A is formed in a manner where an isolating insulating film such as a silicon oxide film is filled into a groove formed on the primary surface of the semiconductor layer so as to reach the upside of a buried insulating layer. The deep isolating parts 4A (4A1 to 4A5 ) are selectively formed at levels lower than the primary surface of the semiconductor layer to serve as isolating parts or other functional parts. The shallow isolation part 4B is formed in a manner where an isolating insulating film such as a silicon oxide film is filled into a groove which is formed so as to reach a halfway point in the semiconductor layer penetrating through the surface of the semiconductor layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to an SOI (Silicon On I / O) having a semiconductor layer for element formation on a buried insulating layer.
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device using a substrate.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device using an SOI substrate is disclosed in, for example, (1) Yo-Hwan Koh, Jin-Hyeok Choi, M.
yung-Hee Nam, and Ji-Woon Yang, “Body-Contacted SOI
MOSFET Structure with Fully Bulk CMOS Compatible
Layout and Process, ”IEEE Trans. Electron Device
s, Vol.18, NO.3, pp.102-104, MARCH 1997., (2) .W.Chen, Y.
Taur, D.Sadan a, KAJSUN, and S.Cohen, Suppression
of the SOI Floating-body Effects by Linked-body De
vice Structure, 1996 Symposium on VLSI Technology D
It is described in igest of Technical Papers.pp.92,1996.

All of these documents describe a method of reducing the substrate floating effect of a MOS-FET formed on an SOI substrate. A semiconductor layer is left below an isolation portion, and a gate electrode is formed through the semiconductor layer. A technique is disclosed in which a predetermined potential is supplied to the well to stabilize the potential of the well and reduce the substrate floating effect.

[0004]

However, the present inventor has found that there is the following problem in the technique of leaving a thin semiconductor layer between the bottom surface of the isolation part and the buried insulating layer in the SOI substrate.

First, when an SOI substrate having the above structure is used and a back gate is formed on a support substrate, the back gate is formed on the semiconductor layer due to moisture, dirt, etc. attached to the side surfaces of the semiconductor chip. There is a problem that a leak current flows between the well and the back gate formed on the supporting substrate.

In a semiconductor integrated circuit device using an SOI substrate, a back gate may be provided on a supporting substrate below a buried insulating layer. The purpose of the back gate is to adjust the threshold voltage (Vth), reduce the floating effect of the substrate, and perform element isolation. Ideally, the semiconductor layer for element formation and the supporting substrate are electrically separated by a buried insulating layer. However, in reality, leakage current flows between the semiconductor layer and the back gate due to moisture, contamination, and the like attached to the side surface of the semiconductor chip. In a normal SOI substrate structure, the field insulating film and the trench isolation constituting the isolation portion reach the buried insulating layer, so that the elements are completely electrically isolated within the semiconductor chip. Leakage current on the side of the semiconductor chip does not matter.
However, in the case of an SOI substrate structure in which the semiconductor layer is left under the separation portion, the semiconductor layer is exposed on the side surface of the semiconductor chip. In this way, the well formed in the semiconductor layer and the back gate of the supporting substrate are electrically connected, and a leak current flows between them. For this reason, the potential of the well is dragged by the potential of the back gate, a desired voltage is not applied to the buried insulating layer, and the effect of the back gate is lost or power consumption is increased due to leakage current. Occur.

Second, there is a problem that junction capacitance and wiring capacitance increase. That is, in the case of the structure in which the semiconductor layer is left under the separation portion, the p-type well and the n-type well are not completely separated from each other and are in contact with each other to form a pn junction. Increase. Further, since the semiconductor layer remains under the separation portion, the capacitance of the wiring formed above the separation portion also increases.

Third, there is a problem that the reliability of the device is reduced. That is, in the case of the structure in which the semiconductor layer is left under the isolation portion, the p-type well and the n-type well are in contact with each other in the semiconductor layer, so that the possibility of latch-up is increased. Further, in the case of configuring this structure, it is not sufficiently considered that elements having different driving voltages may be arranged in the semiconductor chip. Therefore, the region of the semiconductor layer where elements having different driving voltages are formed is not considered. There is a problem in that they come into contact with each other and adversely affect a circuit having a high drive voltage from a circuit having a high drive voltage through the portion.

Fourth, there is a problem that it is difficult to detect a mark in a photolithography process, an inspection process, or the like. In a manufacturing process of a semiconductor integrated circuit device, alignment between patterns is performed by detecting a mark provided on an SOI substrate side, inspection is performed, or a CMP (Chem.
ical Mechanical Polishing) process and the thickness of nano-spec insulating film in dry etching process. By the way, in the case of the above-described structure in which the semiconductor layer is left under the separation portion, the semiconductor layer remains under the mark. However, in any case, light is used for the mark detection. Part), the semiconductor layer remains under
Reflected light from the interface between the semiconductor layer and the buried insulating film and the interface between the semiconductor layer and the separation portion adversely affect mark detection, making accurate mark detection and measurement difficult.

An object of the present invention is to prevent a leak current from flowing between a semiconductor layer and a supporting substrate in a semiconductor integrated circuit device using an SOI substrate in which a semiconductor layer is left under an isolation portion. It is to provide the technology that can be done.

It is another object of the present invention to provide a technique capable of reducing unnecessary capacitance in a semiconductor integrated circuit device using an SOI substrate in which a semiconductor layer is left under a separation portion.

Another object of the present invention is to provide a technique capable of improving reliability in a semiconductor integrated circuit device using an SOI substrate in which a semiconductor layer is left under a separation portion.

A further object of the present invention is to provide a technique capable of improving mark detection accuracy in a semiconductor integrated circuit device using an SOI substrate in which a semiconductor layer is left under a separation portion.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a semiconductor chip formed using an SOI substrate having a semiconductor layer provided on a support substrate via an insulating layer, The SOI substrate is provided with a shallow isolation portion extending from the main surface of the semiconductor layer to a depth position in the middle thereof, and a deep isolation portion extending from the main surface of the semiconductor layer to the insulating layer is provided at a selective plane position. It is a thing.

A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a semiconductor chip composed of an SOI substrate having a semiconductor layer provided on a support substrate via an insulating layer, wherein the semiconductor layer has A relatively shallow separation part reaching the middle depth position of the semiconductor layer from the main surface, and a relatively deep separation part reaching the insulating layer from the main surface of the semiconductor layer, the deep separation part, It is formed to extend along the outer periphery of the semiconductor chip.

Further, according to the semiconductor integrated circuit device of the present invention, there is provided an SOI device having a semiconductor layer provided on a supporting substrate via an insulating layer.
A semiconductor integrated circuit device having a semiconductor chip composed of a substrate, wherein the semiconductor layer has a relatively shallow separation portion reaching from the main surface to a position in the middle of the semiconductor layer,
A relatively deep isolation portion extending from the main surface of the semiconductor layer to the insulating layer is provided, and the deep isolation portion is provided so that circuit regions having different driving voltages are electrically separated from each other.

Further, the semiconductor integrated circuit device of the present invention has an SOI structure in which a semiconductor layer is provided on a supporting substrate via an insulating layer.
A semiconductor integrated circuit device having a semiconductor chip composed of a substrate, wherein the semiconductor layer has a relatively shallow separation portion reaching from the main surface to a position in the middle of the semiconductor layer,
Providing a relatively deep isolation portion reaching the insulating layer from the main surface of the semiconductor layer, such that the deep isolation portion is configured such that semiconductor regions of different conductivity types formed in the semiconductor layer are electrically isolated from each other. It is provided.

Further, the semiconductor integrated circuit device of the present invention has an SOI structure in which a semiconductor layer is provided on a supporting substrate via an insulating layer.
A semiconductor integrated circuit device having a semiconductor chip composed of a substrate, wherein the semiconductor layer has a relatively shallow separation portion reaching from the main surface to a position in the middle of the semiconductor layer,
A relatively deep isolation portion extending from the main surface of the semiconductor layer to the insulating layer is provided, and the deep isolation portion is provided so as to cover a wiring region where an integrated circuit element is not formed in the semiconductor layer.

Furthermore, the semiconductor integrated circuit device of the present invention
SO comprising a semiconductor layer provided on a supporting substrate via an insulating layer
A semiconductor integrated circuit device having a semiconductor chip composed of an I-substrate, wherein a relatively shallow separation portion extending from a main surface of the semiconductor layer to an intermediate depth position in the semiconductor layer; A relatively deep separating portion reaching from the surface to the insulating layer, and a mark is formed by the deep separating portion.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

(Embodiment 1) FIG. 1 is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA of FIG. 3 is a cross-sectional view taken along the line BB of FIG. 1, FIG. 4 is a cross-sectional view taken along the line CC of FIG. 1, and FIG. 5 is a modification of the present embodiment, which is a semiconductor chip constituting a semiconductor integrated circuit device. FIG. 6 is a sectional view taken along line AA of FIG. 5, and FIGS. 7 to 14 are FIGS.
30 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step thereof; FIG. Note that FIGS. 1 to 6 show a state where there is no wiring layer above the gate electrode in order to make the drawings easy to see.

In the first embodiment, the present invention is applied to, for example, a CMOS (Complimentary Metal Oxide Semiconductor).
tor) A case where the present invention is applied to a logic circuit will be described.
As shown in FIGS. 1 to 4, for example, a main surface of a semiconductor chip 1 formed in a plane quadrangular shape has an input / output circuit formation region I / O (upper right side in FIG. 1) and a logic circuit formation region L
G (substantially half on the left side in FIG. 1), a wiring area L (lower right side in FIG. 1), and a mark M (lower right lower side in FIG. 1) are arranged.

The input / output circuit formation area I / O is an area where input / output circuits such as an input circuit, an output circuit, and an input / output bidirectional circuit are arranged. Channel type MOS ・ FET (Metal Oxide Se
miconductor Field Effect Transistor; hereafter, nMO
Abbreviated as S) Qn1 and p-channel type MOSFET
(Hereinafter abbreviated as pMOS) Qp1 is provided. The logic circuit formation region LG is a region where a predetermined logic circuit is arranged. In this region, a plurality of nMOS Qn2 and pMOS Qp2 constituting the circuit are formed. The driving voltage of the input / output circuit is, for example, 5
V, and the drive voltage of the logic circuit is lower than the drive voltage of the input / output circuit, for example, about 1.5 to 3.3 V.

The wiring region L is a region where wiring for electrically connecting the elements in the semiconductor chip 1 is arranged, and the element itself is not arranged here. Mark M
By detecting the reflected light of the light irradiated here, pattern alignment, inspection, or CMP (Chemical Mecha) is performed at the time of forming elements and wirings.
This is to measure the thickness of the nano-spec insulating film in the nical polishing (dry polishing) process or the dry etching process. The planar shape of the mark M is formed, for example, in a cross shape.
However, the plane shape of the mark M is not limited to this, and can be variously changed, for example, an I-shape, an L-shape,
It may be a frame, a square, or a group of a plurality of parallel bar patterns. In FIG. 1, the mark M is drawn relatively large in order to make the drawing easy to see, but the actual size is for alignment at the time of the photolithography process, for example, 10 mm.
For example, it is about 50 μm × 50 μm for measurement in the CMP process.

The SOI substrate 1A constituting the element forming substrate of the semiconductor chip 1 is constituted by providing a thin semiconductor layer 1A3 for element formation on a supporting substrate 1A1 via a buried insulating layer 1A2. Supporting substrate 1A1, for example n ^-
Shaped silicon single crystal, mainly SOI substrate 1A
It has a function to ensure the mechanical strength of In the supporting substrate 1A1, a portion below the formation region of the nMOSs Qn1 and Qn2 and in contact with the buried insulating layer 1A2 is provided with a p-type semiconductor region 2bg1 for forming a back gate.
2bg2 is formed. This semiconductor region 2bg1,2
bg2 is, for example, boron-introduced, and nMOSQ
It has functions such as adjustment of the threshold voltage (Vth) of n1 and Qn2, reduction of the substrate floating effect, and element isolation. The semiconductor regions 2bg1 and 2bg2 are configured to be supplied with a potential from the main surface side of the SOI substrate 1A. That is,
The semiconductor regions 2bg1 and 2bg2 are electrically connected to wiring formed on the main surface of the SOI substrate 1A, and a voltage of a predetermined potential is applied through the wiring. The voltage applied to the semiconductor regions 2bg1 and 2bg2 is a negative voltage of 0 (zero) V or less, for example, about -5 V, and the Vth of the nMOSs Qn1 and Qn2 is shifted in the positive direction (Vth
In the upward direction (hereinafter the same). On the other hand, the support substrate 1A1
It also has a function as a back gate of p2. That is, a predetermined potential is supplied to the support substrate 1A1 from the main surface or the back surface of the SOI substrate 1. As this potential, a positive potential higher than the potential applied to the semiconductor regions 2bg1, 2bg2, for example, about 5 V is applied, and the pMOSs Qp1, Qp2
Has the effect of shifting Vth in the positive direction (actually a negative direction, but a positive direction in the direction of increasing Vth).

The buried insulating layer 1A2 is, for example, 0.1 μm thick.
The support substrate 1A1 and the semiconductor layer 1A3 are sandwiched between them so as to be electrically separated from each other. In the connection region between the back gate semiconductor regions 2bg1 and 2bg2 and the wiring, the buried insulating layer 1A2 is partially removed so that both are electrically connected to each other.

The semiconductor layer 1A3 for element formation is made of, for example, a p-type silicon single crystal having a thickness of about 0.2 μm, and a p-well 3pw is formed in a region where the nMOS Qn1 and Qn2 are formed.
1,3pw2 are formed, and n-wells 3nw1,3nw2 are formed in the formation regions of the pMOSs Qp1, Qp2. The semiconductor layer 1A3 and the p wells 3pw1, 3pw
2 is introduced with, for example, boron, and n wells 3nw1,3
For example, phosphorus or arsenic is introduced into nw2.

In the first embodiment, two types of separation parts, a deep separation part 4A and a shallow separation part 4B, are formed in the semiconductor layer 1A3 of the SOI substrate 1A.
In FIG. 1, a hatched hatching is applied to the deep separating portion 4A to make the drawing easier to see, and the shallow separating portion 4B
Is not hatched.

The deep isolation portion 4A is formed by embedding an isolation insulating film such as a silicon oxide film in a groove formed so as to reach from the main surface of the semiconductor layer 1A3 to the upper surface of the buried insulating layer 1A2. Is formed. In the first embodiment, the deep separation portion 4A (4A1 to 4A5)
Are selectively formed as separation parts or other functional parts in the following plane positions on the main surface of the semiconductor layer 1A3.

First, a deep isolation portion 4A1 is formed so as to surround the inside of the semiconductor chip 1 along the outer periphery of the semiconductor chip 1. Thus, the semiconductor layer 1A3 for element formation and the semiconductor regions 2bg1, 2b for the back gate are formed.
g2 can be completely electrically separated from the well, so that the well of the semiconductor layer 1A3 and the semiconductor region 2bg1,
2bg2 can be prevented from conducting through moisture, contaminants, etc. attached to the side surface of the semiconductor wafer during the manufacturing process (inspection process) of the semiconductor chip 1 or the semiconductor integrated circuit device. The plane pattern of the deep isolation portion 4A1 is formed as a relatively wide pattern extending from the outer periphery of the semiconductor chip 1 toward the center of the semiconductor chip 1.

Second, a deep isolation portion 4A2 is formed so as to surround a formation region I / O of an input / output circuit having a high drive voltage. Thus, the input / output circuit having a relatively high drive voltage and the logic circuit having a relatively low drive voltage can be completely electrically separated in the semiconductor layer 1A3.
It is possible to prevent an adverse electrical effect from being exerted on the circuit region having a relatively high driving voltage to the circuit region having a relatively low driving voltage through the semiconductor layer 1A3.

Third, the deep isolation portion 4A3 is formed by a p-well 3p
It is formed in the boundary region between w1,3pw2 and n-wells 3nw1,3nw2. Thereby, p well 3pw1,3p
Since w2 and n-wells 3nw1 and 3nw2 can be completely electrically separated from each other, the formation of a pn junction by the well can be prevented, and the junction capacitance can be reduced. Also, p wells 3pw1, 3pw2 and n well 3nw
Since 1,3nw2 can be completely electrically separated, latch-up can be prevented.

Fourth, the deep isolation region 4A4 is formed in the wiring region L
Is formed. That is, by forming the deep isolation region 4A4 in the wiring region L where no element is formed, S
It is possible to reduce the wiring capacitance parasitic on the wiring formed on the main surface of the OI substrate 1A. The deep isolation region 4A4 is formed, for example, in a planar rectangular shape.

Fifth, the mark M is formed by a deep isolation region 4A5. Thereby, silicon-
Since the interface between the silicon oxide films can be reduced, and the reflected light from the silicon-silicon oxide film that interferes with inspection and measurement using light can be reduced, the mark M can be detected during the inspection and measurement. It is possible to improve accuracy.

On the other hand, the shallow isolation part 4B is formed in the semiconductor layer 1A3
An isolation insulating film such as a silicon oxide film is buried in a groove extending from the main surface to a depth position in the middle of the semiconductor layer 1A3. That is, the semiconductor layer 1A3 is left under the shallow isolation portion 4B. Thereby, the well potential can be supplied stably, and the substrate floating effect can be reduced. n-well 3n
The supply of the potential to w1,3nw2 is performed from the main surface side of the SOI substrate 1A through the connection holes 5a1,5a2 opened in the shallow separation section 4B, and the supply of the potential to the p-wells 3pw1,3pw2 is Connection holes 5b1, 5b opened in 4B
2 through the main surface side of the SOI substrate 1A. The connection holes 5a1,5 for supplying the well potential
Although no single a2, 5b1, 5b2 is shown, a plurality of a2, 5b1, 5b2 may be provided for each well. Further, the area of the connection holes 5a1, 5a2, 5b1, 5b2 may be increased. These make it possible to improve the heat radiation effect.

Such a deep separation part 4A and a shallow separation part 4
B, the above-mentioned nMOS Qn1,
Qn2 and pMOSs Qp1 and Qp2 are formed.
Each of the nMOSs Qn1, Qn2 has a p-well 3pw1, 3p
w2, a pair of semiconductor regions 6nd, 6n
d, a gate insulating film 7i formed on the main surface of the semiconductor layer 1A3, and a gate electrode 8g formed on each of them. Each of the pMOSs Qp1 and Qp2 has a pair of semiconductor regions 6pd and 6pd formed in each of the n-wells 3nw1 and 3nw2, a gate insulating film 7i formed on the main surface of the semiconductor layer 1A3, and a respective one thereof. And a gate electrode 8g formed thereon.

The pair of semiconductor regions 6pd, 6pd have pM
This is a region for forming source / drain regions of OSQp1 and Qp2, and is formed apart from each other with a channel region therebetween. The pair of semiconductor regions 6pd, 6pd
Is set to be p-type by introducing boron, for example.
The pair of semiconductor regions 6nd and 6nd are formed of nMOSQ.
This is a region for forming source and drain regions of n1 and Qn2, and is formed apart from each other with a channel region therebetween. The pair of semiconductor regions 6nd and 6nd are set to be n-type by introducing, for example, phosphorus or arsenic. The nMOS Qn1, Qn2 and pMOS Qp1, Q
The p2 channel region is completely depleted when a gate voltage substantially equal to Vth is applied to the gate electrode 8g. When the entire channel region is depleted, there is no floating region, so that the accumulation of holes over time is eliminated. As a result, the kinking of the MOSFET
The occurrence rate of the characteristics can be reduced, and the fluctuation of Vth can be suppressed.

Each of the semiconductor regions 6pd and 6nd is formed adjacent to a high-concentration region having a relatively high impurity concentration determining the conductivity type and a channel region, and has a relatively high impurity concentration determining the conductivity type. A structure having a low concentration region for suppressing low hot carriers may be employed. In the low-concentration region, the source region is located near the bottom corner on the channel region side.
A structure in which a pocket region for suppressing punch-through between drains may be provided. This pocket region is set to a conductivity type opposite to the conductivity type of semiconductor regions 6pd and 6nd.

The gate insulating film 7i is made of, for example, a silicon oxide film having a thickness of about 8 nm. The thickness of the gate insulating film 7i of the nMOS Qn1 and the pMOS Qp1 forming the input / output circuit is changed by the nMOS Qn forming the logic circuit.
The thickness may be larger than the thickness of the gate insulating film 7i of n2 and pMOS Qp2. As a result, the withstand voltage of the gate insulating film 7i can be ensured on the input / output circuit side where the drive voltage is high, and the operation speed can be improved on the logic side where the drive voltage is low. Further, the gate insulating film 7i is formed of an oxynitride film (SiO
N). Thereby, the gate insulating film 7i
Since the generation of interface states in the gate insulating film 7i can be suppressed and electron traps in the gate insulating film 7i can be reduced, the hot carrier resistance of the gate insulating film 7i can be improved. Therefore, the reliability of the gate insulating film 7i can be improved.

As a method of oxynitriding the gate insulating film 7i, for example, a method of performing a high-temperature heat treatment in an NH ₃ gas atmosphere or a NO ₂ gas atmosphere when forming the gate insulating film 7i by an oxidation treatment, After forming a gate insulating film 7i made of a film or the like, a method of forming a nitride film on the upper surface thereof, a method of performing ion implantation of nitrogen on the main surface of the semiconductor layer 1A3 and then performing an oxidation treatment for forming the gate insulating film 7i Alternatively, there is a method in which nitrogen is ion-implanted into a polysilicon film for forming a gate electrode and then heat treatment is performed to deposit nitrogen on the gate insulating film 7i.

The gate electrode 8g is made of a single film of low-resistance polysilicon which is set to an n-type by introducing phosphorus, for example. However, the structure of the gate electrode 8g is not limited to this, and can be variously changed. For example, a so-called polycide structure in which a silicide layer such as tungsten silicide is provided on low-resistance polysilicon may be used. Further, for example, a so-called polymetal structure in which a metal film such as tungsten is provided on low-resistance polysilicon via a barrier metal film such as titanium nitride or tungsten nitride. When a polymetal structure is employed, the electric resistance of the gate electrode 8g can be significantly reduced. This structure is particularly effective when the gate width of the gate electrode 8g is long.

Note that a sidewall made of, for example, a silicon oxide film, a silicon nitride film, or a composite film thereof may be formed on the side surface of the gate electrode 8g. This sidewall normally functions as a mask for impurity ion implantation when forming the above-described high-concentration region so as to form the above-mentioned low-concentration region in a self-aligned manner. When formed by a film, the sidewall can be made to function as an etching stopper when a connection hole is formed so that the semiconductor regions 6pd and 6nd are exposed in the interlayer insulating film.
Thus, the connection holes can be formed in a self-aligned manner with good alignment, so that the layout area of the element can be miniaturized, reliability can be improved, and characteristics can be improved.

A plurality of wiring layers are provided on the main surface of such an SOI substrate 1 with an interlayer insulating film interposed. Wiring for electrically connecting elements is formed in a pattern on each wiring layer. This wiring is made of a metal such as aluminum, aluminum-silicon-copper alloy or tungsten. Note that this wiring may be formed by a buried wiring. That is, when forming the wiring, a so-called Damascene method or a dual damascene (Du
al-Damascene). In the damascene method, after a trench for forming a wiring is formed in an interlayer insulating film, the SOI substrate 1A is formed.
A conductive film for forming a wiring is deposited on the entire main surface of the substrate, and the conductive film in a region other than the groove is removed by CMP or the like, thereby forming a buried wiring in the groove for forming the wiring. . The dual damascene method is an application of the damascene method. After forming a groove for forming a wiring and a connection hole for connecting to a lower layer wiring in an interlayer insulating film, the wiring for forming a wiring is formed on the entire main surface of the SOI substrate 1A. In this method, a conductive film is deposited, and the conductive film in a region other than the groove is removed by CMP to form a buried wiring in a wiring forming groove and to form a plug in a connection hole. . These embedded wirings are made of, for example, a copper-based conductor material (copper or copper alloy).
Consists of From the viewpoint of preventing the diffusion of copper atoms, the periphery of the copper-based conductor material may be surrounded by, for example, a titanium-based barrier metal film.

By the way, in FIG.
A1 was formed in a relatively wide pattern.
As shown in FIG. 6, the deep isolation portion 4A1 may be formed in a narrow pattern. In this case, the same effect as described above can be obtained. Other than that, the description is omitted because it is the same as the above.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 7, the SOI substrate 1A
(At this stage, an SOI wafer) is prepared. Support substrate 1
A1 is set to, for example, n-type, and the semiconductor layer 1A3 is set to, for example, p-type. The boron concentration of the semiconductor layer 1A3 is, for example, about 4 × 10 ¹⁵ cm ³ . SOI
The substrate 1A is manufactured by a bonding technique or a SIMOX technique. In the bonding technique, a non-oxidized semiconductor wafer and an oxidized semiconductor wafer are bonded to each other and heat-treated to improve the bonding strength between the two wafers. 1A3
This is a technique for manufacturing an SOI substrate by forming an SOI substrate. In this case, as a method of shaving the semiconductor wafer, for example, there is a method of shaving only by plasma etching or a method of performing plasma etching after mechanical polishing. S
In the IMOX technique, oxygen ions are implanted at a predetermined depth from a main surface of a semiconductor wafer at a predetermined dose, and then heat treatment is applied to the buried insulating layer 1A2 having a predetermined thickness at the position where the oxygen ions are implanted. Is formed, and a semiconductor layer 1A3 is formed thereover.

Subsequently, as shown in FIG.
An insulating film made of, for example, a silicon nitride film is deposited on the main surface of the semiconductor layer 1A3 of A by CVD or the like, and is patterned by photolithography and etching to form an insulating film 9 covering the active region.
Is formed. Thereafter, a photoresist pattern 10 is patterned on the semiconductor layer 1A3 so as to cover the active region (the insulating film 9) and the region where the shallow isolation portion is formed.

Next, the photoresist pattern 10
The semiconductor layer 1A3 exposed from the photoresist pattern 10 is removed to an intermediate depth position as shown in FIG. The removal thickness at this time is, for example, about 0.15 μm.

Subsequently, after removing the photoresist pattern 10 (see FIG. 8), the semiconductor layer 1A3 exposed from the insulating film 9 is subjected to dry etching using the insulating film 9 as a mask as shown in FIG. Remove. The removal thickness at this time is, for example, about 0.15 μm. As a result, the upper surface of the buried insulating layer 1A2 can be exposed in the formation region of the deep isolation portion, and the semiconductor layer 1A3 can be left in the formation region of the shallow isolation portion.

Then, after the insulating film 9 is removed by etching with hot phosphoric acid or the like, the main surface of the SOI substrate 1A (the semiconductor layer 1) is removed.
An insulating film made of, for example, a silicon oxide film or the like is formed on the surface on which A3 is formed) by a CVD method or the like, and is then removed by a CMP method or the like so that the insulating film remains only in the isolation region. As shown in FIG.
A and a shallow isolation portion 4B are formed.

Next, a photoresist pattern is formed on the main surface of the SOI substrate 1A so as to cover the p-well formation region and expose the n-well formation region, and then use this as an ion implantation mask to form a semiconductor layer 1A3. Then, for example, phosphorus is accelerated at an energy of about 150 keV,
At about × 10 ¹² cm ^-2 , as shown in FIG.
An n-well 3nw1 (3nw2) is formed.

Then, using the photoresist pattern as an ion implantation mask, the semiconductor layer 1A3 is doped with, for example, boron at an acceleration energy of about 10 keV and a dose of 5 × 1.
The implantation is performed at about 0 ¹² cm ⁻² to form a buried channel of pMOS.

Next, after removing the photoresist pattern, a photoresist pattern is formed on the main surface of the SOI substrate 1A so as to cover the n-well formation region and expose the p-well formation region. I do. And
Using the photoresist pattern as an ion implantation mask, for example, boron is implanted into the semiconductor layer 1A3 at an acceleration energy of about 80 keV and a dose of about 4 × 10 ¹² cm ⁻² to form a p-well 3pw1 (3pw2).

Then, using the photoresist pattern as an ion implantation mask, the semiconductor layer 1A3 is doped with, for example, boron at an acceleration energy of about 10 keV and a dose of 2 × 1.
The implantation is performed at about 0 ¹² cm ^-2 to adjust the Vth of the nMOS. Thereafter, using the photoresist pattern as an ion implantation mask, the semiconductor layer 1A3 is doped with, for example, boron at an acceleration energy of about 130 keV and a dose of 1 × 10 ¹⁴ c.
^{Implanted at} about m ⁻² to form a semiconductor region 2b for the back gate
g1 (2bg2).

Next, by subjecting the SOI substrate 1A to an oxidation process, as shown in FIG.
A gate insulating film 7i made of, for example, a silicon oxide film or the like having a thickness of about 8 nm is formed on the main surface 3. Then, SO
On the main surface of the I-substrate 1A, for example, the phosphorus concentration is 1 × 10 ²⁰ c
After depositing a low-resistance polysilicon film having a thickness of about 0.3 μm with a thickness of about m ³ by a CVD method or the like, this is patterned by a dry etching method or the like to form a gate electrode 8g.

Next, after forming a photoresist pattern on the main surface of SOI substrate 1A so as to cover the n-well formation region and expose the p-well formation region, the photoresist pattern and gate electrode 8g are formed. For example, arsenic is applied to the semiconductor layer 1A3 as an ion implantation mask at an acceleration energy of about 10 keV and a dose of 2 × 10 ¹⁵ c.
Implantation is performed at about m ⁻² to form a pair of semiconductor regions 6nd of the nMOS Qn1 (Qn2). Subsequently, after the photoresist pattern is removed by ashing, SOI
On the main surface of the substrate 1A, the p-well formation region is covered, and
A photoresist pattern is formed such that an n-well formation region is exposed, and the semiconductor layer 1 is formed by using the photoresist pattern and the gate electrode 8g as an ion implantation mask.
For example, boron is implanted into A3 at an acceleration energy of about 10 keV and a dose of about 2 × 10 ¹⁵ cm ⁻² , and the pMO
A pair of semiconductor regions 6pd of SQp1 (Qp2) are formed. Then, for example, 850 is applied to the SOI substrate 1A.
The implanted impurities are activated by performing a heat treatment at about 10 ° C. for about 10 minutes.

Next, as shown in FIG. 14, an insulating film made of, for example, a silicon oxide film having a thickness of about 0.9 μm is deposited on the main surface of the SOI substrate 1A by a CVD method or the like. The interlayer insulating film 11 is formed by flattening by about 0.4 μm by CMP. Subsequently, the connection hole 1 is formed such that a part of the semiconductor regions 6nd and 6pd is exposed.
2a, connection hole 1 such that a part of gate electrode 8g is exposed
2b, connection hole 12c such that a part of p-well 3pw1 (3pw2) is exposed (corresponding to connection holes 5a1, 5a2)
And a semiconductor region 2bg1 (2bg
A connection hole 12d such that a part of 2) is exposed is formed by a photolithography technique and a dry etching technique. Then, on the interlayer insulating film 11 and the connection holes 12a to
After depositing a conductive film made of, for example, tungsten, aluminum or an aluminum-silicon-copper alloy by sputtering or CVD in 12d, the conductive film is patterned by photolithography and dry etching. One-layer wiring 1
Form 3 Subsequent steps are a normal manufacturing process of the semiconductor integrated circuit device, and the description is omitted.

As described above, according to the first embodiment, the following effects can be obtained.

(1) Since the deep isolation portion 4A1 is formed along the outer periphery of the semiconductor chip 1, the well of the semiconductor layer 1A3 and the semiconductor regions 2bg1, 2bg2 for the back gate are separated from the semiconductor chip 1 or the semiconductor integrated circuit device. Wafer (SOI wafer) during the manufacturing process (inspection process)
Can be prevented from conducting through moisture, contaminants, and the like attached to the side surface of the substrate.

(2) Since the deep isolation portion 4A2 is formed so as to surround the input / output circuit formation region I / O where the drive voltage is high, the circuit region where the drive voltage is relatively high and the circuit region where the drive voltage is relatively low are formed. In this way, it is possible to prevent electrical adverse effects from occurring through the semiconductor layer 1A3.

(3). By forming the deep isolation portion 4A3 in the boundary region between the p wells 3pw1, 3pw2 and the n wells 3nw1, 3nw2, the well junction capacitance can be reduced.

(4) Since the deep isolation portion 4A3 is formed in the boundary region between the p-wells 3pw1, 3pw2 and the n-wells 3nw1, 3nw2, latch-up can be prevented.

(5) Since the deep isolation region 4A4 is formed in the wiring region L, it is possible to reduce the wiring capacitance parasitic on the wiring formed on the main surface of the SOI substrate 1A.

(6) Since the mark M is formed by the deep isolation region 4A5, the reflected light from the silicon-silicon oxide film, which interferes with inspection and measurement using light, can be reduced. It is possible to improve the detection accuracy of the mark M at the time of inspection and measurement.

(7) The above (1), (2) and (4) make it possible to improve the reliability of the semiconductor integrated circuit device.

(8) According to the above (3) and (4), the operation speed of the semiconductor integrated circuit can be improved.

(9) According to the above (6), the inspection accuracy and the measurement accuracy can be improved, so that the yield of the semiconductor integrated circuit device can be improved.

(Embodiment 2) FIG. 15 is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. FIG. 2 is an overall plan view of a semiconductor chip included in the integrated circuit device.

The second embodiment describes a structure whose main purpose is to separate wells of different conductivity types. FIG. 15 shows that the p-wells 3pw1 and 3pw2 are connected to the deep separation portion 4A6.
(4A) shows a case where the image is surrounded. p well 3p
w1 and 3pw2 are each surrounded by a separate deep separation part 4A6. FIG. 16 shows n-wells 3nw1, 3n
This shows a case where w2 is surrounded by a deep separation portion 4A7 (4A). In this case, both n-wells 3nw1 and 3nw2 are surrounded by one deep separating portion 4A7. Also,
The deep isolation portion 4A4 of the wiring region L
It is integrated with.

According to the second embodiment, the effects (3) to (9) of the first embodiment can be obtained.

(Embodiment 3) FIG. 17 is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device according to another embodiment of the present invention.

Embodiment 3 describes a structure mainly intended to isolate a circuit formation region where a driving voltage is relatively high. As shown in FIG. 17, the deep separation part 4A8 (4
A) is formed so as to surround the input / output circuit formation region where the drive voltage is relatively high. In this case, wells of different conductivity types described in the second embodiment may be separated by a deep separation portion.

According to the third embodiment, the effects (2) and (7) of the first embodiment can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the first to third embodiments, and the present invention is not limited thereto. It goes without saying that various changes can be made.

For example, in the first to third embodiments,
The case where the deep isolation portion is provided along the outer periphery of the semiconductor chip has been described. However, the present invention is not limited to this. For example, the separation may be performed by providing an n-type semiconductor region along the outer periphery of the semiconductor chip. May be. The n-type semiconductor region is formed, for example, in a pattern having a width of about several μm in a plane, and impurities (for example, phosphorus or arsenic) forming the n-type semiconductor region extend from the main surface of the semiconductor layer to the upper surface of the buried insulating layer. It is formed so as to reach.

In the first embodiment, the case where the deep isolation portion is provided on the outer periphery of the semiconductor chip has been described. However, the present invention is not limited to this.
You may make it provide a deep isolation | separation part along the outer periphery of a wafer (semiconductor wafer).

In the above description, the case where the invention made by the present inventor is mainly applied to a logic circuit which is the field of application as the background has been described. However, the present invention is not limited to this, and various applications are possible. DRA
M (Dynamic Random Access Memory), SRAM (Stati
c Random Access Memory) or Flash Memory (EEPROM; Electrically Erasable Programmable)
ROM), etc.
The present invention can be applied to a memory-logic mixed circuit in which the memory circuit and the logic circuit are mixed, and further to an analog-digital mixed circuit in which an analog circuit and a digital circuit are mixed.

In this case, the structures described in the first to third embodiments may be applied to the memory circuit, the memory-logic mixed circuit, and the analog-digital mixed circuit. The portions may be formed at the following planar positions, for example.

First, in the above-mentioned memory circuit, a deep isolation portion may be formed in a boundary region between the memory cell region and the peripheral circuit region, for example, so that both are electrically separated from each other in the semiconductor layer. In this case, noise can be prevented from propagating from the peripheral circuit region to the memory cell region through the semiconductor layer, so that the reliability of data read and write operations can be improved.

In particular, a flash memory (EEPRO)
In M), for example, a structure may be employed in which the formation region of the high voltage generation circuit is surrounded by a deep isolation portion and is electrically separated from other regions in the semiconductor layer for element formation. In this case, the same effect as in the third embodiment can be obtained.

The memory-logic mixed circuit may have a structure in which a deep isolation portion is formed in a boundary region between a memory cell region and a logic circuit region, for example, so that both are electrically separated from each other in a semiconductor layer. . In this case, since noise can be prevented from propagating from the logic circuit region to the memory cell region through the semiconductor layer, the reliability of data read and write operations can be improved. Note that this structure may be combined with the structure in the case of only the memory circuit.

Further, in the analog-digital mixed circuit, for example, a structure in which both are electrically separated from each other in the semiconductor layer by forming a deep isolation portion in a boundary region between the digital circuit region and the analog circuit region may be employed.
In this case, since noise can be prevented from propagating through the semiconductor layer between the analog circuit region and the digital circuit region, reliability of circuit operation in each of the analog circuit and the digital circuit can be improved.

Incidentally, each structure of the memory circuit, the memory-logic mixed circuit and the analog-digital mixed circuit may be appropriately combined with the structures of the first to third embodiments.

[0086]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, since the deep isolation portion is formed to extend along the outer periphery of the semiconductor chip, the semiconductor layer and the supporting substrate are formed in a semiconductor chip or a semiconductor integrated circuit device manufacturing process (inspection). Semiconductor wafer (S)
It is possible to prevent conduction through moisture, contaminants, and the like attached to the side surface of the OI wafer).

(2) According to the present invention, a deep isolation portion is formed so as to electrically isolate circuits having different drive voltages from each other. This makes it possible to prevent the circuit region from being adversely affected by electric through the semiconductor layer.

(3) According to the present invention, a deep isolation portion is formed so that semiconductor regions of different conductivity types formed in a semiconductor layer are electrically isolated from each other, thereby reducing the well junction capacitance. It becomes possible.

(4) According to the present invention, a latch-up is prevented by forming a deep isolation portion so that semiconductor regions of different conductivity types formed in a semiconductor layer are electrically isolated from each other. Becomes possible.

(5) According to the present invention, since the deep isolation region is formed in the wiring region, it is possible to reduce the wiring capacitance that is parasitic on the wiring formed on the main surface of the SOI substrate.

(6) According to the present invention, since the mark is formed by the deep isolation region, the reflected light from the silicon-silicon oxide film, which hinders inspection and measurement using light, can be reduced. Therefore, it is possible to improve the mark detection accuracy during the inspection and measurement.

(7) According to the above (1), (2) and (4), the reliability of the semiconductor integrated circuit device can be improved.

(8) According to the above (3) and (4), the operation speed of the semiconductor integrated circuit can be improved.

(9) According to the above (6), the inspection accuracy and the measurement accuracy can be improved, so that the yield of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG. 1;

FIG. 3 is a sectional view taken along line BB of FIG. 1;

FIG. 4 is a sectional view taken along line CC of FIG. 1;

FIG. 5 is a modification of the present embodiment and is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device.

FIG. 6 is a sectional view taken along line AA of FIG. 5;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 or 5 during a manufacturing step thereof;

8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 or FIG. 5 during a manufacturing step following that of FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 or 5 during a manufacturing step following that of FIG. 8;

10 is a diagram showing the semiconductor integrated circuit device shown in FIG. 1 or FIG. 5;
FIG. 14 is a cross-sectional view of a main part in a manufacturing step following the step shown in FIG.

FIG. 11 shows the semiconductor integrated circuit device of FIG. 1 or FIG.
FIG. 10 is a cross-sectional view of a main part of another manufacturing step following the step 0.

FIG. 12 is a diagram of the semiconductor integrated circuit device of FIG. 1 or FIG. 5;
FIG. 2 is a cross-sectional view of a main part in a manufacturing step following FIG.

FIG. 13 shows the semiconductor integrated circuit device of FIG. 1 or FIG. 5;
FIG. 3 is a cross-sectional view of a main part in a manufacturing step following Step 2.

FIG. 14 shows the semiconductor integrated circuit device of FIG. 1 or 5;
FIG. 4 is a cross-sectional view of a main part in a manufacturing step following FIG. 3;

FIG. 15 is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 16 is a modification of the second embodiment and is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device.

FIG. 17 is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 semiconductor chip 1A SOI substrate 1A1 support substrate 1A2 buried insulating layer 1A3 semiconductor layer 2bg1, 2bg2 semiconductor region 3nw1, 3nw2 n well 3pw1, 3pw2 p well 4A deep separation portion 4A1 deep separation portion 4A3 deep separation portion A4 deep separation portion Isolation portion 4A5 Deep isolation portion 4A6 Deep isolation portion 4A7 Deep isolation portion 4A8 Deep isolation portion 4B Shallow isolation portion 5a1, 5a2, 5b1, 5b2 Connection hole 6pd Semiconductor region 6nd Semiconductor region 7i Gate insulating film 8g Gate electrode 9 Insulating film 10 Photoresist Pattern 11 Interlayer insulating film 12a to 12d Connection hole 13 First layer wiring I / O Input / output circuit forming area LG Logic circuit forming area L Wiring area M Mark Qn1, Qn2 n-channel type MOS • FET Qp1, Qp2 p-channel MOS FET

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 27/12

Claims (10)

[Claims] 1. A semiconductor integrated circuit device having a semiconductor chip composed of an SOI substrate in which a semiconductor layer is provided on a supporting substrate via an insulating layer, wherein the semiconductor layer is formed on a main surface of the semiconductor layer from a main surface thereof. A relatively shallow isolation portion reaching the middle depth position, and a relatively deep isolation portion reaching the insulating layer from the main surface of the semiconductor layer,
2. The semiconductor integrated circuit device according to claim 1, wherein said deep isolation portion extends along an outer periphery of said semiconductor chip. 2. A semiconductor integrated circuit device having a semiconductor chip composed of an SOI substrate in which a semiconductor layer is provided on a supporting substrate with an insulating layer interposed therebetween, wherein the semiconductor layer is provided on the semiconductor layer from a main surface thereof. A relatively shallow isolation portion reaching the middle depth position, and a relatively deep isolation portion reaching the insulating layer from the main surface of the semiconductor layer,
A semiconductor integrated circuit device, wherein the deep isolation portion is provided so that circuit regions having different driving voltages are electrically isolated from each other. 3. A semiconductor integrated circuit device having a semiconductor chip composed of an SOI substrate in which a semiconductor layer is provided on a supporting substrate with an insulating layer interposed therebetween, wherein the semiconductor layer is provided on the semiconductor layer from a main surface thereof. A relatively shallow isolation portion reaching the middle depth position, and a relatively deep isolation portion reaching the insulating layer from the main surface of the semiconductor layer,
A semiconductor integrated circuit device, wherein the deep isolation portion is provided so that semiconductor regions having different conductivity types formed in the semiconductor layer are electrically separated from each other. 4. A semiconductor integrated circuit device having a semiconductor chip composed of an SOI substrate in which a semiconductor layer is provided on a supporting substrate with an insulating layer interposed therebetween, wherein the semiconductor layer is formed on a main surface thereof from the semiconductor layer. A relatively shallow isolation portion reaching the middle depth position, and a relatively deep isolation portion reaching the insulating layer from the main surface of the semiconductor layer,
A semiconductor integrated circuit device, wherein the deep isolation portion is provided in the semiconductor layer so as to cover a wiring region where an integrated circuit element is not formed. 5. A semiconductor integrated circuit device having a semiconductor chip composed of an SOI substrate in which a semiconductor layer is provided on a supporting substrate with an insulating layer interposed therebetween, wherein the semiconductor layer is formed on the semiconductor layer from a main surface thereof. A relatively shallow isolation portion reaching the middle depth position, and a relatively deep isolation portion reaching the insulating layer from the main surface of the semiconductor layer,
A semiconductor integrated circuit device, wherein a mark is formed by the deep separation part. 6. A semiconductor integrated circuit device having a semiconductor chip composed of an SOI substrate in which a semiconductor layer is provided on a support substrate via an insulating layer, wherein the semiconductor layer is formed on a main surface of the semiconductor layer from a main surface thereof. A relatively shallow isolation portion reaching a depth position in the middle of the semiconductor layer, and a relatively deep isolation portion reaching the insulating layer from the main surface of the semiconductor layer. And another one of the deep isolation portions is provided so that circuit regions having different driving voltages are electrically isolated from each other, and another one of the deep isolation portions is formed in the semiconductor layer. Semiconductor regions having different conductivity types are provided so as to be electrically separated from each other, and another one of the deep isolation portions is provided in the semiconductor layer so as to cover a wiring region where an integrated circuit element is not formed, and The deep separation The semiconductor integrated circuit device characterized by the formation of the click. 7. A semiconductor integrated circuit device having a semiconductor chip composed of an SOI substrate in which a semiconductor layer is provided on a support substrate via an insulating layer, wherein the semiconductor layer is provided on a main surface of the semiconductor layer from a main surface thereof. A relatively shallow isolation portion reaching a depth position in the middle of the semiconductor device, and a relatively deep isolation portion reaching the insulating layer from the main surface of the semiconductor layer, wherein one of the deep isolation portions is a circuit region having a different driving voltage. Are provided so as to be electrically separated from each other, and another one of the deep separation portions is provided so that semiconductor regions having different conductivity types formed in the semiconductor layer are electrically separated from each other. Semiconductor integrated circuit device. 8. A method of manufacturing a semiconductor integrated circuit device having an SOI substrate in which a semiconductor layer is provided on a supporting substrate with an insulating layer interposed therebetween, wherein (a) the semiconductor layer includes Forming a relatively shallow isolation portion reaching a depth position in the middle of (b), and (b) forming a relatively deep isolation portion reaching the insulating layer from the main surface of the semiconductor layer; Forming a predetermined integrated circuit element in an element formation region surrounded by the shallow isolation section and the deep isolation section, and forming the deep isolation section along the outer periphery of the semiconductor chip; Forming the deep isolation portion so that circuit regions having different driving voltages are electrically isolated from each other;
Forming the deep isolation portion so that semiconductor regions having different conductivity types formed in the semiconductor layer are electrically isolated from each other; and forming the deep isolation portion in a wiring region where an integrated circuit element is not formed in the semiconductor layer. A method of manufacturing a semiconductor integrated circuit device, comprising: at least one of a step of forming a cover and a step of forming a mark by the deep isolation portion. 9. A method for manufacturing a semiconductor integrated circuit device having an SOI substrate in which a semiconductor layer is provided on a supporting substrate with an insulating layer interposed therebetween, wherein (a) the semiconductor layer includes Forming a relatively shallow separation part reaching a depth position in the middle of the step and a relatively deep separation part reaching an insulating layer from the main surface of the semiconductor layer; and (b) forming a mark by the deep separation part. Detecting the reflected light of the light applied to the mark; and (c) forming a predetermined integrated circuit element in an element formation region surrounded by the shallow separation part and the deep separation part. A method for manufacturing a semiconductor integrated circuit device, comprising: 10. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein, during the step of forming the predetermined integrated circuit element, a step of forming a gate insulating film on the semiconductor layer; A method for manufacturing a semiconductor integrated circuit device, comprising: forming a gate electrode thereon; and forming semiconductor regions for source and drain on both sides of the gate electrode in the semiconductor layer.