JP2012028790A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which avoids decrease in an operation speed and increase in power consumption due to increase in pn junction capacitance composed of a source/drain region in a MOS transistor of a constant-voltage logic circuit unit.SOLUTION: The nonvolatile semiconductor storage device comprises a first MOS transistor included in a memory cell array part and a second MOS transistor included in a constant-voltage logic circuit unit situated next to the first MOS transistor on an SOI substrate 1. A silicon layer 4 included in the first MOS transistor is thicker than a silicon layer 4 included in the second MOS transistor.

Description

  The present invention relates to the structure of a semiconductor device including a nonvolatile semiconductor memory device, and more particularly to the structure of a flash memory using an SOI (Silicon On Insulator) substrate. The present invention also relates to the structure of a semiconductor integrated circuit such as an LSI in which the nonvolatile semiconductor memory device is formed.

  FIG. 46 is a cross-sectional view schematically showing the structure of a memory cell transistor in a flash memory using a bulk substrate (meaning a normal semiconductor substrate that is not an SOI substrate). A pair of source region 102s and drain region 102d are formed in the upper surface of the silicon substrate 101 so as to be separated from each other. A stacked structure in which a gate oxide film 103, a floating gate 104, an insulating film 105, and a control gate 106 are stacked in this order is formed on the upper surface of the silicon substrate 101 at a portion sandwiched between the source region 102s and the drain region 102d. A side wall 107 made of an insulating film is formed on the side surface of the laminated structure.

  In the data write operation, for example, a high voltage is applied to the drain region 102d and the control gate 106 with a ground potential applied to the source region 102s. As a result, hot electrons generated in the high electric field region near the channel region and the drain region 102 d are injected into the floating gate 104.

  FIG. 47 is a cross-sectional view schematically showing the structure of a memory cell transistor in a flash memory using an SOI substrate. The SOI substrate 108 has a stacked structure in which a silicon substrate 109, a BOX (Buried OXide) layer 110, and a silicon layer 111 are stacked in this order. In the silicon layer 111, a complete isolation type element isolation insulating film 112 that reaches the upper surface of the BOX layer 110 from the upper surface of the silicon layer 111 is selectively formed. In the element formation region defined by the element isolation insulating film 112, a pair of a source region 102s and a drain region 102d are formed apart from each other. The bottom surfaces of the source region 102 s and the drain region 102 d reach the top surface of the BOX layer 110.

  A gate oxide film 103, a floating gate 104, an insulating film 105, and a control gate 106 are stacked in this order on the upper surface of the body layer, that is, the portion of the silicon layer 111 sandwiched between the source region 102s and the drain region 102d. A stacked layer structure is formed, and a sidewall 107 made of an insulating film is formed on a side surface of the stacked structure.

  FIG. 48 is a circuit diagram showing a part of the configuration of the memory cell array of the flash memory. FIG. 48 shows only the configuration of a total of 15 memory cells of 5 rows × 3 columns. Each memory cell includes a memory cell transistor shown in FIG. For memory cells belonging to the same row, the control gate CG of each memory cell transistor is connected to a common word line. For example, the control gate CG of each memory cell transistor included in the memory cells MC11 to MC13 is commonly connected to the word line WL101.

  For the memory cells belonging to the same row, the source S of each memory cell transistor is connected to a common source line. For example, the source S of each memory cell transistor included in the memory cells MC11 to MC13 is commonly connected to the source line SL101. The source lines SL101 to SL105 in each row are connected to a common source line SL100.

  For memory cells belonging to the same column, the drain D of each memory cell transistor is connected to a common bit line. For example, the drain D of each memory cell transistor included in the memory cells MC11 to MC51 is commonly connected to the bit line BL101.

  FIG. 49 is a top view showing a structure of a conventional nonvolatile semiconductor memory device having the configuration of the memory cell array shown in FIG. However, FIG. 49 schematically shows the arrangement relationship of a floating gate, a word line (also serving as a control gate), a source line, and an element isolation insulating film. For example, the floating gates 411, 412, and 421 shown in FIG. 49 correspond to the floating gates FG of the memory cell transistors provided in the memory cells MC11, MC12, and MC21 shown in FIG.

  For example, the source region Sa shown in FIG. 49 corresponds to each source S of the memory cell transistor included in each of the memory cells MC11 and MC21 shown in FIG. 48, and the source region Sd shown in FIG. Correspond to each source S of the memory cell transistor included in each of the memory cells MC31 and MC41 shown in FIG.

  For example, the drain region Da shown in FIG. 49 corresponds to each drain D of the memory cell transistor included in each of the memory cells MC21 and MC31 shown in FIG. 48, and the drain region Dd shown in FIG. Corresponds to each drain D of the memory cell transistor provided in each of the memory cells MC41 and MC51 shown in FIG.

  Referring to FIG. 49, source lines SL101 and SL102 include source regions Sa to Sc, source lines SL103 and SL104 include source regions Sd to Sf, and source line SL105 includes source regions Sg to Si. The source lines SL101 to SL105 are formed by providing regions between the rows where the element isolation insulating film 112 is not formed.

  50 is a cross-sectional view showing a cross-sectional structure at a position along line segment X100 shown in FIG. The source region Sa and the source region Sb are separated from each other by a complete isolation type element isolation insulating film 112.

  However, such conventional nonvolatile semiconductor memory devices have the following problems. This problem will be described with reference to FIG. As described above, in the data write operation, a high voltage is applied to the drain region 102d and the control gate 106 with the ground potential applied to the source region 102s. At this time, a large number of electron-hole pairs are generated in the vicinity of the channel region and the drain region 102d due to the impact ionization phenomenon.

  In a conventional nonvolatile semiconductor memory device using an SOI substrate, holes are accumulated in the body region because the body region is in an electrically floating state. Therefore, when the body potential rises, the parasitic bipolar transistor including the source region 102s, the drain region 102d, and the body region is driven, and as a result, a parasitic bipolar current flows from the source region 102s toward the drain region 102d, A malfunction occurs. Thus, according to the conventional nonvolatile semiconductor memory device, the parasitic bipolar transistor is driven by the accumulation of holes in the body region due to the body region being in an electrically floating state, There was a problem that malfunction occurred.

  The present invention has been made to solve such a problem. By avoiding the accumulation of holes in the body region, a nonvolatile operation that does not cause malfunction due to the driving of a parasitic bipolar transistor does not occur. And a reduction in operating speed and an increase in power consumption of the semiconductor device due to an increase in the pn junction capacitance formed by the source / drain regions of the MOS transistors in the constant voltage logic circuit portion are obtained. Is the main purpose.

  In a semiconductor device according to the present invention, a semiconductor layer is provided between an SOI substrate having a structure in which a semiconductor substrate, an insulating layer, and a semiconductor layer are stacked in this order, and the insulating layer formed in the main surface of the semiconductor layer. A first MOS transistor formed in the semiconductor layer, and a second MOS transistor formed adjacent to the first MOS transistor in the semiconductor layer. The semiconductor layer of the first MOS transistor is thicker than the semiconductor layer of the second MOS transistor.

  According to the present invention, since the semiconductor layer of the second MOS transistor is thin, the source / drain region of the first MOS transistor is formed so as not to reach the upper surface of the insulating layer, and the source of the second MOS transistor Forming the drain region so as to reach the upper surface of the insulating layer can be performed by the same ion implantation process. When the source / drain region of the second MOS transistor reaches the upper surface of the insulating layer, an increase in the pn junction capacitance formed by the second MOS transistor is suppressed, and a decrease in operating speed and an increase in power consumption of the semiconductor device can be avoided.

1 is a cross-sectional view showing a structure of a memory cell transistor in a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing a part of the configuration of the memory cell array in the nonvolatile semiconductor memory device according to the first embodiment of the present invention. 1 is a top view showing a structure of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 6 is a top view showing a structure of a nonvolatile semiconductor memory device according to a modification of Embodiment 1 of the present invention. FIG. 5 is a cross-sectional view showing a cross-sectional structure at a position along a line segment X1 shown in FIG. 4. FIG. 5 is a cross-sectional view showing a cross-sectional structure at a position along a line segment X2 shown in FIG. 4. FIG. 5 is a cross-sectional view showing a cross-sectional structure at a position along a line segment X3 shown in FIG. FIG. 5 is a cross-sectional view showing a cross-sectional structure at a position along a line segment X4 shown in FIG. It is sectional drawing which shows the structure of the non-volatile semiconductor memory device concerning Embodiment 2 of this invention. It is sectional drawing which shows the structure of the non-volatile semiconductor memory device concerning Embodiment 2 of this invention. It is sectional drawing which shows the structure of the non-volatile semiconductor memory device concerning Embodiment 3 of this invention. FIG. 16 is a top view showing a structure of a nonvolatile semiconductor memory device according to a modification of the third embodiment. It is sectional drawing which shows the structure of the semiconductor integrated circuit which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the structure of the semiconductor integrated circuit which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the structure of the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 1st manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 1st manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 1st manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 1st manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 2nd manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 2nd manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 3rd manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 3rd manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 3rd manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 4th manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 4th manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 4th manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 4th manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the 4th manufacturing method of an element isolation insulating film in order of a process regarding the semiconductor integrated circuit which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the other structure of the semiconductor integrated circuit based on Embodiment 6 of this invention. FIG. 31 is a cross-sectional view showing a method of manufacturing the semiconductor integrated circuit shown in FIG. 30 in order of processes. FIG. 31 is a cross-sectional view showing a method of manufacturing the semiconductor integrated circuit shown in FIG. 30 in order of processes. FIG. 31 is a cross-sectional view showing a method of manufacturing the semiconductor integrated circuit shown in FIG. 30 in order of processes. FIG. 31 is a cross-sectional view showing a method of manufacturing the semiconductor integrated circuit shown in FIG. 30 in order of processes. It is a top view which shows typically the structure of the semiconductor integrated circuit which concerns on Embodiment 7 of this invention. It is sectional drawing which shows typically the cross-section of the semiconductor integrated circuit which concerns on Embodiment 7 of this invention. It is a top view which shows typically the structure of the semiconductor integrated circuit which concerns on the 1st modification of Embodiment 7 of this invention. It is a top view which shows typically the structure of the semiconductor integrated circuit which concerns on the 2nd modification of Embodiment 7 of this invention. It is sectional drawing which shows typically the structure of the semiconductor integrated circuit which concerns on Embodiment 8 of this invention. It is sectional drawing which shows typically the structure of the semiconductor integrated circuit which concerns on Embodiment 9 of this invention. It is sectional drawing which shows the structure of the semiconductor integrated circuit based on Embodiment 10 of this invention. It is sectional drawing which shows the structure of the semiconductor integrated circuit based on Embodiment 10 of this invention. It is sectional drawing which shows the structure of the semiconductor integrated circuit based on Embodiment 10 of this invention. FIG. 29 is a circuit diagram showing a part of the configuration of the memory cell array in the nonvolatile semiconductor memory device according to Embodiment 11 of the present invention. 24 is a timing chart showing waveforms of drive signals applied to a word line and a body line in the nonvolatile semiconductor memory device according to the eleventh embodiment of the present invention. It is sectional drawing which shows typically the structure of the memory cell transistor of the flash memory using a bulk substrate. It is sectional drawing which shows typically the structure of the memory cell transistor of the conventional non-volatile semiconductor memory device. FIG. 10 is a circuit diagram showing a part of the configuration of a memory cell array extracted from a conventional nonvolatile semiconductor memory device. It is a top view which shows the structure of the conventional non-volatile semiconductor memory device. FIG. 50 is a cross-sectional view showing a cross-sectional structure at a position along line segment X100 shown in FIG. 49.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the structure of a memory cell transistor in a flash memory according to Embodiment 1 of the present invention. The SOI substrate 1 has a stacked structure in which a silicon substrate 2, a BOX layer 3, and a silicon layer 4 are stacked in this order. In the upper surface of the silicon layer 4, a partial trench isolation type (hereinafter simply referred to as “partial isolation type”) element isolation insulating film 5 whose bottom surface does not reach the upper surface of the BOX layer 3 is selectively formed. Yes. Further, in the element formation region defined by the element isolation insulating film 5, a source region and a drain region (not shown in FIG. 1) forming a pair with the body region 70 interposed therebetween are formed in the upper surface of the silicon layer 4. ing. On the upper surface of the silicon layer 4 where the body region 70 is formed, a stacked structure is formed in which a gate oxide film 6, a floating gate 7, an insulating film 8, and a control gate 9 are stacked in this order. Yes. A sidewall 11 (not shown in FIG. 1) made of an insulating film is formed on the side surface of the laminated structure, thereby forming a gate electrode structure.

  As described above, by using the partial isolation type element isolation insulating film 5 instead of the complete isolation type element isolation insulating film as the element isolation insulating film for isolating adjacent memory cells, the element isolation insulation is achieved. The potential of the body region 70 can be fixed from the outside through a portion of the silicon layer 4 located between the bottom surface of the film 5 and the top surface of the BOX layer 3. Therefore, the malfunction due to the accumulation of holes in the body region 70 can be avoided, and the source-drain breakdown voltage can be increased. As a result, a memory cell transistor that can execute a data write operation and a read operation using a high voltage can be obtained.

  Further, not only in the memory cell array part in which the memory cells are formed but also in the peripheral circuit part in which the peripheral circuit such as the sense amplifier is formed, by adopting the partial isolation type element isolation insulating film 5, similarly. The breakdown voltage between the source and the drain can be increased.

  FIG. 2 is a circuit diagram showing a part of the configuration of the memory cell array of the flash memory. FIG. 2 shows only the configuration of a total of 15 memory cells of 5 rows × 3 columns. Here, the “row” of the memory cell array refers to the “row” when the direction perpendicular to the direction in which the source and drain regions of the memory cell transistors are aligned is defined as the “row direction” with reference to FIG. Means. A “column” of the memo cell array means a “column” when the direction in which the source region and the drain region of the memory cell transistor are aligned is defined as “column direction” with reference to FIG. 3 described later. Each memory cell includes the memory cell transistor shown in FIG. For memory cells belonging to the same row, the control gate CG of each memory cell transistor is connected to a common word line. For example, the control gate CG of each memory cell transistor included in the memory cells MC11 to MC13 is commonly connected to the word line WL1.

  For the memory cells belonging to the same row, the source S of each memory cell transistor is connected to a common source line. For example, the source S of each memory cell transistor included in the memory cells MC11 to MC13 is commonly connected to the source line SL1. The source lines SL1 to SL5 in each row are connected to a common source line SL0.

  For memory cells belonging to the same column, the drain D of each memory cell transistor is connected to a common bit line. For example, the drain D of each memory cell transistor included in the memory cells MC11 to MC51 is commonly connected to the bit line BL1.

  FIG. 3 is a top view showing the structure of the nonvolatile semiconductor memory device according to the first embodiment having the configuration of the memory cell array shown in FIG. However, FIG. 3 schematically shows the arrangement relationship of the floating gate, the word line (also serving as the control gate), the source line, and the element isolation insulating film. For example, the floating gates 711, 712, and 721 shown in FIG. 3 correspond to the floating gates FG of the memory cell transistors provided in the memory cells MC11, MC12, and MC21 shown in FIG.

  Further, for example, the source region Sa shown in FIG. 3 corresponds to each source S of the memory cell transistor included in each of the memory cells MC11 and MC21 shown in FIG. 2, and the source region Sd shown in FIG. Correspond to each source S of the memory cell transistor included in each of the memory cells MC31 and MC41 shown in FIG.

  Further, for example, the drain region Da shown in FIG. 3 corresponds to each drain D of the memory cell transistor included in each of the memory cells MC21 and MC31 shown in FIG. 2, and the drain region Dd shown in FIG. Corresponds to each drain D of the memory cell transistor provided in each of the memory cells MC41 and MC51 shown in FIG.

  Referring to FIG. 3, source lines SL1 and SL2 include source regions Sa to Sc, source lines SL3 and SL4 include source regions Sd to Sf, and source line SL5 includes source regions Sg to Si. The element isolation insulating film 5 is formed to extend in a strip shape between each column so as to isolate memory cells belonging to different columns. In FIG. 3, the hatched area is hatched in the region where the element isolation insulating film 5 is formed.

  All the source regions belonging to the same row are electrically connected to each other via a portion of the silicon layer 4 located between the bottom surface of the element isolation insulating film 5 and the top surface of the BOX layer 3. For example, the source regions Sa to Sc are electrically connected via the silicon layer 4 in the above portion, thereby configuring strip-like source lines SL1 and SL2 extending in the row direction.

  As described above, in the nonvolatile semiconductor memory device according to the first embodiment, the source regions adjacent to each other in the row direction are between the bottom surface of the partial isolation type element isolation insulating film 5 and the top surface of the BOX layer 3. Are electrically connected to each other via a portion of the silicon layer 4, thereby forming source lines SL <b> 1 to SL <b> 5. Therefore, when forming the source lines SL1 to SL5, it is not necessary to provide a region in which the element isolation insulating film 5 is not formed between the rows. Therefore, compared with the conventional nonvolatile semiconductor memory device shown in FIG. The area of the cell array portion can be reduced.

  FIG. 4 is a top view showing the structure of the nonvolatile semiconductor memory device according to the modification of the first embodiment of the present invention, corresponding to FIG. The non-volatile semiconductor memory device shown in FIG. 4 is based on the non-volatile semiconductor memory device shown in FIG. 3, and element isolation between source regions (for example, source region Sa and source region Sb) adjacent to each other in the row direction is performed. The insulating film 5 is removed and the portion is used as a window for introducing impurities, thereby forming an impurity introducing region 10 to be described later in the silicon layer 4 exposed by removing the element isolation insulating film 5 It is.

  FIGS. 5-8 is sectional drawing which shows the cross-sectional structure in the position along the line segments X1-X4 shown in FIG. 4, respectively. Referring to FIG. 5, body region B11 and body region B12 are electrically connected to each other through a portion of silicon layer 4 located between the bottom surface of element isolation insulating film 5 and the top surface of BOX layer 3. Has been. As a result, by applying a voltage to the silicon layer 4 from the outside, the potentials of the body regions B11 and B12 can be fixed to the same potential.

  Referring to FIG. 6, a recess formed by removing element isolation insulating film 5 is formed in the upper surface of silicon layer 4 located between source region Sd and source region Se. In the silicon layer 4 located between the source region Sd and the source region Se in the portion exposed by the removal of the element isolation insulating film 5, an impurity introduction region 10 having the same conductivity type as the source regions Sd and Se is formed. Is formed.

  Referring to FIG. 8, element isolation insulating film 5 between word line WL3 and word line WL4 is removed. An impurity introduction region 10 is formed in a portion of the silicon layer 4 exposed by removing the element isolation insulating film 5.

  After the memory cell transistor is formed, the impurity introduction region 10 is formed by removing the element isolation insulating film 5 to form the recess, and thereafter, impurities having the same conductivity type as the source region are removed from the bottom surface of the recess by ion implantation. It is formed by introducing it into the silicon layer 4. In removing the element isolation insulating film 5, as shown in FIGS. 6 and 8, it may be completely removed until the underlying silicon layer 4 is exposed or only a part thereof may be removed. Good.

  As shown in FIGS. 6 and 8, the impurity introduction region 10 is desirably formed so that the bottom surface thereof reaches the top surface of the BOX layer 3. As a result, the occurrence of a pn junction capacitance between the bottom surface of the impurity introduction region 10 and the silicon layer 4 can be avoided, and the parasitic capacitance of the source line can be reduced, so that the operation speed is increased and the power consumption is reduced. You can plan.

  Referring to FIG. 7, source regions Sa, Sd, Sg and drain regions Da, Dd reach the upper surface of BOX layer 3. Here, “the source region and the drain region reach the upper surface of the BOX layer” means that the impurity diffusion region itself of the source region and the drain region reaches the upper surface of the BOX layer (FIG. 7), and the source region and the drain region. The depletion layer generated at the pn junction between the region and the silicon layer includes both of the modes reaching the upper surface of the BOX layer. The same applies to this point hereinafter. By forming the source region and the drain region so as to reach the upper surface of the BOX layer 3, the pn junction capacitance generated between the source region and the drain region and the silicon layer 4 can be reduced, and the parasitic capacitance of the source line can be reduced. Therefore, the operation speed can be increased and the power consumption can be reduced.

  As described above, according to the nonvolatile semiconductor memory device according to the modification of the first embodiment, the impurity having the same conductivity type as the source region is formed in the silicon layer 4 located between the source regions adjacent to each other in the row direction. An introduction region 10 was formed. Therefore, the resistance of the source lines SL1 to SL5 can be reduced.

Embodiment 2. FIG.
In the nonvolatile semiconductor memory device according to the first embodiment, the source region and the drain region of the memory cell transistor are formed deep so as to reach the upper surface of the BOX layer 3 as shown in FIG. However, as shown in FIG. 7, for example, the body region B21 is sandwiched between the source region Sa and the drain region Da from the left and right, so that the width of the body region Da in the channel length direction is narrowed. As a result, in FIG. Body resistance increases in the vertical direction (“Bulk-Layout-Compatible 0.18 μm SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI)”, Y.Hirano et al., 1999 IEEE International SOI Conference, Oct. 1999 , pp. 131). In the second embodiment, a nonvolatile semiconductor memory device that can avoid such inconvenience is proposed.

FIG. 9 is a cross-sectional view showing the structure of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 9 corresponds to an enlarged view of only one memory cell transistor corresponding to FIG. The source region S and the drain region D of the memory cell transistor are formed shallow so as not to reach the upper surface of the BOX layer 3. In this way, the source region S and the drain region D that do not reach the upper surface of the BOX layer 3 are, for example, a condition in which the implantation energy is 8 keV and the dose is 4 × 10 ¹⁵ / cm ² when the film thickness of the silicon layer 4 is 150 nm. And As (in the case of NMOS) can be formed by ion implantation.

  FIG. 10 is a sectional view showing the structure of the nonvolatile semiconductor memory device according to the second embodiment of the present invention corresponding to FIG. The source region S is formed so as not to reach the upper surface of the BOX layer 3, whereas the impurity introduction region 10 is formed so as to reach the upper surface of the BOX layer 3 as in the first embodiment. Yes.

  As described above, according to the nonvolatile semiconductor memory device according to the second embodiment, the source region S and the drain region D of the memory cell transistor are formed so as not to reach the upper surface of the BOX layer 3. It is possible to avoid an increase in body resistance in the vertical direction.

  3 and 4, in the nonvolatile semiconductor memory device according to the first embodiment, the body potential can be fixed only through a region between memory cells adjacent to each other in the row direction. . On the other hand, in the nonvolatile semiconductor memory device according to the second embodiment, since the silicon layer 4 exists between the bottom surfaces of the source region S and the drain region D and the top surface of the BOX layer 3, The body potential can also be fixed through a region between memory cells adjacent to each other in the direction. As a result, the body potential fixing capability is increased, and the breakdown voltage between the source and the drain can be further increased.

  In addition, as shown in FIG. 10, since the impurity introduction region 10 is formed so as to reach the upper surface of the BOX layer 3, it is avoided that a pn junction capacitance is generated between the impurity introduction region 10 and the silicon layer 4. can do. Therefore, an increase in the parasitic capacitance of the source line accompanying the formation of the source region and the drain region so as not to reach the upper surface of the BOX layer 3 can be suppressed to a minimum.

Embodiment 3 FIG.
In the nonvolatile semiconductor memory device according to the first embodiment, the pn junction capacitance on the drain side affects the data read operation and write operation that are randomly accessed. Further, the pn junction capacitance on the source side affects the data erasing operation performed in a lump. However, these relationships differ depending on the cell structure, the programming / erasing method, and the configuration of the memory cell array (see Nikkei Microdevice, March 2000, pp 74, 75).

FIG. 11 is a cross-sectional view showing the structure of the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention. FIG. 11 corresponds to an enlarged view of the memory cell transistors included in the memory cells MC31 and MC41, corresponding to FIG. The drain regions Da and Dd are formed deep so as to reach the upper surface of the BOX layer 3 as in the first embodiment. As described above, the drain regions Da and Dd reaching the upper surface of the BOX layer 3 are, for example, As (under the condition that the implantation energy is 50 keV and the dose is 4 × 10 ¹⁵ / cm ² when the thickness of the silicon layer 4 is 150 nm. (In the case of NMOS) can be formed by ion implantation. On the other hand, the source region Sd is formed shallow so as not to reach the upper surface of the BOX layer 3 as in the second embodiment.

  In the nonvolatile semiconductor memory device according to the third embodiment, the layout configuration shown in FIG. 4 can be adopted as the configuration of the memory cell array. In this case, the source line has the structure shown in FIG.

  As described above, according to the nonvolatile semiconductor memory device according to the third embodiment, the drain region is formed so as to reach the upper surface of the BOX layer 3, so that the data read operation and write operation can be performed at high speed and with low power consumption. By forming the source region so as not to reach the upper surface of the BOX layer 3 while maintaining the above operation, the body potential fixing ability can be enhanced.

  FIG. 12 is a top view showing a structure of a nonvolatile semiconductor memory device according to a modification of the third embodiment. However, FIG. 12 schematically shows the arrangement relationship of the floating gate, the word line (also serving as the control gate), the source line, and the element isolation insulating film. Similarly to the layout of the memory cell array shown in FIG. 49, a region where the element isolation insulating film 5 is not formed is provided between the rows, and the source lines SL1 to SL5 are formed in this region. At this time, the source lines SL <b> 1 to SL <b> 5 are formed shallow so as not to reach the upper surface of the BOX layer 3. That is, the silicon layer 4 exists between the bottom surfaces of the source lines SL1 to SL5 and the top surface of the BOX layer 3.

  According to the nonvolatile semiconductor memory device in the modification of the third embodiment, the potentials of the body regions adjacent to each other in the column direction across the source lines SL1 to SL5 are set to the bottom surface of the source lines SL1 to SL5 and the BOX layer 3. They can be fixed to each other through a portion of the silicon layer 4 located between the upper surfaces of the two layers. Therefore, it is inferior to the layout shown in FIGS. 3 and 4 from the viewpoint of reducing the area of the memory cell array portion, but is very excellent in terms of the body potential fixing ability. Therefore, it is desirable to adopt the layout shown in FIG. 12 in a flash memory that requires a high breakdown voltage between the source and drain, such as a large number of rewrites. Even in the nonvolatile semiconductor memory device adopting the layout shown in FIG. 12, since the drain region is formed to reach the upper surface of the BOX layer 3, the data read operation and write operation are performed at high speed. It is possible to maintain low power consumption operation.

Embodiment 4 FIG.
FIG. 13 is a cross-sectional view showing the structure of the semiconductor integrated circuit according to the fourth embodiment of the present invention. The SOI substrate 1 has a memory cell array section in which a memory cell array of a flash memory is formed, and a low voltage logic circuit section in which a low voltage logic circuit that operates at a voltage lower than the operating voltage of the flash memory is formed. Yes. Specifically, a peripheral circuit of the flash memory itself and other logic circuits used in combination with the flash memory are formed in the low voltage logic circuit unit.

  The memory cell array portion and the low voltage logic circuit portion are separated from each other by a partial isolation type element isolation insulating film 5 formed in the upper surface of the silicon layer 4. The film thickness of the silicon layer 4 in the memory cell array part and the film thickness of the silicon layer 4 in the low voltage logic circuit part are equal to each other.

  With respect to the memory cell array portion, source / drain regions 12 that are spaced apart from each other and form a pair are formed in the upper surface of the silicon layer 4. Further, a stacked structure in which a gate oxide film 6, a floating gate 7, an insulating film 8, and a control gate 9 are stacked in this order is formed on the upper surface of the silicon layer 4 that is sandwiched between the source / drain regions 12. ing. Further, a side wall 11 is formed on the side surface of the laminated structure to constitute a gate electrode structure. The source / drain regions 12 do not reach the upper surface of the BOX layer 3 as in the second embodiment. However, similarly to the third embodiment, the drain region may reach the upper surface of the BOX layer 3 and only the source region may not reach the upper surface of the BOX layer 3.

  On the other hand, with respect to the low voltage logic circuit portion, a source / drain region 14 is formed in the upper surface of the silicon layer 4 so as to be spaced apart from each other. A stacked structure in which the gate oxide film 6 and the gate electrode 13 are stacked in this order is formed on the upper surface of the silicon layer 4 between the source / drain regions 14. Further, a side wall 11 is formed on the side surface of the laminated structure to constitute a gate electrode structure. The source / drain regions 14 are all formed so as to reach the upper surface of the BOX layer 3.

  Thus, according to the semiconductor integrated circuit according to the fourth embodiment, in the memory cell array portion, the source / drain region 12 is the same as in the second embodiment, or only the source region is the same as in the third embodiment. However, in the low voltage logic circuit portion, both the source / drain regions 14 are formed so as to reach the upper surface of the BOX layer 3. . Therefore, the pn junction constituted by the source / drain region 14 and the silicon layer 4 is obtained in the low voltage logic circuit portion while obtaining the effect of the nonvolatile semiconductor memory device according to the second and third embodiments with respect to the memory cell array portion. A decrease in operating speed and an increase in power consumption accompanying an increase in capacity can be avoided.

Embodiment 5 FIG.
FIG. 14 is a sectional view showing a structure of a semiconductor integrated circuit according to the fifth embodiment of the present invention. As in the fourth embodiment, the SOI substrate 1 has a memory cell array portion and a low voltage logic circuit portion. The film thickness of the silicon layer 4 in the low voltage logic circuit part is smaller than the film thickness of the silicon layer 4 in the memory cell array part. The memory cell array portion and the low voltage logic circuit portion are separated from each other by a partial isolation type element isolation insulating film 15 formed in the upper surface of the silicon layer 4.

  In the memory cell array portion, memory cell transistors similar to those in the fourth embodiment are formed. Further, on the upper surface of the silicon layer 4 in the low voltage logic circuit portion, a gate electrode structure similar to that of the fourth embodiment is configured. A source / drain region 36 reaching the upper surface of the BOX layer 3 is formed in the silicon layer 4 in the low voltage logic circuit portion. The depth from the top surface of the silicon layer 4 to the bottom surface of the source / drain region 12 is equal to the depth from the top surface of the silicon layer 4 to the bottom surface of the source / drain region 36.

The structure shown in FIG. 14 includes (a) a step of preparing an SOI substrate 1 with a silicon layer 4 having a film thickness of, for example, 200 nm, and (b) the silicon layer 4 in the low-voltage logic circuit portion having an upper surface of 100 nm. (C) a step of forming the element isolation insulating film 15; (d) a step of forming a gate electrode structure in each of the memory cell array portion and the low voltage logic circuit portion; The step of ion-implanting As (in the case of NMOS) under the conditions of 50 keV and a dose of 4 × 10 ¹⁵ / cm ² is obtained in this order.

  As described above, according to the semiconductor integrated circuit according to the fifth embodiment, as in the fourth embodiment, the memory cell array unit is obtained with the effects of the nonvolatile semiconductor memory device according to the second and third embodiments. In the low voltage logic circuit portion, it is possible to avoid a decrease in operating speed and an increase in power consumption accompanying an increase in pn junction capacitance formed by the source / drain regions 36 and the silicon layer 4.

  Moreover, since the silicon layer 4 in the low voltage logic circuit portion is thinned in advance, the source / drain region 12 that does not reach the upper surface of the BOX layer 3 and the source / drain region 36 that reaches the upper surface of the BOX layer 3 are It can be formed by the same ion implantation step (e).

Embodiment 6 FIG.
FIG. 15 is a sectional view showing a structure of a semiconductor integrated circuit according to the sixth embodiment of the present invention. The semiconductor integrated circuit according to the sixth embodiment is based on the semiconductor integrated circuit according to the fourth embodiment shown in FIG. 13 and has an element isolation insulating film at the boundary between the memory cell array portion and the low voltage logic circuit portion. Instead of 5, an element isolation insulating film 16 is formed. The element isolation insulating film 16 has a complete isolation part 40 reaching the upper surface of the BOX layer 3 at a part of the bottom surface.

  16 to 19 are sectional views showing the first manufacturing method of the element isolation insulating film 16 in the order of steps (Japanese Patent Application No. 10-367265). First, an oxide film 17 and a nitride film 18 are formed on the entire surface of the silicon layer 4 in this order. Next, a photoresist 19 having an opening pattern above the region where the element isolation insulating film 16 is to be formed is formed on the upper surface of the nitride film 18. Next, using the photoresist 19 as a mask, the nitride film 18, the oxide film 17, and the silicon layer 4 are etched in this order to form the recess 20. At this time, part of the silicon layer 4 remains between the bottom surface of the recess 20 and the top surface of the BOX layer 3 (FIG. 16).

  Next, a sidewall 21 made of an insulating film is formed on the side surface of the recess 20 (FIG. 17). As shown in FIG. 17, the central portion of the bottom surface of the recess 20 is exposed from the sidewall 21. Next, using the sidewall 21 and the photoresist 19 as a mask, the silicon layer 4 is etched until the upper surface of the BOX layer 3 is exposed, thereby forming the recess 22 (FIG. 18). Next, after filling the recesses 20 and 22 with an insulating film, the whole is polished by CMP to such an extent that the bottom of the nitride film 18 remains, and then the remaining nitride film 18 and oxide film 17 are removed. Then, the element isolation insulating film 16 having the complete isolation portion 40 is formed (FIG. 19).

  20 and 21 are cross-sectional views showing the second manufacturing method of the element isolation insulating film 16 in the order of steps (Japanese Patent Application No. 10-367265). First, after obtaining the structure shown in FIG. 16, the photoresist 19 is removed. Next, a photoresist 23 having an opening pattern is formed above the region where the complete separation portion 40 is to be formed (FIG. 20). Next, using the photoresist 23 as a mask, the silicon layer 4 is etched until the upper surface of the BOX layer 3 is exposed, thereby forming a recess 24 (FIG. 21).

  Next, after removing the photoresist 23, the recesses 20 and 24 are filled with an insulating film. Next, the whole is polished by CMP to such an extent that the bottom of the nitride film 18 remains, and then the remaining nitride film 18 and oxide film 17 are removed, so that the complete isolation portion 40 is provided as in FIG. An element isolation insulating film 16 is formed.

  22 to 24 are cross-sectional views showing the third manufacturing method of the element isolation insulating film 16 in the order of steps (Japanese Patent Application No. 11-177091). First, an oxide film 17 and a nitride film 18 are formed on the entire surface of the silicon layer 4 in this order. Next, a photoresist 25 having an opening pattern above the region where the complete separation portion 40 is to be formed is formed on the upper surface of the nitride film 18. Next, using the photoresist 25 as a mask, the nitride film 18, the oxide film 17, and the silicon layer 4 are etched in this order until the upper surface of the BOX layer 3 is exposed, thereby forming a recess 26 (FIG. 22). ).

  Next, after removing the photoresist 25, a photoresist 27 having an opening pattern above the region where the element isolation insulating film 16 is to be formed is formed on the upper surface of the nitride film 18 (FIG. 23). Next, using the photoresist 27 as a mask, the nitride film 18, the oxide film 17, and the silicon layer 4 are etched in this order to form a recess 28. At this time, part of the silicon layer 4 remains between the bottom surface of the recess 28 and the top surface of the BOX layer 3. Thereafter, the photoresist 27 is removed (FIG. 24).

  Next, after filling the recesses 26 and 28 with an insulating film, the entire surface is polished by CMP so that the bottom of the nitride film 18 remains, and then the remaining nitride film 18 and oxide film 17 are removed. Similarly to FIG. 19, the element isolation insulating film 16 having the complete isolation portion 40 is formed.

  25 to 29 are sectional views showing a fourth manufacturing method of the element isolation insulating film 16 in the order of steps (Japanese Patent Application No. 2000-39484). First, an oxide film 17, a polysilicon film 29, and a nitride film 18 are formed on the entire top surface of the silicon layer 4 in this order. Next, a photoresist 30 having an opening pattern is formed on the upper surface of the nitride film 18 above the region where the element isolation insulating film 16 is to be formed (FIG. 25).

  Next, using the photoresist 30 as a mask, the nitride film 18, the polysilicon film 29, the oxide film 17, and the silicon layer 4 are etched in this order to form the recess 31. At this time, a part of the silicon layer 4 remains between the bottom surface of the recess 31 and the top surface of the BOX layer 3. Thereafter, the photoresist 30 is removed (FIG. 26).

  Next, similarly to the second manufacturing method, the silicon layer 4 is formed until the upper surface of the BOX layer 3 is exposed using the photoresist 23 having an opening pattern above the region where the complete separation portion 40 is to be formed as a mask. The recess 32 is formed by etching. Thereafter, the photoresist 23 is removed (FIG. 27).

  Next, wet oxidation is performed under a temperature condition of about 700 to 900 ° C. to form an oxide film 33 on the side surfaces of the recesses 31 and 32 (FIG. 28). The oxide film 33 penetrates deeply between the polysilicon film 29 and the oxide film 17 and between the oxide film 17 and the silicon layer 4. Therefore, the bird's beak shape of the oxide film 33 becomes remarkable.

  Next, after the recesses 31 and 32 are filled with the oxide film 34, the silicon oxide film 34 is polished by CMP so that the upper surface of the oxide film 34 does not become lower than the upper surface of the nitride film 18 (FIG. 29). ). Next, by removing the nitride film 18, the polysilicon film 29, and the oxide film 17, the element isolation insulating film 16 having the complete isolation part 40 is formed as in FIG.

  In the above description, the case where the invention according to the sixth embodiment is applied based on the semiconductor integrated circuit according to the fourth embodiment shown in FIG. 13 has been described. However, the embodiment shown in FIG. The invention according to the sixth embodiment can be applied on the basis of the semiconductor integrated circuit according to the fifth embodiment. FIG. 30 is a cross-sectional view showing the structure of the semiconductor integrated circuit according to the sixth embodiment of the present invention based on the semiconductor integrated circuit according to the fifth embodiment. In the semiconductor integrated circuit shown in FIG. 30, an element isolation insulating film 35 is formed in place of the element isolation insulating film 15 shown in FIG. 14 at the boundary between the memory cell array portion and the low voltage logic circuit portion. The element isolation insulating film 35 has a complete isolation portion 41 reaching the top surface of the BOX layer 3 at a part of the bottom surface.

  31 to 34 are cross-sectional views showing a method of manufacturing the semiconductor integrated circuit shown in FIG. First, an SOI substrate 1 having a stacked structure in which a silicon substrate 2, a BOX layer 3, and a silicon layer 4 are stacked in this order is prepared (FIG. 31). Next, the upper surface of the silicon layer 4 in the low voltage logic circuit portion is thermally oxidized to form a silicon oxide film (not shown). Since thermal oxidation also proceeds inside the silicon layer 4, the bottom surface of the silicon oxide film exists at a position lower than the top surface of the silicon layer 4 in the memory cell array portion. Next, the silicon oxide film formed by thermal oxidation is removed by etching. As a result, the upper surface of the silicon layer 4 in the low voltage logic circuit portion becomes lower than the upper surface of the silicon layer 4 in the memory cell array portion (FIG. 32).

  Next, the element isolation insulating film 35 is formed at the boundary between the memory cell array portion and the low voltage logic circuit portion by the same method as that for forming the element isolation insulating film 16. Further, a partial isolation type element isolation insulating film 5 is formed in the memory cell array portion and the low voltage logic circuit portion (FIG. 33).

  Next, in the memory cell array portion and the low voltage logic circuit portion, gate electrode structures are formed on the upper surface of the silicon layer 4 (FIG. 34). Specifically, a floating gate material is formed in advance in the memory cell array portion, for example, a polycide structure of polysilicon and tungsten silicide is formed on the entire surface, and then patterned to form a gate electrode structure.

  Thereafter, by using the gate electrode structure and the element isolation insulating films 5 and 35 as a mask, impurities are ion-implanted into the silicon layer 4 to form source / drain regions 12 and 36, and the structure shown in FIG. obtain.

  Referring to FIGS. 13 and 14, partial isolation type element isolation insulating films 5 and 15 are formed at the boundary between the memory cell array portion and the low voltage logic circuit portion. And the upper surface of the BOX layer 3 is a silicon layer 4. Therefore, noise generated in the memory cell array portion and the low voltage logic circuit portion easily propagates to each other through the silicon layer 4 in this portion, and the memory cell transistor and the low voltage logic circuit are susceptible to noise from each other. It was.

  On the other hand, according to the semiconductor integrated circuit according to the sixth embodiment, the element isolation insulating films 16 and 35 having the complete isolation portions 40 and 41 at the boundary portion between the memory cell array portion and the low voltage logic circuit portion. Is formed. Therefore, it is possible to prevent the noise in the memory cell array portion and the low voltage logic circuit portion from propagating to each other, and it is possible to obtain a semiconductor integrated circuit that is not easily affected by the noise.

  In the above description, the case where the element isolation insulating films 16 and 35 having the complete isolation portions 40 and 41 are formed on a part of the bottom surface has been described. Instead of forming the element isolation insulating films 16 and 35, BOX The same effect as described above can be obtained by forming a complete isolation type element isolation insulating film having a bottom surface reaching the top surface of the layer 3.

Embodiment 7 FIG.
FIG. 35 is a top view schematically showing a configuration of the semiconductor integrated circuit according to the seventh embodiment of the present invention. FIG. 36 is a cross sectional view schematically showing a cross sectional structure of the semiconductor integrated circuit according to the seventh embodiment of the present invention. As shown in FIGS. 35 and 36, the semiconductor integrated circuit according to the seventh embodiment includes a low voltage part including the low voltage logic circuit part and the like, and a high voltage part that handles a higher voltage than the low voltage part. ing. The high voltage part has a high voltage circuit part and a memory cell array part, and the high voltage circuit part and the low voltage part are arranged on the opposite side of the substrate across the memory cell array part. The high voltage circuit portion is separated from the memory cell array portion by an element isolation insulating film 45. The low voltage part is separated from the memory cell array part by the element isolation insulating film 45. As shown in FIG. 36, the element isolation insulating film 45 has a complete isolation portion 47 on a part of the bottom surface. However, instead of the element isolation insulating film 45, a complete isolation type element isolation insulating film may be formed.

  In the memory cell array portion, a plurality of memory cell transistors separated from each other by the partial isolation type element isolation insulating film 5 are formed in a matrix. Here, the invention according to the first to third embodiments may be applied to the memory cell array portion.

  In the low voltage portion, a plurality of low voltage transistors that are driven at a voltage lower than the drive voltage of the memory cell transistor are formed. Low voltage transistors adjacent to each other are separated by an element isolation insulating film 5. Here, the inventions according to the fourth and fifth embodiments may be applied to the memory cell array portion and the low voltage portion. In the high voltage circuit portion, a plurality of high voltage transistors that are driven at a voltage higher than the drive voltage of the low voltage transistors are formed. High voltage transistors adjacent to each other are separated by an element isolation insulating film 5.

  As described above, according to the semiconductor integrated circuit according to the seventh embodiment, the high voltage circuit portion and the low voltage portion are arranged on the opposite side of the substrate with the memory cell array portion interposed therebetween. It is possible to suppress the influence of the high voltage circuit portion that is likely to be a source.

  Further, the low voltage portion and the memory cell array portion, and the memory cell array portion and the high voltage circuit portion are separated from each other by the element isolation insulating film 45 having the complete isolation portion 47 or the complete isolation type element isolation insulating film. Therefore, it is possible to suppress the noise generated in each region from propagating to each other through the silicon layer 4 and to obtain a semiconductor integrated circuit which is not easily affected by the noise.

  FIG. 37 is a top view schematically showing a configuration of a semiconductor integrated circuit according to the first modification of the seventh embodiment of the present invention. The high voltage circuit section is divided into a plurality of circuit blocks 42a to 42d, and the low voltage section is divided into a plurality of circuit blocks 44a to 44f. The circuit blocks adjacent to each other are separated by an element isolation insulating film 45. According to the semiconductor integrated circuit of the first modification of the seventh embodiment, the mutual influence of noise between circuit blocks can be suppressed in the high voltage circuit portion and the low voltage portion, respectively.

  FIG. 38 is a top view schematically showing a configuration of a semiconductor integrated circuit according to the second modification of the seventh embodiment of the present invention. As in the semiconductor integrated circuit according to the first modification, an element isolation insulating film 45 is formed between the high voltage circuit portion, the memory cell array portion, and the low voltage portion, and the high voltage circuit The element isolation insulating film 45 is also formed between the circuit blocks in the part and the low voltage part.

  In the semiconductor integrated circuit according to the second modification of the seventh embodiment, for the sake of layout, a part of the high voltage circuit part and a part of the low voltage part are arranged adjacent to each other, and An element isolation insulating film 46 a wider than the element isolation insulating film 45 is formed between the high voltage circuit portion and the low voltage portion of the adjacent portions. The element isolation insulating film 46 a is an element isolation insulating film having a complete isolation portion 47 as with the element isolation insulating film 45 or a complete isolation type element isolation insulating film. According to the semiconductor integrated circuit according to the second modification of the seventh embodiment, a wider width having higher isolation performance than the element isolation insulating film 45 between the high voltage circuit portion and the low voltage portion in the adjacent portions. Since the element isolation insulating film 46a is formed, the mutual influence of noise between the high voltage circuit portion and the low voltage portion in the adjacent portion can be suppressed.

  Further, in the semiconductor integrated circuit according to the first and second modifications of the seventh embodiment, a high voltage (RF) circuit that handles a high frequency analog minute signal is formed in the low voltage portion. It is desirable to form a high-frequency circuit in the circuit blocks 44f and 44j arranged farthest from the circuit unit. Thereby, the influence which a high frequency circuit receives with the noise which generate | occur | produced in the high voltage circuit part can be relieved.

  Further, referring to FIG. 38, when a high frequency circuit is formed in circuit block 44j, wide element isolation with high isolation performance is provided between circuit block 44j and circuit blocks 44g and 44i adjacent thereto. The insulating film 46b may be formed. The element isolation insulating film 46 b is an element isolation insulating film having a complete isolation portion 47 as with the element isolation insulating film 45 or a complete isolation type element isolation insulating film. Thereby, the influence which a high frequency circuit receives by the noise which generate | occur | produced in areas other than the circuit block 44j can further be relieved.

Embodiment 8 FIG.
FIG. 39 is a sectional view schematically showing a configuration of a semiconductor integrated circuit according to the eighth embodiment of the present invention. As shown in FIG. 39, the semiconductor integrated circuit according to the eighth embodiment is based on the semiconductor integrated circuit according to the seventh embodiment shown in FIG. 36, and the element isolation insulating film in the high voltage circuit portion and the memory cell array portion. 48 and 49 are formed deeper than the element isolation insulating films 5 and 45 in the low voltage portion.

  The element isolation insulating film 48 is a partial isolation type element isolation insulating film, and is formed between high voltage transistors adjacent to each other in the high voltage circuit portion and between memory cell transistors adjacent to each other in the memory cell array portion. Yes. The element isolation insulating film 49 is an element isolation insulating film having a complete isolation portion 50 on a part of the bottom surface, and is formed between the high voltage circuit portion and the memory cell array portion.

  As described above, according to the semiconductor integrated circuit according to the eighth embodiment, the element isolation insulating films 48 and 49 in the high voltage circuit portion and the memory cell array portion are formed deeper than the element isolation insulating films 5 and 45 in the low voltage portion. Therefore, the isolation breakdown voltage of the element isolation insulating films 48 and 49 can be increased in the high voltage portion that handles a higher voltage than the low voltage portion.

Embodiment 9 FIG.
FIG. 40 is a cross-sectional view schematically showing the configuration of the semiconductor integrated circuit according to the ninth embodiment of the present invention. In FIG. 40, the high voltage circuit portion and the memory cell array portion in the eighth embodiment are collectively described as “high voltage portion”. The same applies to FIGS. 41 to 43 described later. In the low voltage portion, a channel cut layer 52 is formed in a portion of the silicon layer 4 located between the bottom surface of the element isolation insulating film 5 and the top surface of the BOX layer 3. In the high voltage portion, a channel cut layer 51 having an impurity concentration higher than that of the channel cut layer 52 is present in a portion of the silicon layer 4 located between the bottom surface of the element isolation insulating film 5 and the top surface of the BOX layer 3. Is formed.

  As described above, according to the semiconductor integrated circuit according to the ninth embodiment, the impurity concentration of the channel cut layer 51 formed in the high voltage portion is higher than the impurity concentration of the channel cut layer 52 formed in the low voltage portion. Therefore, the isolation breakdown voltage between elements can be increased in the high voltage portion.

Embodiment 10 FIG.
41 to 43 are cross-sectional views showing the structure of the semiconductor integrated circuit according to the tenth embodiment of the present invention. Referring to FIG. 41, transistors are formed in the high voltage portion and the low voltage portion of SOI substrate 1, respectively. A channel doped region 54 is formed in the silicon layer 4 in the low voltage portion, and a channel doped region 53 having an impurity concentration higher than that of the channel doped region 54 is formed in the silicon layer 4 in the high voltage portion. Has been.

  Referring to FIG. 42, transistors are formed in the high voltage portion and the low voltage portion of SOI substrate 1, respectively. The thickness of the gate oxide film 55 of the transistor formed in the high voltage portion is larger than the thickness of the gate oxide film 6 of the transistor formed in the low voltage portion.

  Referring to FIG. 43, transistors are formed in the high voltage portion and the low voltage portion of SOI substrate 1, respectively. The gate length of the transistor formed in the high voltage portion is longer than the gate length of the transistor formed in the low voltage portion. The structures shown in FIGS. 41 to 43 may be used in any combination.

  As described above, according to the semiconductor integrated circuit according to the tenth embodiment, the threshold voltage of the transistor formed in the high voltage portion is set higher than the threshold voltage of the transistor formed in the low voltage portion. Since it can be set, the punch-through resistance of the transistor can be increased in the high voltage portion.

Embodiment 11 FIG.
Embodiment 11 of the present invention is directed to a nonvolatile semiconductor memory device having a structure in which both the source region and the drain region reach the upper surface of the BOX layer 3 as shown in FIG. FIG. 44 is a circuit diagram showing a part of the configuration of the memory cell array of the flash memory according to the eleventh embodiment of the present invention. FIG. 44 shows only the configuration of a total of nine memory cells of 3 rows × 3 columns. Memory cell transistors belonging to the same row are connected to a common body line. For example, the memory cell transistors included in the memory cells MC11 to MC13 are commonly connected to the body line BDL1.

  The word lines WL1 to WL3 are connected to word line drive circuits 601 to 603, respectively. The body lines BDL1 to BDL3 are connected to body line drive circuits 611 to 613, respectively. At this time, as shown in FIG. 44, the drive circuits 601 to 603 and the drive circuits 611 to 613 are preferably arranged on the opposite side of the substrate with the memory cell array interposed therebetween.

  In a general flash memory, for example, data is written by applying a voltage of 0 V to the source S, 5 V to the drain D, and 12 V to the control gate CG, and injecting hot electrons into the floating gate FG. Do.

  In the eleventh embodiment, when data write operation is performed, a voltage is also applied to body lines BDL1 to BDL3. FIG. 45 is a timing chart showing waveforms of a word line (WL) drive signal and a body line (BDL) drive signal applied to the word line and the body line, respectively, when writing data. The WL drive signal changes from the L level to the H level at time t1. At this time, it is desirable to drive the body line BDL so that the BDL drive signal transitions from the L level to the H level at time t2 earlier than t1. That is, it is desirable to drive the body line BDL prior to the word line WL.

  The body line BDL made of silicon has a higher resistance and a lower signal transmission speed than the word line WL made of silicide or the like. However, by driving the body line BDL prior to the word line WL, it is possible to avoid delaying the BDL drive signal with respect to the WL drive signal.

  Thus, according to the nonvolatile semiconductor memory device in accordance with the eleventh embodiment, the body line BDL is driven together with the word line WL when performing a data write operation. Thereby, since a bipolar current can also flow from the source S to the drain D of the memory cell transistor, it is possible to improve the writing efficiency. For example, by applying a voltage of 0.3V to the body line BDL, the voltage applied to the word line WL can be lowered to 10V. Thereby, power consumption can be reduced.

  In addition, since the drive circuits 601 to 603 and the drive circuits 611 to 613 are arranged on the opposite side of the substrate across the memory cell array, the influence of the voltage drop due to the resistances of the word line WL and the body line BDL is affected. Can be offset. This makes it possible to make the write characteristics uniform for a plurality of memory cells belonging to the same row.

  Note that a voltage of 0 V is applied to the non-selected body line BDL from the drive circuits 611 to 613, or a voltage having a polarity opposite to that of the selected body line BDL (for example, −0.3 V) is applied. Is desirable. Thereby, it is possible to avoid the occurrence of disturb failure.

  1 SOI substrate, 2 silicon substrate, 3 BOX layer, 4 silicon layer, 5, 15, 16, 35, 46a, 46b, 48, 49 element isolation insulating film, 70 body region, 10 impurity introduction region, 12, 14, 36 Source / drain region, 40, 41, 47, 50 Completely isolated portion, 51, 52 Channel cut layer.

Claims (10)

An SOI substrate having a structure in which a semiconductor substrate, an insulating layer, and a semiconductor layer are stacked in this order;
A first isolation insulating film formed in a main surface of the semiconductor layer and having the semiconductor layer between the insulating layer;
A first MOS transistor formed in the semiconductor layer;
A second MOS transistor formed adjacent to the first MOS transistor in the semiconductor layer;
The semiconductor device in which the semiconductor layer of the first MOS transistor is thicker than the semiconductor layer of the second MOS transistor. The semiconductor device according to claim 1, wherein the first isolation insulating film is formed between the first MOS transistor and the second MOS transistor. A second isolation insulating film formed from the main surface of the semiconductor layer to the upper surface of the insulating layer;
The semiconductor device according to claim 1, wherein the second isolation insulating film is formed between the first MOS transistor and the second MOS transistor. The third isolation insulating film formed between the first MOS transistor and the second MOS transistor includes a first region on the formation region of the first MOS transistor and the second MOS transistor. The semiconductor device according to claim 1, wherein a third region in contact with the insulating layer is continuously formed between a second region on the transistor formation region, the first region, and the second region. The semiconductor device according to claim 2, wherein a source / drain region of the second MOS transistor reaches an upper surface of the insulating layer.   The semiconductor device according to claim 5, wherein a source / drain region of the first MOS transistor does not reach an upper surface of the insulating layer. The first MOS transistor constitutes a high voltage part,
The semiconductor device according to claim 5, wherein the second MOS transistor forms a low voltage portion. The first MOS transistor constitutes a memory cell transistor;
The semiconductor device according to claim 5, wherein the second MOS transistor forms a logic circuit. The first MOS transistor includes a gate electrode formed on the body region of the portion sandwiched between the source region and the drain region via an insulating film,
The semiconductor device according to claim 5, wherein the potential of the body region is fixed from the outside. The semiconductor device according to claim 1, wherein the first MOS transistor constitutes a flash memory.

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