JP3064002B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a MISFET.

[Conventional technology]

In a semiconductor device having an MISFET, a high electric field is generated in the vicinity of the drain region because the gate insulating film is thinned and the channel length is shortened due to high integration. For this reason, generation of hot electrons becomes remarkable, causing an increase in a current flowing in the substrate, that is, a so-called substrate current. As a result, MISF
The electrical characteristics of the ET threshold voltage deteriorated with time.

Therefore, a double drain structure is formed by a semiconductor region with a high impurity concentration and a semiconductor region with a low impurity concentration, and the MISF
A method for relaxing a high electric field near the drain region of the ET has been proposed. To form a double drain structure, for example, phosphorus is ion-implanted and thermally diffused to form a low-concentration impurity region, and then arsenic is ion-implanted to form a high-concentration impurity region, or Arsenic is ion-implanted almost simultaneously to form a semiconductor region with a high impurity concentration and a semiconductor region with a low impurity concentration due to a difference in diffusion coefficient.

On the other hand, semiconductor integrated circuits with MISFETs are susceptible to electrical breakdown due to static electricity.
When ET is adopted, there is a problem that the electrostatic breakdown voltage is reduced.

To solve such a problem, Japanese Patent Application Laid-Open No.
JP-A-61-177769 and JP-A-61-177769 disclose a single-drain structure MI as a MISFET connected to the periphery of a semiconductor integrated circuit, that is, an external input / output terminal.
An SFET is placed in the center, that is, a MISFET that is not directly connected to such a terminal.
It is shown that a MISFET is arranged, a single drain having a high electrostatic breakdown voltage is provided in a peripheral portion where electrostatic breakdown easily occurs, and a double drain which suppresses a substrate current is used in a central portion. That is, as shown in FIG. 3, a MISFET having a single drain structure is arranged in a peripheral portion where static electricity is easily applied so as not to deteriorate the electrostatic breakdown voltage, and a MISFET having a double drain structure having a small substrate current is arranged in a central portion. Things.

Although the MISFET having a single drain structure in the peripheral portion does not cause a decrease in the electrostatic breakdown voltage, it is similar to the conventional single drain structure in that the substrate current is large. Further, the peripheral circuits generally form an input / output circuit, and the current flowing therethrough is large. For this reason, the MISFET in the peripheral portion was liable to cause a reduction in snapback voltage and deterioration of the gate oxide film of the MISFET.

In order to solve the above-mentioned problems, the present inventor has proposed a MISFET having a double drain structure in both the central portion and the peripheral portion of a semiconductor device.
In the center, use a deep MISFET that suppresses the substrate current and has a low diffusion depth and a low diffusion.The peripheral portion uses a MISFET with a small reduction in electrostatic breakdown voltage and a thin diffusion that can suppress the substrate current to some extent. It has been found that optimal electrical characteristics can be obtained by the use.

[Problems to be solved by the invention]

In view of the above, the present invention improves the precision of the diffusion depth and tunes the electrical characteristics in manufacturing a semiconductor device that reduces the substrate current and does not lower the electrostatic breakdown voltage even in the peripheral portion. It is an object to provide an easy manufacturing method.

[Means for solving the problem]

According to the present invention, a conductive layer is provided on a main surface of a first semiconductor region of a first conductivity type with an insulating film interposed therebetween, and the first semiconductor region on both sides of the conductive layer is provided.
A first conductive type second semiconductor region provided on a main surface of the semiconductor region, and a second conductive type third semiconductor region having a lower impurity concentration than the second conductive type semiconductor region provided along the second semiconductor region;
And a second MISFET, wherein the first MISFET is disposed in a central portion of the semiconductor device, the second MISFET is disposed in a peripheral portion of the semiconductor device, and the second MISFET is disposed in the third semiconductor region. A method of manufacturing a semiconductor device having a thickness of less than that of the first MISFET, wherein the second MISFET formation region is covered with a mask;
Introducing a first impurity into the main surface of the first semiconductor region in the MISFET formation region, and removing the mask in the second MISFET formation region.
Diffusing the introduced first impurity; introducing a first impurity into a main surface portion of the first MISFET formation region and the second MISFET formation region; The first MI is diffused by diffusing impurities.
Forming a third semiconductor region of the SFET formation region and the second MISFET formation region; and introducing a second impurity into a main surface portion of the first MISFET formation region and the second MISFET formation region. And a step of forming a second semiconductor region by diffusing the introduced second impurity.

[Action]

According to the method of manufacturing a semiconductor device of the present invention, since the step of introducing the first impurity is divided into two steps, the impurity concentration is adjusted between the first introduction and the second introduction, so that the first MISFET and the second impurity are introduced. The third semiconductor region having a different thickness from the second MISFET can be formed with high accuracy.

Therefore, the first MISFET can sufficiently reduce the substrate current, and the second MISFET can reduce the substrate current without significantly lowering the electrostatic breakdown voltage. The second MISFET is arranged in a peripheral portion of the semiconductor device which is easily damaged by static electricity, and is electrically connected to an external input / output terminal. The first MISFET is arranged in a central portion because the substrate current can be reduced. . Therefore, it is possible to provide a semiconductor device having a good balance between the reduction of the substrate current and the electrostatic breakdown voltage in the peripheral portion connected to the external input / output terminal.

EXAMPLES Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a diagram schematically showing an embodiment of a semiconductor device manufactured by the present invention. In the drawings, the same components are denoted by the same reference numerals, and the description thereof will not be repeated.

In FIG. 1, reference numeral 1 denotes a first MISFET arranged at the center of the semiconductor device, which is not connected to an external input / output terminal. Reference numeral 2 denotes a second MISFET arranged in a peripheral portion connected to an external input / output terminal of the semiconductor device.

30 is a semiconductor substrate, 36 is a first semiconductor region, 33 is a field insulating film, 32 is an insulating film, 31 is a conductive layer, 39 is a second semiconductor region, 35 and 37 are third semiconductor regions, 41 is an interlayer insulating film, Reference numeral 42 denotes an aluminum (Al) film for wiring.

The semiconductor substrate 30 is, for example, an N-type silicon
Ωcm can be used. First on the main surface of the semiconductor substrate 30
A semiconductor region 36 is formed. The first semiconductor region 36 is a P-type semiconductor region, so-called P-well, and is formed by introducing and diffusing impurities such as boron by a known method. When a P-type semiconductor substrate is used, it is not necessary to have a well structure, and the semiconductor substrate 30 becomes the first semiconductor region.

A field insulating film for electrically isolating the MISFET is formed on a main surface portion or a boundary of the first semiconductor region 36 by a known technique such as a LOCOS method. In addition, the first semiconductor region 36
The first semiconductor region 36 is formed in a region of the main surface of the
An insulating film 32 formed by thermally oxidizing the MISFET is provided and used as a gate insulating film of the MISFET. Further, a conductive layer 31 is provided via an insulating film 32. The conductive layer 31 is formed by forming a polycrystalline silicon layer, then doping phosphorus, and then by a well-known etching technique. Used as

The second semiconductor region 39 is formed by, for example, arsenic ion implantation, is an N-type region having a high impurity concentration, and is a so-called N ⁺ region. In addition, the second semiconductor region 39 is a drain
In the source region, the diffusion depth is approximately 0 in this embodiment.
3 μm.

The third semiconductor regions 35 and 37 are provided along the second semiconductor region 39, are N-type regions having a lower impurity concentration than the second semiconductor region 39, and are so-called N ⁻ regions. The third semiconductor regions 35 and 37 are formed by, for example, introducing and diffusing phosphorus. Since the third semiconductor regions 35 and 37 have the same impurity introduced therein, they can be regarded as a single semiconductor region.

An interlayer insulating film 4 is formed over the entire surface of the MISFETs 1 and 2.
1 is, for example, SiO ₂ formed by CVD, and an aluminum (Al) film 42 for wiring is provided for connection of MISFET.

Both MISFET1 and MISFET2 have a second semiconductor region 39 and a third semiconductor region, but the third semiconductor region of MISFET2 is thinner than MISFET1.

FIG. 2 shows a method of manufacturing a semiconductor device having a MISFET having the above-described structure.

A first semiconductor region 36 is formed on the semiconductor substrate 30 by a known method, and a field oxide film 33 is formed. Next, after forming the insulating film 32, for example, a polycrystalline silicon film is formed by CVD,
The conductive layer 31 is formed by doping phosphorus.

First, as shown in FIG. 2A, the MISFET 2 formation region in the peripheral portion of the semiconductor device where the electrostatic breakdown voltage is not reduced is masked.
Then, an impurity forming the third semiconductor region 35, for example, phosphorus is ion-implanted in an amount of 8.0 × 10 ¹³ cm ⁻² at an energy of 100 keV.

Next, after removing the mask 40, the ion-implanted phosphorus is diffused in a furnace at 1000 ° C. for 30 minutes to form a third semiconductor region 35 as shown in FIG. 2B.

Next, as shown in FIG. 2C, phosphorus ions are implanted at 7.0 × 10 ¹³ cm ⁻² at an energy of 100 keV. At this time, Nch-MI
It is only necessary to implant ions into the entire region where the SFET is to be formed, and it is only necessary to mask the region of the Pch-MISFET as in the conventional case, so that there is no need to add an extra step. As a result, the first
A total of 1.5 × 10 ¹⁴ cm ⁻² phosphorus ions are implanted into the MISFET, and a 7.0 × 10 ¹³ cm ⁻² ion implantation is performed into the second MISFET.

Next, the ion-implanted phosphorus is diffused in a furnace at 1000 ° C. for 30 minutes, and the ion-implanted phosphorus is diffused for a total of 60 minutes to form third semiconductor regions 35 and 37 as shown in FIG. 2D.

Subsequently, an impurity for forming the second semiconductor region 39, for example, arsenic is ion-implanted in an amount of 5 × 10 ¹⁵ cm ⁻² at an energy of 75 keV.

Further, the ion-implanted arsenic is thermally diffused in a furnace at 1000 ° C. for 50 minutes to form a second semiconductor region 39 of arsenic as shown in FIG. 2F. At this time, the second semiconductor region 39 has a diffusion depth of about 0.1 for both the first MISFET1 and the second MISFET2.
3 μm.

Further, an interlayer insulating film 41, an aluminum film for wiring 42 and the like are provided, and the semiconductor device of FIG. 1 is formed.

Embodiment 2 Embodiment 2 of the present invention is directed to the third semiconductor region 3 of the first MISFET1.
5. The amount and diffusion time of the first ion implantation for forming 5 and the amount and diffusion of the second ion implantation for forming the third semiconductor regions 35 and 37 of the first MISFET1 and the second MISFET2. Other than that, the time is the same as that of the first embodiment.

In the second embodiment, the third semiconductor region 35 of the first MISFET
The first ion implantation to form phosphorus is 100 keV phosphorus
Do an amount of 1.2 × 10 ¹⁴ cm ^-2 with energy. Next, the ion-implanted phosphorus is diffused in a furnace at 1000 ° C. for 45 minutes to form a third semiconductor region 35 as shown in FIG. 2B.

Next, the second ion implantation for ion-implanting into the formation regions of the first MISFET1 and the second MISFET2 is performed at an energy of 100 keV.
Perform an amount of 3.0 × 10 ¹³ cm ^-2 . Subsequently, the ion-implanted phosphorus is diffused in a furnace at 1000 ° C. for 15 minutes to form third semiconductor regions 35 and 37 as shown in FIG. 2B.

Phosphorus is implanted in a total amount of 1.5 × 10 ¹⁴ cm ⁻² and diffused for a total of 60 minutes. That is, in the first and second embodiments, the same amount of ions and the same diffusion time are added to the first MISFET, and the ratio of the first ion implantation to the second ion implantation is changed. Table 1 summarizes the ion implantation amounts and diffusion times of Example 1 and Example 2.

Table 1 shows the electrostatic breakdown strength and the substrate current of the semiconductor device formed by such a method. Table 2 shows the breakdown rate of the device when a voltage is applied to the external output terminal, and a voltage of 3.0 V applied to the gate and 7.0 V applied to the drain.
3 shows a substrate current when a voltage of?

First, the conventional MISF with double drain structure
In the case of ET (MISFET1 of this embodiment), the substrate current is suppressed to 3.6 μA.
Above 400V all will be degraded. On the other hand, the MISFET of the single drain structure does not cause electrostatic breakdown, but the substrate current is much larger than that of the double drain, 41.1μ
A.

The MISFET having a thin double drain structure of the third semiconductor region manufactured by the manufacturing method of the present invention is, for example, 250 V in the first embodiment.
The thing which causes electrostatic destruction appears, and all deteriorates at 550V or more. The substrate current is 3.8 μA. In the second embodiment, no electrostatic breakdown occurs up to 600 V, and the substrate current is 5.4 μA.
It is. As described above, the substrate current is considerably smaller than that of the single drain, and the withstand voltage of the electrostatic breakdown is improved as compared with the conventional double drain structure.

In the present invention, a MISFET having a double-drain structure with a small diffusion depth is used in the periphery, and a conventional MISFET with a large diffusion depth is used in the center, so that the former has the required electrostatic withstand voltage and suppresses the substrate current. The latter has a double drain structure capable of sufficiently suppressing the substrate current.

In the first embodiment, the ion implantation amount in the first and second times is about 1:
Although the ratio is set to 1 and the ratio is set to 4: 1 in the second embodiment, it is desirable to set the impurity introduction amount and the diffusion time so as to optimize them in consideration of the balance between the substrate current and the electrostatic breakdown voltage.
As a typical value, for example, it is set to be between 1: 1 to 8: 1, and the thickness of the low impurity concentration region of the MISFET in the peripheral portion is
The amount of impurity introduced and the diffusion time may be set so as to be approximately 0.1 to 0.8 times that of the central portion.

〔The invention's effect〕

According to the manufacturing method of the present invention, the MISFET having a double-drain structure with a thin third semiconductor region is used in the periphery, and the MISFET with a thick third semiconductor region is used in the center as in the related art. The double drain structure has a strength and can suppress the substrate current, and the latter has a double drain structure that can sufficiently suppress the substrate current. Further, the semiconductor device having the above structure can be formed without increasing the number of steps.

[Brief description of the drawings]

FIG. 1 is a view showing an embodiment of a semiconductor device manufactured by the present invention, FIG. 2 is a view showing an embodiment of a method of manufacturing a semiconductor device of the present invention, and FIG. 3 is a view showing a conventional semiconductor device. is there. 30 semiconductor substrate 31 conductive layer 32 insulating film 33 field insulating film 36 semiconductor region 35, 37 third semiconductor region 39 second semiconductor region 40 mask

Claims (1)

(57) [Claims] 1. A conductive layer is provided on a main surface of a first semiconductor region of a first conductivity type with an insulating film interposed therebetween, and said first layer is formed on both sides of said conductive layer.
A first conductive type second semiconductor region provided on a main surface of the semiconductor region, and a second conductive type third semiconductor region having a lower impurity concentration than the second conductive type semiconductor region provided along the second semiconductor region;
And a second MISFET, wherein the first MISFET is disposed in a central portion of the semiconductor device, the second MISFET is disposed in a peripheral portion of the semiconductor device, and the second MISFET is disposed in the third semiconductor region. A method of manufacturing a semiconductor device having a thickness of less than the first MISFET, wherein the second MISFET formation region is covered with a mask,
A step of introducing a first impurity into a main surface portion of the first semiconductor region in the MISFET formation region; and a step of diffusing the introduced first impurity after removing a mask in the second MISFET formation region. Introducing a first impurity into a main surface of the first MISFET formation region and the second MISFET formation region; and diffusing the introduced first impurity to form the first MISF.
Forming an ET formation region and a third semiconductor region of the second MISFET formation region; and introducing a second impurity into a main surface of the first MISFET formation region and the second MISFET formation region. A method for manufacturing a semiconductor device, comprising: a step of forming a second semiconductor region by diffusing the introduced second impurity.