JP2001176986A - Method for producing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a producing method for semiconductor device, with which a threshold voltage can be controlled without damaging reliability against hot electron. SOLUTION: After an impurity is injected for controlling a threshold value and annealing is performed for activating source and drain regions just after the gate of a CMOS transistor formed over plural wafers (S101), boron is injected so that the concentration of the impurity can become a peak in the region of prescribed depth from the surface of the wafer, phosphor almost as much as boron is injected (S102), the threshold voltage of the wafer is measured (S103) and the boron and the phosphor are activated by performing annealing to the wafer, which requires the control of the threshold voltage, on the basis of the measured result (S106). Concerning such a producing method, reliability against hot electron is maintained by suppressing a change in the concentration of the impurity in the region of the prescribed depth from the surface of the wafer and on the surface of the wafer, the threshold value is arbitrarily controlled corresponding to the change in the concentration of the impurity caused by anneal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an LDD structure (LigtlyDop).
The present invention relates to a method for manufacturing a semiconductor device suitable for controlling the threshold voltage of a MOS transistor (ed Drain).

[0002]

2. Description of the Related Art In order to prevent variation in threshold voltage (hereinafter referred to as VT) in a conventional CMOS transistor, management for minimizing variation in various manufacturing apparatuses, reduction in heat treatment temperature and heat treatment time are described. This is done by a method such as minimizing the variation of the impurity profile due to the shortening or the like.

Furthermore, with the recent miniaturization of devices, the sensitivity of VT to the gate length of a transistor is high, so that the amount of ion implantation and the heat treatment time must be adjusted according to the variation in the gate length. We are responding.

In the case of a BIP integrated circuit or a GaAs integrated circuit, a technique is used in which the electrical characteristics of the active layer are measured and the annealing time is changed based on the measurement result to control the electrical characteristics of the active layer. Have been.

[0005]

However, the above-mentioned conventional method for preventing VT variation does not allow for a desired VT even if various manufacturing equipment variations or heat treatment measures are adopted.
A variation of about 10% occurs.

Further, even in the case of adjusting the ion implantation amount or the heat treatment time corresponding to the variation in the gate length, the variation in the VT does not depend only on the gate length. Can not be controlled.

Further, as in the case of a BIP integrated circuit or a GaAs integrated circuit, the method for controlling the electrical characteristics of the active layer by performing annealing after measuring the electrical characteristics of the active layer is as follows. Therefore, it cannot be applied to a CMOS circuit.

That is, unlike a CMOS circuit, a BIP integrated circuit or a GaAs integrated circuit does not mainly require a complementary operation.
In a PN transistor or a GaAs integrated circuit, if the N-channel transistor can be controlled without variation, the P
Even if there is some variation between the NP transistor and the P-channel transistor, there is no problem in circuit characteristics.

However, in a CMOS circuit, both an N-channel transistor (hereinafter referred to as an NMOS transistor) and a P-channel transistor (hereinafter referred to as a PMOS transistor) play a large role in circuit operation. This is because, as in the case of an N-channel transistor of a GaAs integrated circuit, operation control or circuit characteristics cannot be satisfied by controlling only one of the transistors.

As for the process, the LDD shown in FIG.
As shown in the cross-sectional view of the transistor having the structure, the low-concentration layer 6 is provided on the drain electrode (also on the source electrode in terms of structure) to alleviate the drain electric field.
In a method of ion-implanting impurities for controlling hFE or VT like an integrated circuit and performing annealing, CM is used.
In the case of an OS transistor, the concentration at the place where the electric field generated near the drain of the NMOS transistor becomes highest (about 0.1 μm from the silicon surface) changes, and the reliability for hot electrons, which has been conventionally guaranteed, changes. Problems arise.

The present invention has been made in view of the above problems, and a main object of the present invention is to provide a method of manufacturing a semiconductor device capable of controlling a threshold voltage without impairing the reliability of hot electrons. Is to provide.

[0012]

According to a first aspect of the present invention, an impurity for controlling a threshold is implanted immediately below a gate of a CMOS transistor formed on a wafer. After that, in the method of manufacturing a semiconductor device for performing annealing for activating the source and drain regions, (a) the impurity concentration peaks at a predetermined depth from the wafer surface after the activation annealing. (B) implanting a predetermined amount of the first conductivity type impurity so that the impurity concentration peaks at the predetermined depth from the wafer surface after the first conductivity type impurity is implanted. Implanting an impurity of a second conductivity type in an amount substantially equal to the impurity of the first conductivity type; (c) measuring the threshold voltage of the wafer; and (d) measuring the threshold voltage of the wafer. Based on measurement results Come, wherein when the adjustment of the threshold voltage is required, the first conductivity type impurity and the second was the injected
Performing an annealing process for activating the conductive impurities.

According to a second aspect of the present invention, there is provided a method for activating a source and a drain region after implanting an impurity for controlling a threshold immediately below a gate of a CMOS transistor formed on a wafer. (A) measuring the threshold voltage of the wafer after the activation annealing; and (b) measuring the threshold voltage of the wafer after the activation annealing.
When it is necessary to adjust the threshold voltage based on the measurement result of the threshold voltage, a predetermined amount of the first conductive material is adjusted so that the impurity concentration peaks at a predetermined depth from the wafer surface. Implanting a mold impurity; and (c) an amount of the impurity substantially equal to the first conductivity type impurity such that the impurity concentration peaks at the predetermined depth from the wafer surface after the implantation of the first conductivity type impurity. The method includes at least a step of implanting a second conductivity type impurity and a step of (d) performing annealing for activating the implanted first conductivity type impurity and the second conductivity type impurity.

In the present invention, in the region at the predetermined depth from the wafer surface, the first conductivity type impurity and the second conductivity type impurity cancel each other out, thereby suppressing a change in impurity concentration. It is preferable that the threshold voltage changes with a change in impurity concentration.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the method of manufacturing a semiconductor device according to the present invention, in a preferred embodiment, a semiconductor device is formed immediately below a gate of a CMOS transistor formed on a plurality of wafers.
After performing impurity implantation for controlling the threshold value and annealing for activating the source and drain regions,
Boron is implanted so that the impurity concentration peaks in a region at a predetermined depth from the wafer surface, and approximately the same amount of phosphorus as boron is implanted so that the impurity concentration peaks in the same region. Threshold voltage is measured, and based on the measurement result, annealing is performed on a wafer that requires adjustment of the threshold voltage to activate boron and phosphorus. In a region at a predetermined depth from the wafer surface, impurities are removed. The change in the concentration is suppressed to maintain the reliability against hot electrons, and the threshold value on the wafer surface is arbitrarily adjusted by the change in the impurity concentration due to the annealing.

[0016]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 and 2 are process flow charts for explaining a method of manufacturing a semiconductor device according to one embodiment of the present invention, and a portion surrounded by a dotted line in the drawing is a characteristic portion of the present embodiment. FIG. 3 is a cross-sectional view showing the LDD cross-sectional structure of the transistor. FIG. 4 is a distribution diagram of the VT (hereinafter referred to as VTN) of the NMOS transistor and the VT (hereinafter referred to as VTP) of the PMOS transistor. FIG. 3 is a cross-sectional view showing a cross-sectional structure of an NMOS / PMOS transistor.

FIGS. 6 to 8 show impurity profiles immediately below the NMOS gate according to one embodiment of the present invention.
7 shows a state before ion implantation, FIG. 7 shows a state after ion implantation, and FIG. 8 shows a state after annealing. 9 to 11
Is an impurity profile immediately below the PMOS gate;
Similarly, FIG. 9 shows before ion implantation, and FIG.
FIG. 11 shows a state after annealing.

FIGS. 12 and 13 show the substrate bias characteristics of the NMOS according to one embodiment of the present invention. FIG. 12 shows the state before annealing, and FIG. 13 shows the state after annealing. 14 and 15 show the substrate bias characteristics of the PMOS. Similarly, FIG. 14 shows the state before annealing, and FIG. 15 shows the state after annealing.

As shown by the hatched portion in FIG. 4, when the VTN varies to a higher value and the VTP varies to a lower value in absolute value, a semiconductor device which does not satisfy the desired circuit characteristics will be described.
With reference to FIG. 1, a method for controlling VT by adding only three steps without reducing the reliability of NMOS transistors against hot electrons and without increasing the number of masks in the manufacturing process will be described with reference to FIG. This will be described below.

First, as shown in FIGS. 3 and 5, a normal CMOS transistor is formed on a silicon substrate 9 by NMO.
The S transistor is provided on the P well 11 and the PMOS transistor is provided on the N well 12, and each transistor is provided with a gate electrode, a source electrode and a drain electrode.

In this state, gate boron implantation for controlling the respective VTs is performed immediately below the gate 1 of the NMOS and PMOS transistors, and an anion for forming the source 5 and drain 4 regions is formed. As a result, the impurity profile is stable due to the resistance (S101). NMO at this time
FIG. 6 shows an impurity profile immediately below the gate 1 of the S transistor, and FIG. 9 shows an impurity profile of the PMOS transistor.

In this state, ion implantation for VT control is performed on the entire surface of the wafer without a mask (S10).
2) As in the case of the BIP integrated circuit or the GaAs integrated circuit shown in the conventional example, the VT can be sufficiently controlled by using only the donor impurity or the acceptor impurity.
Donor impurities or acceptor impurities are also implanted into the low concentration layer 6 of the transistor of FIG.

This low concentration layer 6 is provided for the purpose of relaxing a high electric field during the operation of the NMOS transistor.
Changing the impurity concentration changes the reliability of hot electrons that has been guaranteed conventionally.

Therefore, in the present embodiment, boron is added so that the donor impurity or the acceptor impurity (phosphorus in this embodiment) for VT control does not adversely affect the reliability due to hot electrons, and the concentration is canceled. I have to. In other words, the impurity peak in the substrate depth direction is
The acceleration energy of each impurity (phosphorus, boron) is adjusted so as to be about 0.1 μm from the silicon surface, and each impurity (phosphorus, boron) cancels out so that the VT of each transistor does not change before and after ion implantation. Matching do
The ion implantation is performed while adjusting the amount of ion implantation.

Here, the depth of the ion implantation is set to a peak of about 0.1 μm from the silicon surface which is most effective in alleviating impact ionization. 0.1 μm from the silicon surface
Is the region where the electric field is strongest because the substrate concentration is slightly higher than the other parts due to channel doping.

In this embodiment, the ion implantation of boron is performed.
For acceleration, acceleration energy of 100 (KeV),
-Amount 1E12 (a / cm^Two), Ion implantation of phosphorus
Regarding insertion, acceleration energy -250 (KeV),
Dose amount 5E12 (a / cm ^Two). At this time
Impurity profile directly under the gate in NMOS transistors
The file is shown in FIG.
FIG. 8 shows the impurity profile immediately below the gate.

Next, the VT of each transistor is measured (S
103), only those wafers whose VT is in the operation failure area 8 of the shaded area in FIG. 4 are selected (S104), and annealing is performed (S106). In the present embodiment, annealing is performed at 700 ° C. for 15 minutes as a step of S106.

Here, the state of the silicon substrate surface and the impurity state at a depth of about 0.1 μm from the silicon surface where impact ionization occurs will be described. First, on the silicon substrate surface, phosphorus for strengthening the N-type is piled up on the silicon substrate surface by annealing, and at the same time, boron, which has been ion-implanted, has a smaller diffusion coefficient than phosphorus, so that boron moves more than phosphorus. Is dull and diffused into the gate oxide film on the surface of the silicon substrate, and the P-type is weakened. Needless to say, this surface concentration change greatly affects VT control.

In addition, at a depth of about 0.1 μm from the silicon surface near the drain where impact ionization occurs, phosphorus and boron are ion-implanted so as to cancel each other out. There is no change. That is, there is no influence on the reliability reduction due to the hot electrons. FIG. 8 shows the impurity profile immediately below the gate in the annealed NMOS transistor.
FIG. 11 shows an impurity profile immediately below the gate in the PMOS transistor.

6 to 8 showing the impurity concentration of the NMOS transistor, it can be seen that only the surface concentration changes without changing the concentration at a depth of about 0.1 μm from the silicon surface. I understand.

Further, the change in surface concentration greatly affects VT control. FIGS. 12 to 15 show plots of VT at that time as substrate bias characteristics. FIG.
2 shows substrate bias characteristics before VTN annealing, FIG. 13 shows substrate bias characteristics after VTN annealing (700 ° C., 15 minutes), similarly, FIG. 14 shows substrate bias characteristics before VTP annealing, and FIG. After annealing (70
0 ° C. for 15 minutes), and changes before and after annealing of VTN (700 ° C. for 15 minutes) are shown in FIG. 12 and FIG.
The change before and after (0 ° C. for 15 minutes) can be understood from a comparison between FIG. 14 and FIG.

Thereafter, in step S105, an interlayer insulating film is deposited, and a wafer manufacturing process is completed through a contact hole and an aluminum wiring process.

As described above, after annealing of the source and drain regions of the CMOS transistor is completed,
By implanting phosphorus and boron impurities and annealing, the N-type is strengthened on the surface of the silicon substrate to change VT, and VT is changed at a depth of about 0.1 μm from the silicon surface where impact ionization occurs. The concentration change before and after the ion implantation for control or before and after the annealing for VT control can be minimized, so that the reliability due to hot electrons can be prevented from being changed.

In this embodiment, after annealing the source and the drain (S101), ion implantation for VT control is performed (S102), and after measuring the VT (S103), the measured VT value is used. Although the case where annealing is performed (S106) has been described, the present invention is not limited to the above embodiment, and as shown in FIG. 2, after annealing of the source and drain (S201), V
It is also possible to measure the T (S202), dope the ion implantation amount corresponding to the wafer requiring the VT control and the correction amount (S205), and anneal (S206).

[0035]

As described above, according to the method of manufacturing a semiconductor device of the present invention, phosphorus and boron are ion-implanted after the annealing of the source and drain regions of the CMOS transistor is completed. VT requires no additional mask, has little effect on manufacturing time and cost, and requires only three additional steps.
Can be controlled.

Further, according to the present invention, even if VT control is performed, the reliability due to hot electrons is not reduced, and the production margin of a device having a high VT sensitivity in terms of a circuit can be increased. To play.

[Brief description of the drawings]

FIG. 1 is a process flow chart for explaining a method of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a process flow chart for explaining another method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 3 shows an LDD of a transistor according to one embodiment of the present invention.
It is sectional drawing which shows a cross-sectional structure.

FIG. 4 shows VTN- of the semiconductor device according to one embodiment of the present invention;
It is a distribution map of VTP.

FIG. 5 shows an NMOS of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view showing a cross-sectional structure of a / PMOS transistor.

FIG. 6 is an impurity profile before ion implantation immediately below an NMOS gate according to one embodiment of the present invention.

FIG. 7 is an impurity profile after ion implantation immediately below an NMOS gate according to one embodiment of the present invention.

FIG. 8 is an impurity profile immediately below an NMOS gate after annealing according to one embodiment of the present invention.

FIG. 9 is an impurity profile immediately before a PMOS gate before ion implantation according to an embodiment of the present invention.

FIG. 10 is an impurity profile after ion implantation immediately below a PMOS gate according to one embodiment of the present invention.

FIG. 11 is an impurity profile immediately below a PMOS gate after annealing according to one embodiment of the present invention.

FIG. 12 shows substrate bias characteristics of an NMOS according to an embodiment of the present invention before annealing.

FIG. 13 is a graph showing substrate bias characteristics after annealing of an NMOS according to an embodiment of the present invention.

FIG. 14 shows substrate bias characteristics before annealing of a PMOS according to an embodiment of the present invention.

FIG. 15 is a graph showing substrate bias characteristics after annealing of a PMOS according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate 2 Side wall 3 Gate oxide film 4 Drain diffusion layer 5 Source diffusion layer 6 Low concentration layer 7 Operable area 8 Malfunction area 9 Silicon substrate 10 Locos oxide film 11 P well 12 N well

Claims (7)

[Claims] An impurity for controlling a threshold is implanted immediately below a gate of a CMOS transistor formed on a wafer, and then annealing for activating a source and a drain region is performed. (A) implanting a predetermined amount of a first conductivity type impurity such that the impurity concentration has a peak at a predetermined depth from the wafer surface after the activation annealing; A) a step of implanting an impurity of the second conductivity type substantially equal to the impurity of the first conductivity type such that the impurity concentration peaks at the predetermined depth from the wafer surface after the implantation of the first conductivity type impurity. (C) measuring the threshold voltage of the wafer; (d) adjusting the threshold voltage based on the measurement result of the threshold voltage, if necessary, based on the measurement result of the threshold voltage. 1st conductivity type A step of performing annealing for activating the pure substance and the second conductivity type impurity. 2. The semiconductor device according to claim 1, wherein an impurity for controlling a threshold value is implanted immediately below a gate of the CMOS transistor formed on the wafer, and then annealing for activating the source and drain regions is performed. (A) measuring the threshold voltage of the wafer after the activation annealing; and (b) adjusting the threshold voltage based on the measurement result of the threshold voltage. When necessary, so that the impurity concentration peaks at a predetermined depth from the wafer surface,
Implanting a predetermined amount of the first conductivity type impurity; and (c) after the first conductivity type impurity implantation, the first conductivity type impurity is so formed as to have a peak impurity concentration at the predetermined depth from the wafer surface. Implanting an impurity of the second conductivity type in an amount substantially equal to the type impurity; and (d) performing an annealing for activating the implanted first conductivity type impurity and the second conductivity type impurity. A method for manufacturing a semiconductor device, comprising at least: 3. In a region at a predetermined depth from the wafer surface, the first conductivity type impurity and the second conductivity type impurity cancel each other, thereby suppressing a change in impurity concentration. 3. The method according to claim 1, wherein the threshold voltage changes according to the change. 4. A depth from the wafer surface, wherein the first conductivity type impurity and the second conductivity type impurity cancel each other to suppress a change in impurity concentration, and the depth from the wafer surface is set to approximately 0.1 μm. 4. The method for manufacturing a semiconductor device according to claim 3, wherein: 5. The method of manufacturing a semiconductor device according to claim 3, wherein boron is used as said first conductivity type impurity and phosphorus is used as said second conductivity type impurity. 6. The method according to claim 1, wherein the first conductivity type impurity and the second conductivity type impurity are implanted into the entire surface of the wafer. 7. An annealing device for activating said first conductivity type impurities and said second conductivity type impurities is required to adjust said threshold voltage based on the measurement result of said threshold voltage. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed only on a simple wafer.