JP3381693B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an LDD structure (LihgtlyDop).
The present invention relates to a method for manufacturing a semiconductor device suitable for controlling the threshold voltage of a MOS transistor of ed drain).

[0002]

2. Description of the Related Art In order to prevent variations in threshold voltage (hereinafter referred to as VT) in a conventional CMOS transistor, control for minimizing variations in various manufacturing apparatuses, reduction in heat treatment temperature, and heat treatment time are required. This was done by a method such as minimizing the variation of the impurity profile due to the shortening of.

Further, with the recent miniaturization of elements, the sensitivity of VT to the gate length of a transistor is high, so that the amount of ion implantation and the heat treatment time are adjusted depending on the variation of the gate length. We are taking action.

In the case of a BIP integrated circuit or a GaAs integrated circuit, a technique of controlling the electrical characteristics of the active layer by measuring the electrical characteristics of the active layer and changing the annealing time based on the measurement result is used. Has been.

[0005]

However, the above-described conventional method for preventing VT variations does not exceed the desired VT even if variations in various manufacturing apparatuses and heat treatment measures are adopted.
A variation of about 10% will occur.

Further, even in the method of adjusting the ion implantation amount and the heat treatment time corresponding to the variation in the gate length, the variation in the VT does not depend only on the gate length, so that the VT is surely achieved. Cannot be controlled.

Further, as in the case of the BIP integrated circuit or the GaAs integrated circuit, the method for controlling the electrical characteristics of the active layer by annealing after measuring the electrical characteristics of the active layer is as follows. Therefore, it cannot be applied to a CMOS circuit.

That is, unlike the CMOS circuit, the BIP integrated circuit and the GaAs integrated circuit are not required to have a complementary operation, so that the BIP integrated circuit has N
In the PN transistor and GaAs integrated circuit, if the N-channel transistor can be controlled without variation, P
Even if there is some variation in the NP transistor and the P-channel transistor, there is no problem in terms of circuit characteristics.

However, in a CMOS circuit, both an N-channel transistor (hereinafter referred to as an NMOS transistor) and a P-channel transistor (hereinafter referred to as a PMOS transistor) play a large role in the circuit operation, and therefore, the NPN transistor of the BIP integrated circuit. This is because a transistor control on only one side, such as an N-channel transistor of a GaAs integrated circuit, causes a malfunction or cannot satisfy circuit characteristics.

Regarding the process, the LDD shown in FIG.
As shown in the cross-sectional view of the transistor having the structure, the low-concentration layer 6 is provided on the drain electrode (also on the source electrode due to the structure) for buffering the drain electric field.
In the method of ion-implanting impurities for controlling hFE or VT like an integrated circuit and annealing,
In the case of an OS transistor, the concentration at the place where the electric field generated near the drain of the NMOS transistor becomes the highest (about 0.1 μm from the silicon surface) changes, and the reliability against hot electrons that has been guaranteed in the past changes. The problem arises.

The present invention has been made in view of the above problems, and its main purpose is to provide a method of manufacturing a semiconductor device capable of controlling a threshold voltage without impairing reliability against hot electrons. To provide.

[0012]

In order to achieve the above object, according to a first aspect of the present invention, an impurity for controlling a threshold value is implanted just under a gate of a CMOS transistor formed on a wafer. Then, in a method of manufacturing a semiconductor device for annealing for activating the source and drain regions, (a) after the activation annealing, the impurity concentration peaks at a predetermined depth from the wafer surface. And (b) after the first conductivity type impurity is injected, the impurity concentration has a peak at the predetermined depth from the wafer surface. a step of implanting second conductivity type impurity of the first conductivity type impurity and equal correct amount, and measuring the threshold voltage of (c) the wafer, the; (d) the threshold voltage Based on measurement results , Wherein when the adjustment of the threshold voltage is required, annealing for activating the first conductivity type impurity and the second conductivity type impurities said injection - have, and performing Le least, the first 1 conductivity type impurities
Ron is used, and phosphorus is used as the second conductivity type impurity .

According to a second aspect of the present invention, the source and drain regions are activated after implanting an impurity for controlling a threshold value just below the gate of a CMOS transistor formed on a wafer. (A) measuring the threshold voltage of the wafer after the activation annealing in a method of manufacturing a semiconductor device for annealing; and (b)
When it is necessary to adjust the threshold voltage based on the measurement result of the threshold voltage, a predetermined amount of the first conductivity is set so that the impurity concentration has a peak at a predetermined depth from the wafer surface. implanting impurity, (c) the first conductivity type after impurity implantation, so that the impurity concentration becomes a peak at the predetermined depth from the wafer surface, of the first conductivity type impurity and equal correct amount implanting an impurity of a second conductivity type, annealing for activating (d) is the implanted first conductivity type impurity and the second conductivity type impurity - having at least a step of performing Le, the first As one conductivity type impurity
Boron and phosphorus as the second conductivity type impurity.
There is something.

In the present invention, the impurity of the first conductivity type and the impurity of the second conductivity type cancel each other out in a region of the predetermined depth from the wafer surface to suppress a change in impurity concentration, and on the wafer surface, It is preferable that the threshold voltage changes due to a change in impurity concentration.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention, the semiconductor device manufacturing method directly below the gates of CMOS transistors formed on a plurality of wafers,
After performing impurity implantation for controlling the threshold value and annealing for activating the source and drain regions,
Impurity concentration by implanting boron to a peak from the wafer surface in a region at a predetermined depth, so that the impurity concentration is the peak in the same region, by implanting phosphorus, boron and equal correct amount, the teeth of the wafer The threshold voltage is measured and the wafer whose threshold voltage needs to be adjusted is annealed to activate boron and phosphorus based on the measurement result. While suppressing the change in concentration to maintain reliability against hot electrons, the threshold value is arbitrarily adjusted on the wafer surface by changing the impurity concentration due to annealing.

[0016]

EXAMPLES In order to describe the above-described embodiment of the present invention in more detail, one example of the present invention will be described below with reference to FIGS. 1 to 15. 1 and 2 are process flow charts for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, and a portion surrounded by a dotted line in the drawings is a characteristic portion of the present embodiment. 3 is a sectional view showing the LDD sectional structure of the transistor, FIG. 4 is a distribution diagram of the VT of the NMOS transistor (hereinafter referred to as VTN) and the VT of the PMOS transistor (hereinafter referred to as VTP), and FIG. It is sectional drawing which shows the cross-section of NMOS / PMOS transistor.

6 to 8 are impurity profiles just below the NMOS gate according to the embodiment of the present invention.
Shows the state before ion implantation, FIG. 7 shows the state after ion implantation, and FIG. 8 shows the state after annealing. In addition, FIGS.
Is an impurity profile directly under the PMOS gate,
Similarly, FIG. 9 shows before ion implantation, and FIG. 10 shows after ion implantation.
FIG. 11 shows the state after annealing.

12 and 13 show the substrate bias characteristics of the NMOS according to one embodiment of the present invention. FIG. 12 shows the state before annealing and FIG. 13 shows the state after annealing. 14 and 15 show the substrate bias characteristics of the PMOS. Similarly, FIG. 14 shows the state before annealing and FIG. 15 shows the state after annealing.

As shown by the hatched portion in FIG. 4, in the case where the VTN is higher and the VTP is lower in absolute value, the semiconductor device which does not satisfy the desired circuit characteristics is
Referring to FIG. 1, a method of controlling the VT without degrading the reliability of the hot transistor of the NMOS transistor and further adding only three steps without increasing the mask in the manufacturing process is described. This will be described below.

First, as shown in FIG. 3 and FIG. 5, a normal CMOS transistor is formed on a silicon substrate 9 by an NMO.
The S transistor is provided on the P well 11, the PMOS transistor is provided on the N well 12, and a gate electrode, a source electrode and a drain electrode are provided on each transistor.

In this state, gate boron implantation for controlling the VT of each of the NMOS and PMOS transistors is performed immediately below the gate 1, and the source 5 and drain 4 regions are formed as an anisotropy. The impurity profile is stable due to the above (S101). NMO at this time
FIG. 6 shows the impurity profile immediately below the gate 1 in the S transistor, and FIG. 9 shows the impurity profile in the PMOS transistor.

In this state, ion implantation for VT control is performed on the entire surface of the wafer without a mask (S10).
2) Similar to the BIP integrated circuit and the GaAs integrated circuit shown in the conventional example, the VT can be sufficiently controlled even if the impurities are only donor impurities or acceptor impurities.
Donor impurities or acceptor impurities are also implanted into the low-concentration layer 6 of the transistor of FIG.

Since the low concentration layer 6 is provided for the purpose of relaxing a high electric field during the operation of the NMOS transistor,
Changing the impurity concentration changes the reliability of hot electrons that has been guaranteed in the past.

Therefore, in this embodiment, boron is added so that the donor or acceptor impurity for VT control (phosphorus in this embodiment) does not adversely affect the reliability due to hot electrons, and the concentration is canceled. I have to. That is, the peak of impurities in the substrate depth direction is
The acceleration energy of each impurity (phosphorus, boron) is adjusted so that it is approximately 0.1 μm from the silicon surface, and the mutual impurities (phosphorus, boron) are canceled so that the VT of each transistor does not change before and after ion implantation. Do-it
Ion implantation is performed after adjusting the amount.

Here, the ion implantation depth is set to a peak of about 0.1 μm from the silicon surface which is most effective for impact ionization relaxation. 0.1 μm from the silicon surface
Is the region where the electric field is the strongest because the substrate concentration is slightly higher than the other portions due to channel doping.

In this embodiment, boron ion implantation is performed.
As for inclusion, acceleration energy-100 (KeV),
-Amount 1E12 (a / cm²), And then phosphorus ion
Regarding chilling, acceleration energy-250 (KeV),
Dose amount 5E12 (a / cm ²) Went. At this time
Impurity profile directly under the gate in NMOS transistor
Figure 7 shows the file for the PMOS transistor
FIG. 8 shows the impurity profile immediately below the gate.

Next, the VT of each transistor is measured (S
103), only those wafers whose VT is in the defective operation area 8 in the shaded area in FIG. 4 are selected (S104) and annealed (S106). In this example, as the step of S106, annealing was performed at 700 ° C. for 15 minutes.

Here, the state of the silicon substrate surface and the state of impurities having a depth of about 0.1 μm from the silicon surface where impact ionization occurs will be described. First, on the silicon substrate surface, phosphorus for strengthening the N-type is piled up on the silicon substrate surface by annealing, and at the same time boron ion-implanted moves more than phosphorus because it has a smaller diffusion coefficient than phosphorus. Is dull, and on the surface of the silicon substrate, it diffuses into the gate oxide film and the P-type is weakened. It goes without saying that this change in the surface concentration has a large influence on the VT control.

At a depth of about 0.1 μm from the silicon surface where impact ionization occurs in the vicinity of the drain, phosphorus and boron are ion-implanted so as to cancel each other. There is no change. In other words, there is no effect on reliability deterioration due to hot electrons. FIG. 8 shows the impurity profile immediately below the gate in the NMOS transistor after annealing.
FIG. 11 shows the impurity profile just below the gate in the PMOS transistor.

Thus, paying attention to FIGS. 6 to 8 showing the impurity concentration of the NMOS transistor, it is found that only the surface concentration changes without changing the concentration at a depth of about 0.1 μm from the silicon surface. I understand.

Further, the change in the concentration of the surface has a great influence on the VT control, and VT at that time is plotted as the substrate bias characteristic and shown in FIGS. 12 to 15. Figure 1
2 shows the substrate bias characteristic before annealing of VTN, FIG. 13 shows the substrate bias characteristic after annealing of VTN (at 700 ° C. for 15 minutes), similarly, FIG. 14 shows the substrate bias characteristic before annealing of VTP, and FIG. After annealing (70
The substrate bias characteristics at 0 ° C. for 15 minutes) are shown respectively, and the change before and after the annealing of VTN (at 700 ° C. for 15 minutes) is compared with the comparison of FIGS.
The change before and after 0 ° C. for 15 minutes can be understood by comparing FIG. 14 and FIG.

Thereafter, in step S105, an interlayer insulating film is deposited, a contact hole and an aluminum wiring process are performed, and the wafer manufacturing process is completed.

After the annealing of the source and drain regions of the CMOS transistor is completed, as described above,
Impurities of phosphorus and boron are ion-implanted and annealed to strengthen the N-type on the surface of the silicon substrate to change VT, and VT is generated at a depth of about 0.1 μm from the silicon surface where impact ionization occurs. It is possible to minimize the concentration change before and after the control ion implantation or before and after the VT control anneal, and prevent the reliability due to hot electrons from changing.

In the present embodiment, after the source and drain are annealed (S101), ion implantation for VT control is performed (S102), and VT measurement is performed (S103), depending on the measured VT value. Although the case of performing the annealing (S106) has been described, the present invention is not limited to the above-described embodiment, and as shown in FIG. 2, after the source and the drain are annealed (S201), V
It is also possible to adopt a configuration in which T is measured (S202), a wafer requiring VT control and an ion implantation amount corresponding to the correction amount thereof are doped (S205) and annealed (S206).

[0035]

As described above, according to the method of manufacturing the semiconductor device of the present invention, phosphorus and boron are ion-implanted after the annealing of the source and drain regions of the CMOS transistor is completed, and the annealing is performed. By adding a mask, an additional mask is not required, and the manufacturing time and cost are hardly affected.
There is an effect that can be controlled.

Further, according to the present invention, even if VT control is performed, reliability due to hot electrons is not lowered, and the manufacturing margin of a device having a high VT sensitivity in terms of a circuit can be increased. Play.

[Brief description of drawings]

FIG. 1 is a process flow chart for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process flow chart for explaining another manufacturing method of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is an LDD of a transistor according to an embodiment of the present invention.
It is sectional drawing which shows sectional structure.

FIG. 4 is a VTN- of a semiconductor device according to an embodiment of the present invention.
It is a distribution diagram of VTP.

FIG. 5 is an NMOS of a semiconductor device according to an embodiment of the present invention.
6 is a cross-sectional view showing a cross-sectional structure of a / PMOS transistor. FIG.

FIG. 6 is an impurity profile before ion implantation just below an NMOS gate according to an embodiment of the present invention.

FIG. 7 is an impurity profile after ion implantation just below an NMOS gate according to an embodiment of the present invention.

FIG. 8 is an impurity profile after annealing just below an NMOS gate according to an embodiment of the present invention.

FIG. 9 is an impurity profile before ion implantation just below a PMOS gate according to an embodiment of the present invention.

FIG. 10 is an impurity profile after ion implantation just below a PMOS gate according to an embodiment of the present invention.

FIG. 11 is an impurity profile after annealing just under a PMOS gate according to an embodiment of the present invention.

FIG. 12 is a substrate bias characteristic before annealing of the NMOS according to the embodiment of the present invention.

FIG. 13 is a substrate bias characteristic after annealing of the NMOS according to the embodiment of the present invention.

FIG. 14 is a substrate bias characteristic before annealing of a PMOS according to an embodiment of the present invention.

FIG. 15 is a substrate bias characteristic after annealing of a PMOS according to an embodiment of the present invention.

[Explanation of symbols]

1 gate 2 sidewalls 3 Gate oxide film 4 Drain diffusion layer 5 Source diffusion layer 6 Low concentration layer 7 Operable area 8 Malfunction area 9 Silicon substrate 10 Locos oxide film 11 P-well 12 N wells

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Claims (6)

(57) [Claims] 1. A semiconductor device in which an impurity for controlling a threshold value is implanted just below the gate of a CMOS transistor formed on a wafer and then annealed for activating the source and drain regions. In the manufacturing method, (a) after the activation annealing, a step of injecting a predetermined amount of the first conductivity type impurity so that the impurity concentration has a peak at a predetermined depth from the wafer surface; ) the first conductivity type after impurity implantation, the as the impurity concentration is a peak in the from the wafer surface a predetermined depth, a step of implanting second conductivity type impurity of the first conductivity type impurity and equal correct amount And (c) a step of measuring the threshold voltage of the wafer, and (d) an injection of the threshold voltage when adjustment of the threshold voltage is necessary based on the measurement result of the threshold voltage. First conductivity type impurity Things and annealing for activating the second conductivity type impurity - has a step of performing Le, at least, using boron as the first conductivity type impurity, the second conductive
A method of manufacturing a semiconductor device, wherein phosphorus is used as an electric impurity . 2. A semiconductor device in which an impurity for controlling a threshold value is implanted just below the gate of a CMOS transistor formed on a wafer and then annealed for activating the source and drain regions. In the manufacturing method, (a) the step of measuring the threshold voltage of the wafer after the activation annealing, and (b) the adjustment of the threshold voltage based on the measurement result of the threshold voltage. If necessary, so that the impurity concentration has a peak at a predetermined depth from the wafer surface,
Implanting a predetermined amount of impurities of the first conductivity type, and (c) implanting the impurities of the first conductivity type so that the impurity concentration reaches a peak at a predetermined depth from the wafer surface. implanting impurity and equal correct amount of the second conductivity type impurity, annealing for activating (d) is the implanted first conductivity type impurity and the second conductivity type impurity - and performing Le, At least , boron is used as the first conductivity type impurity, and the second conductivity type is used.
A method of manufacturing a semiconductor device, wherein phosphorus is used as an electric impurity . 3. In the region of the predetermined depth from the wafer surface, the impurity of the first conductivity type and the impurity of the second conductivity type cancel each other to suppress the change of the impurity concentration, and the impurity concentration of the wafer surface is suppressed. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the threshold voltage changes due to the change. 4. The depth from the wafer surface where the first conductivity type impurity and the second conductivity type impurity cancel each other out to suppress a change in impurity concentration is 0 . The method for manufacturing a semiconductor device according to claim 3, wherein the thickness is set to 1 μm. The method according to claim 5, wherein said first conductivity type impurity and the second conductivity type impurity, the wafer - a method of manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that injecting the entire surface. 6. The threshold voltage of an anneal for activating the first conductivity type impurity and the second conductivity type impurity needs to be adjusted based on a measurement result of the threshold voltage. 5. The method according to claim 1, wherein the process is performed only on a different wafer.
6. The method for manufacturing a semiconductor device according to any one of 5 above.