JPS62131573A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form an element reduced in size, by a constitution wherein a contact between a semiconductor and a metal in the first and second impurity high-concentration regions has an angle with respect to the surface of a substrate. CONSTITUTION:On a single crystal Si film 302, which is formed on an insulating substrate 301, a resist pattern 303 is formed. With this pattern as a mask, an island structure is formed by dry etching. Then an SiO2 film 304 is deposited to a thickness, which is approximately flash with that of the Si film 302. A hole 305 and a hole 306 are formed by etching. After a conductor metal film is formed, the surface is made to be approximately flat plane by a flattening etching method again. Then, a gate oxide film 309 is formed. A thin conductor film is deposited, and a gate electrode 310 is formed by photolithography and dry etching. With the gate electrode 310 as a mask, ions are implanted, and a source 311 and a drain 312 are formed by a self-aligning mode. Thereafter, source and drain taking out electrodes 313 and 314 and their wiring parts are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the structure of a microscopic semiconductor device suitable for constructing an ultra-highly integrated circuit.

[Background of the invention]

In the conventional highly integrated semi-four body circuit, for example, as shown in Fig. 2(a), (
An MO5 field effect transistor as shown in b) was used as its element.

(a) is a schematic plan view thereof, and (b) is A- in (a).
FIG. 3 is a perspective view showing a cross section taken along line A'.

The device is formed on the surface of the semiconductor substrate 200, and is generally manufactured through the following steps. That is, first, a thick field oxide film 201 is formed by zero selective oxidation, and then a gate oxide film 202 is formed. A layer of polycrystalline silicon or metal silicide is formed on the second layer of this structure, and is etched away leaving the gate 203 and its wiring portion. Using this gate 203 as a mask, an impurity of a conductivity type opposite to that of the substrate is introduced by ion implantation, and the source 204. Each region of the drain 205 is formed. Sauce 2 thus formed
04, contact hole 20 in the surface oxide film of the drain 205
6.degree. 207 is formed by etching so as to be included in each region, and an electrode metal layer is formed by vapor deposition or the like.

Thereafter, the metal layer is etched away leaving the source electrode 208, drain electrode 209, and their interconnections, thereby forming a structure as shown in FIGS. 2(a) and 2(b). In the actual process, there are other steps such as additional ion implantation and oxidation such as threshold voltage control, and steps for multilayer interconnection, but they are not directly related to the content of the present invention, so their explanation will be omitted.

In a MOSFET with such a conventional structure, the connection between the source/drain region formed by introducing impurities and the metal wiring layer is made through a contact hole, and the contact surface is in a plane parallel to the substrate surface. .

In general, the planar shape and dimensions of a semiconductor element are designed according to a so-called layout rule, which consists of a minimum dimension that can be processed and a margin that allows for dimensional changes due to processing. Minimum processing dimensions are usually applied to the length of the gate 203 and the dimensions of the contact holes 206 and 207. When forming elements.

Gate 203 and source/drain electrodes 208, 20
The distance between the contact hole 206.2 and the contact hole 206.
It is also necessary to consider the overlap margin between 07 and the electrode, and to form a single transistor, the minimum processing size of about 10
I had to prepare it twice as long.

This restriction is essential to the conventional structure and manufacturing method, and it has been difficult to reduce this when attempting to make contact between the semiconductor and metal at the contact portion in a plane parallel to the substrate surface. .

In order to improve the semiconductor-metal contact characteristics, a method of filling metal into pores drilled in a substrate was proposed, for example, in JP-A-60
-103671 and JP-A No. 60-98667, etc., but this method is mainly aimed at increasing the contact area, and is not a method that can reduce the device structure beyond the limit of the minimum processing size. do not have.

[Purpose of the invention]

An object of the present invention is to provide an element structure that allows a smaller element to be formed even if conventional manufacturing methods are used. Another object of the present invention is to provide an improved current path and further reduce parasitic resistance by using a novel lead-out electrode structure of the device, thereby realizing a semiconductor device with more excellent characteristics.

[Summary of the invention]

The present invention provides a semiconductor device having first and second high impurity concentration regions provided in a semiconductor layer and a first electrode for controlling conductance between the regions, in which dimensional constraints in a conventional structure are overcome. In view of the fact that the contact between the semiconductor and the metal in the first and second high impurity concentration regions (source/drain regions) is formed parallel to the substrate surface, that is, the plane in which the channel is formed, The contact described above is configured in a plane having an angle to the channel forming surface, so that the area required for the contact and the margin for pattern alignment on the main surface of the substrate are substantially unnecessary, or It is something that shrinks.

[Embodiments of the invention]

FIGS. 1(a) and (b) show an embodiment of the present invention as shown in FIG. 2(a).
) and (b), in which (a) is a plan view,
(b) is a perspective view showing a cross section taken along line AA' in (a).

In this embodiment, substrate 100 is an insulator such as quartz, sapphire or spinel. The semiconductor region 101 has an island shape surrounded by an insulating film 102 . A gate electrode conductor 104 is provided via a gate insulating film 103, and the source 105 and drain 106 regions provided at both ends of the semiconductor region 101 are provided at the same level (height) as the semiconductor region. It is connected to extraction electrodes 107 and 108 via conductor regions.

Source and drain regions 105°106 in the semiconductor layer
The contact with the extraction electrodes 107 and 108 is made on surfaces 110 and 11 that are substantially perpendicular to the channel forming plane 109 of the main surface of the semiconductor.
1, so that the semiconductor layer and the contact conductor are in the same level.

This semiconductor device is formed, for example, by the following steps. FIGS. 3(a) to 3(h) are cross-sectional views showing the steps, which will be explained in detail below. First, as shown in FIG. 3(a), a single crystal Si film 302 having a thickness of 0.5#I11 is formed on an insulating substrate 301 by the well-known SO2 technique. This single-crystal Si film 302 does not need to be completely single-crystal over a wide area; it only needs to be a good single-crystal in the area where a device is to be made, and this can be easily achieved using known techniques. . Note that in this case, the Si film is doped to be p-type.

Next, a resist pattern 303 that is slightly larger than the desired island-like Si is formed on the single-crystal SL film 302, and using this as a mask, the S1 film is removed by dry etching to form an island-like structure (see FIG. 3(b)). )).

Next, Si was deposited on top of this by chemical vapor deposition (CVD).
o. A film 304 is deposited, and unnecessary Sio2 film is removed by, for example, a known planarization method such as etch-back method, so that the thickness becomes the same as that of the Si film 302 (FIG. 3(c)).

Next, the Si film and Si
o. The film is removed again by dry etching to form holes 305 and 306 to be filled with contact conductors (FIG. 3(d)).

Next, after forming a conductive metal film by a method such as sputtering or CVD, the Si
Membrane 3021 for separation Sio, membrane 304. : Form a structure in which the surfaces of the contact conductors 307, 308, etc. are substantially on the same plane (FIG. 3(e)).

Next, a gate oxide film is formed, but here the conventional L
The thermal oxidation method used for SI is the contact conductor 307
, 308 is oxidized in its entirety, so it cannot be applied. However, according to the low-temperature oxidation method using microwave plasma developed by the present inventors (Japanese Patent Application Laid-Open No. 136318/1983),
Even in a system where Si and a contact conductor coexist, it is possible to thinly oxidize only the surface exposed to plasma.

In this way, a gate oxide film 309 is formed at a temperature of about 580° C. (FIG. 3(f)).

Next, a conductive thin film to form a gate electrode is deposited, and a gate electrode 310 is formed by photolithography and dry etching. Furthermore, this gate electrode 310
As (arsenic) is implanted using the ion implantation method as a mask, and the source 311 and drain 312 are self-aligned.
is formed. At this time, ions are implanted into other regions at the same time, but this does not pose a problem in terms of the characteristics of the device. The implanted ion dose is I x 10"am-" or more, and the implanted region becomes amorphous, but the crystallinity is restored by solid phase growth by heat treatment at 600°C, and the contact area between the semiconductor and the contact conductor is It is possible to suppress the reaction to a small extent (Fig. 3 (g)).

Next, the thin oxide film on the contact conductor is removed by etching using a mask, and a conductor layer for lead electrodes and wiring is deposited, and then a desired pattern is formed by photolithography and dry etching again, and the source and drain layers are formed as shown in the figure. The lead electrodes 313 and 314 and their wiring portions are formed, and the structure shown in FIGS. 1(a) and 1(b) is completed.

Focusing on the dimensions of each part, the contact holes 305 and 306 formed in FIG. 3(d) can be formed with the minimum processing size S, and the gate electrode 310 formed in FIG. It is also possible to form S.

The gap between the extraction electrodes 313, 314 and the gate electrode 310 formed in (h) is essentially a dimension adjustment margin m
It is sufficient if the source 311 and drain 3 formed in (g) are twice as long as S + m.
The length of 12 is based on S. The contact conductors 307 and 308 and the extraction electrodes 313 and 314 in FIG. There is no harm in overlapping with this.

Therefore, even a single transistor can be formed with a length of 7S or less, and can be reduced by 30% compared to the length of IO8 in the conventional process.

This structure becomes even more advantageous when configuring a circuit including wiring between transistors. FIG. 4(a) is a sectional view showing an example of a CMOS inverter constructed using this structure, and FIG. 4(b) is a diagram showing an example of its planar layout. In FIG. 4(a), an insulator is used for the substrate 401, and a common gate 402 formed on it
, 402', the transistor 415 on the side driven by the left gate 402 has already been activated in FIGS. 1(a) and 1(b).
), which includes a semiconductor region 403, a source 404, a drain 405, contact conductors 406, 407 . Extraction electrode 408.409
is as described above. The transistor 416 on the side driven by the right gate 402' is an n-channel 1 transistor, and the semiconductor region 410 is doped with n-type impurities at the stage of forming the Sr island. p-type source 41
2 and the drain 411 are formed by B (boron) ion implantation. Drain contact conductor 407
This is common to the drain contact conductor of the n-channel 1-range SF 415, and has a structure in which both end faces are in contact with the conductor sandwiched therebetween. The contact conductor 413 and extraction electrode 414 of the p-channel source 412 are the contact conductor 406 and extraction @pole 40 of the n-channel source 404.
It is symmetrical to 8.

When contact is made on the upper surface of the source and drain as in the conventional structure, a contact region is provided to be included in the source and drain, and an isolation region and a raindrop are provided between the n-channel transistor and the n-channel 1 helangistor. Since it is necessary to provide a connection wiring between them, it is impossible to configure the F) channel transistor and the n-channel transistor with the minimum processing size spacing as in this embodiment. In this embodiment, the CMOS inverter is constructed with a length of 113, and can be constructed with a width approximately 1/2 that of the conventional method. In Figure 4(c).

This is another embodiment in which the common gate 402' and the output terminal 409' are laid out in an easy-to-use manner, but it will be understood that in this case the required area is further reduced.

That is, (C) is a layout in which the n-channel transistor and the n-channel transistor in (b) are rotated by 90°. In the figure, 408' is the source lead electrode of the n-channel transistor, and 414' is the source lead electrode of the n-channel transistor. Note that FIG. 4(d) is a circuit diagram of the CMOS inverter shown in FIGS. 4(a) to (c).

Although the present invention is effective in reducing the size of an element even when applied to an element in which the active area is laid out in a two-dimensional manner as in the above embodiment, it is even more effective in reducing the size of an element in which the active area is arranged in three dimensions. Great effect. Next, an example will be described.

FIGS. 5(a) and 5(b) show an embodiment in which the present invention is applied to a stacked CMO 8, where (a) is a sectional view and (b) is a circuit diagram showing a three-dimensional configuration of wiring.

On the insulating substrate 500, there is a p-type semiconductor region 501 forming a channel region of a first transistor (rx channel type), and a drain 502 formed of an n1-type region.
and a source 503 are provided, and contact conductors 504 and 505 in contact with the source 503 at the side wall end face of the n+ region are formed in the same layer. Other areas within the above layer are
Wiring between elements provided as necessary, especially contact conductors 504 and 505, is a power line φVo that is configured by extending in a direction perpendicular to the plane of the paper in FIG. 5(a) (FIG. 5)
, and a part of the output line φV♂ are provided with an insulating dielectric film 506 formed to have approximately the same thickness. A gate electrode 508 is provided in this first layer semiconductor region via a gate insulating film 507, and in contact with the drain contact conductor 504, a conductor 509 for connecting upper and lower transistors and for output line φv1 is also provided in the same layer. located within. In the other regions of this layer, an insulating dielectric film 510 between the upper and lower transistors is similarly formed with approximately the same thickness. Note that, in this layer, a relay region (not shown) for establishing conduction from the top surface to the power supply line φv0 and an input line φVl (not shown) connected to the common gate 508 are also provided in the same way as the conductor 509. In the uppermost layer, an n-type semiconductor region 511 constituting a second transistor (p-channel type) is connected to a common gate 5.
08 and a gate insulating film 512, and both end portions thereof are a source 513 and a drain 514 which are constituted by ρ" regions. Contact conductors 515. 5
16 are provided.

A contact conductor 516 in the drain portion is connected to the upper and lower transistor connection/output lines φv. An insulating dielectric film 517 is provided in another region within the same layer. It will be easily understood that these structures are formed by applying the steps explained in FIG.

By adopting the above structure, it becomes possible to fabricate a CMOS inverter circuit in a smaller area than the conventional structure using the same minimum processing size technology as the conventional structure.

In the embodiments described above, an insulating substrate was used, but as shown in FIG. Needless to say, it can also be applied to

Further, as shown in FIG. 7, an element is formed on an insulating film formed on the surface of a semiconductor substrate 700, and a part of the semiconductor region of the element is formed through a hole 702 provided in the insulating film. Is it composed of crystals that are continuous with the underlying semiconductor substrate?
Alternatively, they may be electrically connected.

By the way, up until now, the morphological features of the present invention have been explained mainly from the viewpoint of miniaturization of semiconductor elements, but below, the effects of the present invention on electrical characteristics will also be explained.

FIG. 8 is a schematic partial cross-sectional view of the vicinity of the source of a MOSFET having a conventional structure. A substrate 800 is of p-type, and a gate electrode 802 is provided with a gate insulating film 801 interposed therebetween.

In the strong inversion region, a channel 803 is formed on the substrate surface,
Electron current flows from the extraction electrode 804 to the metal-semiconductor contact 80
5 into the source 806 of the heavily doped n1 region,
The current flows along the current line 807 as shown. in this case,
Since the metal-semiconductor contact 805 is almost coplanar with the channel 803, the current lines are dense at the substrate surface and there is less bulk contribution in the source region 806, resulting in a high concentration of S1806 with a high resistivity compared to the metal. resistance cannot be ignored.

Furthermore, since the current is concentrated near the channel of the contact portion, the influence of contact resistance is also large.

FIG. 9 is a diagram corresponding to FIG. 8 in which the present invention is applied, but the metal-semiconductor contact 905 is connected to the channel 903.
It can be seen that the current line also effectively contributes to the bulk of the source region. Since the fI & flow path is expanded, the influence of contact resistance is also reduced, source resistance parasitic to the device is reduced, and the operating speed of the device is improved.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce the size of the device compared to the conventional method even if the same minimum processing size technology as the conventional method is used, and the current path can be reduced by improving the semiconductor-metal contact structure. It is also possible to improve the operating characteristics of the device.

[Brief explanation of drawings]

FIG. 1 shows (a) and (b) a MOSF of an embodiment of the present invention.
Plan view and cross-sectional view showing ET, FIGS. 2(a) and (b)
are a plan view and a cross-sectional view showing a MOSFET with a conventional structure,
FIGS. 3(a) to (h) are explanatory diagrams of the manufacturing process of the MOSFET shown in FIG. 1, and FIGS. 4(a) to (d) are
A sectional view, a planar layout diagram, and a circuit diagram when the present invention is applied to a MOS inverter, FIGS. 7 and 7 respectively show still another embodiment of the present invention, and FIGS. 8 and 9 are cross-sectional views of the vicinity of the source of a MOSFET for explaining the present invention in detail. 100...Substrate 103...Gate oxide film 104...Gate electrode 105.106...Source and drain region 107
, 108... Extraction electrodes 110, 111... Junnosuke Nakamura, patent attorney representing the metal-semiconductor contact department Figure 1! ,! 04 ++o, m-, 4A-1 Kobe r4p O2 figure (Q) ;! f'3 Figure 3, Figure 5? 4 Figure (b) Figure 4 (C) (d) Figure 5 (Q) (b) Figure 8, Figure 9

Claims (5)

[Claims] (1) In a semiconductor device having first and second high impurity concentration regions provided in a semiconductor layer and a first electrode that controls conductance between the regions, the first and second high impurity concentration regions A semiconductor device characterized in that a main surface of a contact portion between a region and an electrode conductor extending from the region has an angle with respect to a main surface of a substrate on which the semiconductor layer is placed. (2) The semiconductor device according to claim 1, wherein the substrate is an insulating substrate or a conductor or semiconductor substrate whose surface is at least partially covered with an insulating film. (3) The first and second high impurity concentration regions are source/drain regions, and the first electrode is a gate electrode.
The semiconductor device according to claim 1, characterized in that the semiconductor device comprises an OSFET. (4) the first and second high impurity concentration regions are source/drain regions, and the first electrode is a gate electrode;
at least two p-channel and n-channel MOSFs
2. The semiconductor device according to claim 1, wherein a CMOS inverter is constructed by arranging ETs in parallel on the substrate. (5) the first and second high impurity concentration regions are source/drain regions, and the first electrode is a gate electrode;
at least two p-channel and n-channel MOSFs
2. The semiconductor device according to claim 1, wherein an ET is stacked on the substrate to constitute a stacked CMOS.