JPS6156461A - Misfet on insulation layer and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the overlap capacitance and remove the short channel effect by a method wherein a metal silicide is formed at part or over the whole of source-drain regions, and the metal silicide is made to reach the interface between the silicon layer and the base insulation substrate. CONSTITUTION:The metal silicides 205 are formed at part or over the whole of the source-drain regions of the MISFET made Si formed on the insulation layer 201, and the metal silicides 205 are made to reach the interface between the Si layers 203 and the insulation layer 201. For example, the sour;ce and drain regions 204 in contact with the gate region 202 consist of an impurity- doped layer. The source-drain regions 205 are the part therefrom the impurity- doped layer 204 is removed and formed out of metal silicide.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to M I 8 (Metal) formed on an insulating layer.
-Insulator -Sem1conducto
r ) type field effect transistor (hereinafter referred to as MIS type F
(referred to as ET).

In particular, the present invention relates to the structure of a MIS field effect transistor that uses metal silicide for the source and drain to achieve low resistance, and a method for manufacturing the same.

(Prior art and its problems) MIS-type FETs using semiconductors on insulating layers have characteristics such as small junction capacitance, small wiring space, and complete isolation between each element, and are suitable for high-speed and high-density integration. It is attracting attention from the point of view of its application to circuits. In high-performance MIS F'ET, gate electrodes and source/drain electrodes are generally formed in self-alignment. In such a self-aligned MI8iFET, in order to reduce the so-called short channel effect, it is necessary to minimize the lateral inward spread of the impurity-doped layer constituting the source and drain electrodes below the gate 2 pole. It is effective to reduce the depth of the impurity-doped layers constituting the source and drain electrodes. However, as the depth of the impurity-doped layer becomes shallower, the sheet resistance of the source/drain increases.
At 3 μm, the value is 300/mouth for n-type and 10 for 9th base.
This large sheet resistance, which is as high as 0 Ω/hole, causes parasitic resistance, which prevents the high performance characteristics achieved by forming it on an insulating layer.

In recent years, as a way to solve this problem,
A method has been proposed to solve the above-mentioned problem of increased sheet resistance by forming a high-melting point metal silicide on the silicon surface that is to become the JS/drain electrode.

FIG. 1 is for explaining this conventional example, and shows a cross-sectional view of an MI8WFET formed on an insulating substrate 101, in which a refractory metal silicide 105 is formed on the surface of the source or drain.

However, the structure shown in FIG. 1 has the following problems. In MIa-type FETs with minute gate lengths of about 1 μm or less, in order to suppress the short channel effect, it is necessary to prevent the impurity-doped layers that form the source and drain from expanding laterally below the gate electrode. Although it is necessary to keep it as small as possible, at present there is a lateral inward spread of about 0.4 μm, and the short channel effect cannot be prevented from occurring. Another problem is that the sheet resistance of the source/drain is not small enough, and the extension of the source/drain cannot be used as wiring. The thickness of the high melting point metal silicide used in Figure 1 is Q, l l1m
-Q, about 2 μm; W, Ta.

Even when using Ti silicide, which has the lowest specific resistivity among silicides such as Mo and Ti, the sheet resistance value is 1.
Ω/gate, and the extension of the source or drain cannot be used as a wiring layer.

(Structure of the Invention) The object of the present invention is to provide an MIS on an insulating layer that solves the above problems.
The object of the present invention is to provide a new and novel structure of type PET and a manufacturing method thereof.

(Structure of the Invention) According to the present invention, in a silicon MIS field effect transistor formed on an insulating layer, metal silicide is formed in part or all of the source/drain region, and the metal silicide is formed between the silicon layer and the base layer. A MIS type field effect transistor is obtained, which is characterized in that it reaches the interface with the insulating substrate.

Furthermore, according to the present invention, after forming a single crystal silicon region in which a MIS field effect transistor is to be formed on an insulating layer, forming a gate insulating film on the surface thereof, and then forming a thin film for a gate electrode. After patterning the gate electrode thin film, the gate insulating film except under the gate electrode thin film is patterned to expose the single crystal silicon surface, and after forming the high melting point metal thin film, non-dopant ions are patterned. A step of converting all the silicon under the exposed single crystal silicon surface into metal silicide by implanting and mixing the interface between the high melting point metal thin film and the exposed single crystal silicon surface and then performing annealing; An insulation characterized by comprising the steps of etching the unreacted and remaining high melting point metal, forming an interlayer insulating film, and then diffusing impurities through an opening in the interlayer insulating film provided on the metal silicide. A method for manufacturing a layered MIS film-effect transistor is obtained.

Further, according to the present invention, after forming a single crystal silicon region on which an MId type field effect transistor is to be formed on the insulating layer, a gate insulating film is formed on the surface thereof, and then a thin film for a gate electrode is formed. With the process.

After patterning the gate electrode thin film, etching the gate insulating film except under the extremely thin film in the gate area to expose the single crystal silicon surface.

After forming a high melting point metal thin film, non-dopant ions and ■
The interface between the refractory metal thin film and the single-crystal silicon surface is mixed by implanting dopant ions of the group or II group, and the interfacial mixed layer and the single crystal under the mixed layer are mixed in the refractory metal thin film, the interfacial mixed layer, and the single crystal under the mixed layer. A step of doping impurities into silicon and then annealing to convert all the silicon under the exposed single crystal silicon surface into metal silicide, and then etching the remaining unreacted high melting point metal. A method for manufacturing a MIS field effect transistor on an insulating layer is obtained, the method comprising:

C Embodiment 1) The structure of an embodiment of the MISFET of the present invention is shown in FIG. 2. In the figure, 204 is a source and drain region in contact with the gate region 202, and is made of an impurity-doped layer. 205 is a source/drain region excluding the impurity doped layer 204; ,,,K1,. Wow 6.4 7. This has the advantage that the lateral inward spread of the source and drain impurity doped layers under the gate electrode can be reduced. In the conventional example shown in Figure 1, the impurity-doped layer forming the source and drain must reach the insulating substrate, and the thickness is the same as the thickness of the semiconductor thin film on the insulating substrate.
Although horizontal inward expansion under the gate electrode of ~0.4 μfrL) is unavoidable, in the present invention, the impurity doped layer 204 is formed to a thickness of about 0.1 μm so as to cover the metal silicide 205. In the structure of the present invention, which was able to suppress the lateral inward expansion to about 0.1 μm, the metal silicide is formed reaching the insulating substrate, compared to the conventional structure in which metal silicide is formed only on the source and drain surfaces. A sheet resistance that is approximately one-fourth lower than that of the previous one was achieved.

Furthermore, in the structure of the present invention, the portion of the source/drain region 204 in contact with the gate region is almost flat, whereas that formed by conventional ion implantation is a curved surface, and the structure of the present invention has a smaller surface area. .

Therefore, leakage current through the junction could be reduced. Embodiments of the present invention will be described below with reference to the drawings.

1 is a schematic sectional view showing main steps for explaining the invention in detail.

Thickness 3100^2 single crystal 8ijl [8ijl of the same thickness was deposited on the sapphire substrate 301 on which the pattern 302 was formed by CVD method. A film was formed to obtain the structure shown in FIG. 3(a). Next, apply a negative resist and expose it from the back side, leaving only the resist on the field area.

8i 0. on 8i film. Remove the film and flatten the surface.

Next, as shown in Figure 3 (bJ), after forming a gate insulator [304] to a thickness of 300^ by thermal oxidation, a polycrystalline silicon film was formed by 4000 layers, and then a polycrystalline silicon film was formed by a normal dry etching method. After patterning, the gate insulating film is etched using the polycrystalline Si 305 as a mask to expose the single crystal silicon surface 306 on which the source and drain are to be formed. The film 307 was formed by sputtering, and the 6 and 8i ions were accelerated at a voltage of 160 KeV.
So 5XIO1scl! After implanting L-2 ions and mixing the interface between the Ti film and single crystal silicon,
Annealing was performed for 0 minutes to cause a metal silicide reaction in the single crystal silicon and polycrystal silicon regions in contact with the Ti film.

Next, by etching the unreacted Ti film on the field insulating film with a Hlo-based etching solution, metal silicide is selectively formed in the source/drain region and gate region, resulting in the structure shown in FIG. 3(C). Obtained.

Next, after forming a silicon oxide film 309 of about 500 OA by vapor phase growth, a contact hole 310 is formed by a normal photoetching method, and then the silicon oxide film 309 is heated to 850°C.
Perform phosphorus diffusion for 20 minutes to transfer phosphorus to metal silicide 308.
An impurity doped layer 311 is formed by diffusing the impurity into the silicon region in contact with the metal silicide through the metal silicide.
In this example, the sheet resistance of the Ti silicide forming the source/drain electrodes was 0.250/mouth, and the lowest resistance was achieved compared to the conventional one.

In a normal MIS type FIT manufacturing procedure, an interlayer insulating film is formed after impurity diffusion for forming sources and drains. However, in this procedure, impurities are redistributed during high-temperature annealing at nearly 1000°C to densify and planarize the interlayer insulating film, increasing the source/drain junction depth and causing the source/drain under the gate electrode to redistribute. In the present invention, the impurity doping for forming the source and drain takes advantage of the property that the diffusion of impurities in metal silicide is much thicker than that in silicon. After the film was formed, doping was performed through the opening 310, and even after sufficient high-temperature annealing for densification and flattening of the glabellar film, the lateral spread was sufficiently small and could be suppressed to about 0.1 μm. .

(Example 3) FIG. 4 shows a schematic cross-sectional view of the main steps for explaining an example of the manufacturing method of the present invention as set forth in claim 3.

Similarly to the embodiment described above, a polycrystalline silicon gate 405 is formed on an island-shaped single crystal silicon 402 having a film thickness of 3100 A formed on an insulating substrate 401 as shown in FIGS.
After that, a Ti film of 160 OA was formed on the entire surface by sputtering and taring.

Next, Si ions were accelerated at a voltage of 160 KeV.
After implanting O”CIIL-2, one S ion was accelerated at a voltage of 3
5×IQ”cIIL−” implanted at 00 KeV,
An interfacial mixed layer 408 and an S-doped layer 409 were formed to obtain FIG. 4(e). In order to minimize the lateral spread of the As doped layer 409 below the gate electrode, the peak of As ion implantation was set on the Ti side from the interface 406 between Ti and single crystal silicon in FIG. 4 (bJ).

Next, annealing was performed at 550°C for 20 minutes, and the Ti
A metal silicide reaction was caused in the monocrystalline silicon and polycrystalline silicon regions in contact with the film.

Next, Ti silicide 410 is selectively formed in the source/drain region and gate region by etching the unreacted Ti film on the field insulating film with an H, O, based etching solution. By performing annealing for 1 minute, As is diffused to cover the Ti silicide in the source and drain regions, and an A3 doped layer 411 is formed. Similar to the example.

Achieved reduction in source/drain sheet resistance.

It is now possible to use the source/drain extensions as wiring. Furthermore, the lateral expansion of the source/drain region below the gate electrode can be made sufficiently small to about 0.1 μfrL, allowing short channel MIS type FlfT with a gate length of 1 μm or less.
It became possible to form with good reproducibility.

In Examples 2 and 3 above, Ti silicide was used as the metal silicide, but Ta, W.

Similar excellent effects were obtained with Mo silicide or a composite layer of these metal silicides. Further, although the case where n-type P e As was used as the impurity forming the source/drain was shown, similar effects were obtained when using p-type impurities such as boron. Further, although silicon was used as the ion implantation species for mixing the metal-silicon interface, similar effects were obtained when non-dopant ions such as argon were used. Furthermore, although the case where polycrystalline silicon is used as the gate electrode of a 1Ml5 type FET has been described, the present invention can also be applied to the case of a metal silicide gate or a metal gate.

Furthermore, the present invention can naturally be applied to a so-called SOI structure transistor in which an 8i single crystal film is formed on an insulating film.

(Effects of the Invention) In the MISFET having the structure of the present invention, since the overlap between the source/drain and the gate can be made sufficiently small, the overlap capacitance can be reduced and undesirable short channel effects can be eliminated. Furthermore, since the resistance of the source/drain layer can be reduced, the extension of the source/drain layer can be used as a wiring.

According to the method of the present invention, the portion in contact with the gate region,
The shape of the source/drain can be made into a flat shape instead of a conventional curved surface, and the diffusion distance of the source/drain impurity layer in the portion in contact with the gate region can be controlled easily and the diffusion distance can be reduced.

[Brief explanation of the drawing]

The numbers in the figure indicate the following. 101.201,301,401...Insulating substrate, 10
2,202,312°412...Single crystal silicon under the gate electrode, 302,402...Single crystal silicon,
104, 204, 311, 411... impurity doped layer, 105, 205, 308, 410... Ti silicide. 107.207...Gate electrode, 106,206
, 304, 404... gate insulating film, 305, 405
... Polycrystalline silicon, 306, 406... Interface between Ti and single crystal silicon, 307,407...T
1 film, 408...interface mixed layer, 309...interlayer insulating film, 310...-contact hole, 313...Ti
Interface between silicide and insulating substrate, 409... impurity doped layer. Figure 1 +07 O 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a silicon MIS field effect transistor formed on an insulating layer, metal silicide is formed in part or all of the source/drain region, and the metal silicide is connected to the silicon layer and the insulating layer. An MIS type field effect transistor on an insulating layer, characterized in that the MIS type field effect transistor reaches the interface of the insulating layer. 2. After forming a single crystal silicon region in which a MIS type field effect transistor is to be formed on the insulating layer, forming a gate insulating film on the surface thereof, and then forming a thin film for a gate electrode, and the thin film for the gate electrode. After patterning, the gate insulating film except under the gate electrode thin film is etched to expose the single crystal silicon surface, and after forming a high melting point metal thin film, non-dopant ions are implanted to remove the high melting point metal thin film. and the exposed single-crystal silicon surface, and then annealing to convert all the silicon under the exposed single-crystal silicon surface into metal silicide; After etching, forming an interlayer insulating film, and then diffusing impurities through an opening in the interlayer insulating film provided on the metal silicide. Production method. 3. After forming a single crystal silicon region in which an MIS field effect transistor is to be formed on the insulating layer, forming a gate insulating film on the surface thereof, and then forming a thin film for the gate electrode; After patterning the thin film, etching the gate insulating film except under the gate electrode thin film to expose the single crystal silicon surface, and after forming the high melting point metal thin film, non-dopant ions and group III or
By implanting group IV dopant ions, the interface between the high melting point metal thin film and the single crystal silicon surface is mixed, and the high melting point metal thin film, the interfacial mixed layer, and the single crystal silicon below the mixed layer are mixed. doping with impurities, and then converting all the silicon under the exposed single crystal silicon surface into metal silicide by annealing, and then etching the remaining unreacted high melting point metal. MI on an insulating layer characterized by
A method for manufacturing an S-type field effect transistor.