JPS6279617A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive reduction in resistance by making the surface of a wiring flat by making to have two or more Si regions which have the same or the different conductive types and a metal silicide film provided between the Si regions and electrically connected to the Si region on an insulation film or an insulation substrate. CONSTITUTION:An SiO2 film 2, an insulation film, is formed on an Si substrate 1 and after a polycrystalline Si layer 5 is deposited, a single crystal Si layer 3 is formed by recrystallizing the polycrystalline Si film 5 by the irradiation with a CWAr<+> laser. Then, after B is implanted with ions in the whole substrate, an SiO2 film 6 is formed and after a required region is removed by hot etching, a W film 7 is deposited on the region. Then, a construction of metal silicide is formed at the region where the single crystal Si layer 2 and the W layer 7 are abutted by the heat treatment in the atmosphere of nitrogen. Later, the W layer 7 which is not reacted is removed, then the SiO2 film 6 is removed and a construction of having a W silicide film 4 between the Si layers 3, 3 electrically connected to the Si layer 3 having low resistance and a flat surface is made.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device having an SOI structure (silicon-on-insulator) and a method for manufacturing the same.

[Background of the invention]

SOI structure (for example, IE
IEE), Electron Device Letters (ELE
CTRON DEVICE L [ETTER8), Vo
1, EDL-1, p. 214 (1980)), and in which devices are formed during single crystal SL film removal, the devices are completely isolated from each other and there is no parasitic effect. It becomes possible to increase the density of elements and increase the degree of freedom in design. Therefore, even in integrated circuits with a three-dimensional stacked structure expected in the future, S○
Engineering structure formation technology will be an important technology.

FIG. 2 shows an example of a semiconductor device using the S○■ structure. This figure shows a complementary MMOS transistor in which p-channel and n-channel MOS transistors are formed on an insulating film provided on a Si substrate.
An example of an OS transistor is shown. In the figure, 21
is Si substrate, 22 is 513N4 film, 23.23' is Si
C2 film, 26 is a p-type Si region, 28 is an n-type heavily doped region, 27 is an n-type S1 region, 29 is an n-type heavily doped region, 30 is a gate insulating film, 24 is a gate electrode, 25 is a A11 (aluminum) wiring layer, 31 is n-channel MO3I-transistor, 32 is p-channel MOS
It is a transistor.

Conventional element isolation regions have been formed by depositing an insulating film over the entire surface of a semiconductor substrate and patterning this insulating film by photolithography. Therefore, this method has a problem in that a large step is created between the element isolation region and the element formation region. In order to reduce this level difference, the device shown in FIG. 2 has a 2-OC○S structure that utilizes one selective oxidation. In this structure, after depositing a Si, N, and film mask on the S' substrate, the S
O2i! Element isolation is performed by the signal (23 in FIG. 2). However, even in this structure, the Si substrate expands due to the thermal oxidation, resulting in a step.

In this way, it is difficult to obtain a sufficiently flat structure in a device having the LOGO3 structure in which the elements are insulated and isolated on the Si○2 film 23, and with this LOC○S structure,
In a conventional device in which wiring is performed using an acid film 25,
The manufacturing process is complicated, and it also limits high integration, which is an advantage of the S○■ structure.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a SO structure with a flat surface and low resistance wiring, and a manufacturing method that can manufacture the device through simple steps.

[Summary of the invention]

Examples of wiring materials having low resistance include high melting point metals and metal silicides. Although high melting point metals are superior in terms of resistance, metal silicides are more suitable in terms of selective formation and stability when in contact with Sj.

The present invention uses this metal silicide film for wiring between elements, and the semiconductor device of the present invention includes two or more Ss having the same or different conductivity types on an insulating film or an insulating substrate.
It is characterized by having an i region and a metal silicide film provided between the Si region and electrically connected to the Si region.

The method for forming a metal silicide film is that silicide can be selectively formed in a certain region on an insulating film, so after depositing a metal film on a Si layer, heat treatment is performed to separate the metal film from the underlying Si layer. A method of forming a metal silicide film through reaction is suitable. In this case, in order to cause the silicide reaction to reach the insulating film or insulating substrate 81 layers below, it is necessary to deposit a metal film with a sufficient thickness on the S1 layer.

That is, the method for manufacturing a semiconductor device of the present invention includes a step of forming a Si layer on an insulating film or an insulating substrate, a step of selectively forming a second insulating film on the S1 layer, and a step of forming a second insulating film on the S1 layer.
a step of forming a metal film on the layer and the second insulating layer 11, and a heat treatment to form the metal layer and the S in contact therewith.
The present invention is characterized by comprising a step of causing a silicide reaction with one layer to form metal silicide Ia, and a step of removing the metal film that has not been silicided.

In a conventional device having a r-acos structure, a step exists between the SiC2 film in the element isolation region and the Jk plate, like a double layer. In the present invention, the step is the above-mentioned S
It exists between the i region and the metal silicide film. However, the volume increase due to silicidation of the Si layer is about 7% if the metal is tungsten, for example, which is smaller than the step difference due to expansion of the 31 substrate in the case of the conventional LOGO5 structure, so a flatter structure can be realized. .

When a junction is formed between a metal silicide layer and a semiconductor layer,
This is usually a Schottky junction, but if the recombination rate of carriers at the interface is very fast, or if the Schottky barrier is thin enough to allow carriers to tunnel, then an ohmic junction occurs.

Therefore, if the impurity concentration at least at the interface with the metal silicide film in the Si region is increased to make the barrier sufficiently thin, an ohmic junction will be formed and a sufficiently low contact resistance will be obtained.

〔Example〕

Example 1 FIG. 1 shows a schematic cross section of a first example of the semiconductor device of the present invention. In the figure, 1 is a Si substrate, 2 is an insulating film provided on the Si substrate, or Si (or Si, N4).
The film 3.3' is a Si region of the same conductivity type.

A metal silicide film 4 is provided on the insulating film 2 and between the Si regions 3.3', and electrically connects the S1 regions 3.3'. Although not shown, qj elements are formed in the Si region 3.3'.

FIGS. 3(a) to 3(c) show the first embodiment of the present invention shown in FIG.
Example of i! It is a sectional view showing the zero manufacturing process.

First, as shown in FIG. 3(a), a 51071 insulating film 2 is formed on an S] substrate 1, and then an SjO film is formed.

゛ After depositing a polycrystalline Si layer 5 with a thickness of 0.5 m on the film 2 by low-pressure CVD, the polycrystalline Si film 5 is recrystallized by irradiation with a CW Ar+ laser to form a single crystal Si layer. 3 (Fig. 3(b)).

Next, B (boron) was ion-implanted into the entire substrate under the conditions of an implantation energy of 50 keV and an implantation resistance of I x 10"am-", and then wet oxidation was performed on the surface to a thickness of 0°2.
After forming a Si○2 film 6 with a thickness of 1 m and removing a desired region by photoetching, a W (tungsten) film 7, which is a metal film, is deposited on it to a thickness of 0.4ρ using a vapor deposition method. Figure 3(b)).

Next, when heat treatment is performed by lamp annealing at approximately 900'C for 160 seconds in a nitrogen atmosphere, WIlu7 and
The portion of the single-crystal Si film 3 in contact with the W film 7 undergoes a silicide reaction, and the silicide reaction in this portion progresses until it reaches the insulating film 2, and in the portion where the single-crystal Si layer 2 and the W layer 7 contact A metal silicide structure can be formed over the entire thickness of the insulating film 2. After that, the W film 7 that did not undergo the silicide reaction was removed using H2O, and the Sin film 6 was removed using HF, and a W silicide film 4 was placed between the Si layers 3 and 3' to be electrically connected thereto. We realized a structure with (Fig. 3 (C)).

In this example, the specific resistance of the W silicide film is 50 μΩ.
.cm, and the contact resistance between the W silicide film and the single crystal Si layer was 3×10 −6 Ω·d.

In this example, the volume increase due to silicidation of the W film is 7
It was possible to achieve a flatter structure compared to the conventional LOCO5 method and A(1) using wiring.The factors that determine the size of the metal silicide film area are Since the size of the mask pattern is only 6, it is possible to form elements with higher density.Furthermore, if lamp annealing is used for silicidation as in this example, it is possible to form elements in other areas. Redistribution of impurities can be reduced.

As mentioned above, in order for the silicide reaction to proceed until it reaches the insulating film 2, the W film must be thick enough to cause the silicide reaction to occur over the entire thickness of the single crystal Si layer in contact with the W film.
A film is deposited on the insulating film 2.

In this embodiment, an n-type Si region can be formed by using P (phosphorus) or Aq (arsenic) instead of B as the ions implanted into the single crystal Si layer 3.

Note that the S1 film on which the metal film is deposited is not limited to single crystal, but may be polycrystalline or amorphous.

Figure 4 shows that by changing the ion implantation amount, n
The contact resistance between the metal silicide film and the 81 region is shown when the impurity near the interface with the metal silicide film in the type and P-type S1 regions is varied by 11 degrees. In the figure,
T1 indicates an n-type Si layer, and p indicates an n-type Si layer. As is clear from this figure, in this example, when the impurity and layer tops of both n-type and p-type are 3 x 10"cm-' or more, contact resistance comparable to that obtained when contacting with AD and the film is obtained. Ta.

Embodiment 2 FIG. 5 shows a schematic cross section of a semiconductor device according to a second embodiment of the present invention. This example is absolutely perfect! This is an example in which a metal silicide film 4 is formed between an n-type Si region 8 and a p-type Sj region 9 on the 4-film 2. When the n-type S1 layer and the p-type Si layer are directly bonded,
A pn junction is formed, but in this example, by providing the metal silicide film 4 at the junction between the two, an ohmic junction could be realized.

Embodiment 3 FIG. 6 shows a schematic cross section of a semiconductor device according to a third embodiment of the present invention. In addition to the structure of Example 1, this example has p-type S
This is an example in which an n-type high degree impurity doped region 0 is formed near the interface with the metal silicide film 4 in the i region 3.3'. In order to manufacture the film on the semiconductor of this embodiment, unreacted WIG! 27 (3rd
Between the step of removing the SiO□ film 6 and the step of removing the SiO□ film 6, P ions were implanted into the entire surface at an implantation energy of 40 keV and an implantation amount of lXl016.
A PSG film was deposited to a thickness of 0.2 mm on the metal surface, and P was removed by lamp annealing at approximately 1100°C for 20 seconds in a nitrogen atmosphere.
A step of selectively drive-in diffusion into the region using a mask to form an n-type heavily doped region 10 and removing the PSG film by dry etching is inserted. If As is used as the implanted ions, the implantation energy may be about 80 keV, and if B is used to form a p-type cavity concentration impurity region, the implantation energy may be about 30 keV.

Embodiment 4 FIG. 7 shows a schematic cross section of a semiconductor device according to a fourth embodiment of the present invention. This embodiment is an example in which Si regions 3 and 3' are located in an upper layer and a lower layer with an insulating film 11 interposed therebetween. First, an intermediate insulating film layer 11 is patterned on the single crystal Si layer 3 as shown in the figure, a W film is deposited on the intermediate insulating film layer 11 and the single crystal Si layer 3, and the single crystal Si layer 11 is heated by heat treatment. and w+yy
By causing a silicide reaction to occur, the W silinite film 4 is formed until it reaches the insulating film 2. Thereafter, the unreacted W film was removed and a single crystal Si layer 3' was formed on the insulating film 11, thereby forming the structure shown in FIG.

The figure shows S1 regions 3 and 3' formed on one side of the W silicide film 4, but S1 regions 3 and 3' are formed on one side of the W silicide film 4.
A semiconductor region connected to i-region 3 or 3' may be formed.

This embodiment can be applied to an integrated circuit with a multilayer three-dimensional stacked structure, and in particular, the upper layer MoS transistor and the lower layer MOS transistor in stacked complementary MOS transistors.
This is effective for wiring between rungis 5.

In the first to fourth embodiments described above, only W silicide was used as the metal silicide film, but the type thereof is of course not limited to this.

〔Effect of the invention〕

As described above, the semiconductor device of the present invention provides a semiconductor device having a structure in which elements are formed on an insulating film or an insulating substrate, and has a flat surface and low-resistance wiring. can do. Also,
According to the method for manufacturing a semiconductor device of the present invention, even when the distance between elements is relatively short, low-resistance inter-element interconnections can be formed flatly in a simple process, thereby increasing the density of elements and simplifying the process. can be realized. Furthermore, by forming a highly doped region with impurities near the interface with the metal silicide film in the Si region, it is possible to provide a new rod structure in which the Si region and the metal silicide film are in ohmic contact.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing an embodiment of the semiconductor device of the present invention, FIG. 2 is a cross-sectional view of a complementary MOs transistor which is an example of a semiconductor device using a conventional S○■ structure, a
) to (c) are process cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device of the present invention, FIG. 4 is a diagram showing the relationship between impurity concentration and contact resistance in the embodiment of the present invention, and FIG. FIGS. 6 and 7 are schematic cross-sectional views of other embodiments of the present invention. 1.21...Si substrate 2.22.23.23'--Insulating film (Si3N4 film or SiO2 film) 3.3', 9...p-type S1 region 4...W silicide film 5- ...Polycrystalline Si layer 6...Patterned 5in2 film 7...W film 8...N-type Si region 10...High concentration impurity doped region 11...Intermediate insulating layer 24...Gate Electrode 25...A wiring layer 26...P type Si region 27...N type Si region 28...N type high concentration impurity doped region 29...P type cavity concentration impurity doped region 30... Gate insulating film 31...n channel MOS transistor 32...p
Channel MO3) - Junnosuke Nakamura, a patent attorney representing Langista? 1 Figure ゛) Figure 2 Figure 5F4 Figure IPS Figure

Claims (4)

[Claims] (1) Two or more silicon regions having the same or different conductivity types on an insulating film or an insulating substrate, and a metal silicide film provided between the silicon regions and electrically connected to the silicon regions. A semiconductor device comprising: (2) The semiconductor device according to claim 1, wherein the silicon region has a region with a high impurity concentration at least near the interface with the metal silicide film. (3) forming a silicon layer on an insulating film or an insulating substrate, selectively forming a second insulating film on the silicon layer, and forming a metal layer on the silicon layer and the second insulating film; a step of forming a film; a step of causing a silicide reaction between the metal film and the silicon layer in contact therewith by heat treatment to form a metal silicide film; and a step of removing the metal film that has not been silicided. A method for manufacturing a featured semiconductor device. (4) A metal film having a thickness sufficient to cause the silicide reaction over the entire thickness of the portion of the silicon layer in contact with the metal film is deposited on the single crystal silicon film. A method for manufacturing a semiconductor device according to scope 3.