JPS58175847A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of freedom regarding a design by forming wiring and a gate electrode into a region surrounded by a field insulating film by poly Si through an insulating thin-film and connecting the wiring and wiring on a substrate by a metal or a metallic semiconductor compound film. CONSTITUTION:A gate oxide film 402 is formed onto the substrate 401, and a gate electrode 410 and wiring 409 are formed by using polysilicon. Impurity ions are implanted, and source-drain and diffusion-layer wiring 408 are formed. CVD SiO2 411 Is deposited onto the whole surface, and the surface of the diffusion layer 408 is exposed through directional etching while SiO2 412 is left on the side surfaces of the gate electrode 410 and the wiring 409. When only SiO2 of the side surface of the wiring 409 is removed through etching while using a resist 413 as a mask and a Pt film is evaporated onto the whole surface and annealed, sections being in contact with silicon or polysilicon are changed into PtSi 414, and the wiring 409 and the wiring 408 are connected electrically by the PtSi.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of making contact between a gate electrode and a diffusion layer wiring.

[Prior art and its problems]

The interconnection of these wirings is typically done through an expanded cathode layer and direct contact in the case of polysilicon. However, the conventional direct contact method has various problems, and a new technology has been desired. The problems of the prior art will be explained below with reference to the drawings.

Figure 1(a) shows an LSI with direct contact.
FIG. 2 is a plan view showing a part of the semiconductor device, in which a gate electrode (101) made of polysilicon, a wiring (102), etc. are arranged. (103) and (104) are the diffusion layer wiring, and at the same time they are the source and drain of a MOS transistor whose gate electrode is (101). It corresponds to a circuit diagram. Polysilicon arrangement 1 (102) and diffusion layer arrangement @ (10
Electrical contact with 4) is through direct contact (10
5). Figure 2 (1) to (d) are the first
The outline of the manufacturing process is drawn in the p-pK cross-sectional view of the circuit element shown in FIG.

For example, a gate oxide film (2
02) is thermally oxidized at, for example, 200 A@degrees. Next, mask alignment is performed and the direct contact section (203
) is removed by etching under NH4 to expose the Si substrate surface (Figure 2 (1)).
.

Next, polysilicon (204) is deposited on the entire surface by a CVD method or the like, and phosphorus is diffused over the entire surface by performing, for example, PO(j) diffusion.At this time, phosphorus is diffused into the silicon substrate in the direct contact area. Diffusion layer (2
05) is formed (Fig. 2)).

Next, a photoresist (206) is left on the gate electrode and wiring portion by -v masking, and the polysilicon (204) is removed by etching using the fin as a mask. This etching can be carried out by reactive ion etching using, for example, CCj4, but in this case, in the transistor part, the etching of 81 stops at the surface of the oxide film (202), but in the direct contact part, there is no oxide film. Figure 2 (
A structure (207) is formed on the silicon substrate in a circular shape as shown in C). Firstly, the gate oxide film (202) is removed and 3~4xlO"cff" ions are implanted at a voltage of, for example, 50 KV. Source/drain and diffusion layers (20 g) are formed by additional annealing at about .degree. At this time, a V diffusion layer is also formed in the trench by ion implantation, and the polysilicon interconnection (209) and the enlarged catfish layer interconnection (20g) are electrically connected. However, the depth and shape of the groove are not constant and vary greatly depending on the etching conditions, over-etching time, etc., so the resistance value varies greatly in the groove. If the groove is formed in a large circular shape, the diffusion layer (20g) and the polysilicon wiring C2m') will be electrically insulated and separated from each other because the diffusion layer will not be connected at the groove, as shown in FIG. The above-mentioned problems become more important as the junction depth becomes shallower with the miniaturization of devices, and have been the cause of a drastic drop in the yield of L8I. There is also another problem in that crystal defects generated in the grooves by reactive ion etching increase junction leakage in the diffusion layer, degrading the performance of the device.

The above describes the case of nine N-channel transistors formed on a p-lid substrate.
In the so-called CMO8il path where parts of
There is an important issue that I will address below.

In other words, if N+ polysilicon is used, direct contact cannot be made in the region where the P channel transistor is formed. For example, as shown in Fig. 3 (-)K, the source, drain, and diffusion layer interconnections are made using Kunohe diffusion layers by implanting boron ions, but after going through the same process as shown in Fig. 2 (a) to (d), In the direct collection department! Since a p-n junction cannot be formed between the polysilicon and the substrate, the substrate will be exposed to the substrate. formation) and P
+ After forming a diffusion layer and forming a circle, a wiring @ (309) is formed with the second r polysilicon, and if it is 9, then V polysilicon (
309) and the P+ diffusion layer (308), a pn11 coupling is formed at the direct contact portion, making it impossible to establish an open contact.

For the above reasons, for example, in a CMO811 circuit using polysilicon wiring, direct contact cannot be made in the P-channel transistor O region and the circuit is round.

During these years, great constraints have been placed on the design of @sha circuits.

[Purpose of the invention]

The present invention has been made in view of the above points, and it is an object of the present invention to provide a contact method that is excellent in yield and can increase the degree of freedom in designing L8I.

[Outline of invention cost]

In accordance with the present invention, a field insulating film of a semiconductor substrate is used.
! Wiring and the gate electrode of the transistor (MI811) are formed using a semiconductor film in the large area of the I-stage with an insulating thin film interposed therebetween. Next, the wiring layer of the substrate and the wiring layer are connected by a metal or metal-semiconductor compound film.

〔Effect of the invention〕

According to the present invention, an insulating thin film is formed in the trenched region with a field insulating film, and then wiring and gate electrodes are provided using a semiconductor film, so that the substrate is not etched when patterning the wiring film. can be prevented, resulting in a dramatic increase in yield. In addition, since the substrate wiring layer and the wiring film are separated by an insulating film formed in the element formation region and interconnected by a metal or metal-semiconductor compound film, contact can be established without depending on the conductivity WaU between the two. is possible, L8I
The degree of freedom in design is greatly improved.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 4(a), after forming a gate oxide film (402) of 50 to 1150 OA, for example 200, on a 1 m substrate (401), a gate electrode (410) made of polysilicon and a U arrangement 11 are formed. (409) is formed. This polysilicon may be, for example, so-called doped polysilicon to which phosphorus or arsenic is added during formation, or it may be doped with impurities by POCj, diffusion, or ion implantation after polysilicon is deposited on the entire surface. Further, impurities may be doped simultaneously with the subsequent formation of the source and drain. Then, for example, Al t 3-5 at 50KV
After X to "cat-" ion implantation, a source/drain and diffusion layer wiring (40 g) are formed.

The ion implantation may be performed through the gate insulator, or may be performed after removal. Field area ([
1 (corresponding to the region other than the diffusion layer in FIG. 1), a thick field insulating film (not shown) is formed.

Next, ions are implanted by annealing in an oxidizing atmosphere or N atmosphere at 1000° C. to activate 7jA@, and CVD sto (41t) is deposited on the entire surface (FIG. 4(b)). Next, the entire surface is subjected to directional ion etching. For example, using reactive ion etching using CF4 and H gas, S10. At the same time, the gate electrode (410) and polysilicon arrangement m (409) are etched to expose the surface of the diffusion layer (40B).
Leave sto (412) on OVa (Fig. 4 (C)
) Next, a photoresist (413) is selectively placed to expose a portion for making electrical contact between the polysilicon wiring (409) and the diffusion layer wiring. Then, for example, the oxide film on the side wall of the polysilicon wiring is removed by etching on the leeward side (Fig. 11114(d)'), and then the entire surface is etched.
iIIK about 1$00A true 9! When formed by black bonding and annealed for about 15 minutes in an atmosphere of 550"0, °P*8i (platinum silicide) is formed only in the areas where the Pt film is in contact with silicon or polysilicon.
(414) is formed. Thereafter, when it is treated in aqua regia, the unreacted Pt film is removed and the structure shown in FIG. 4(e) K is obtained.

Pi silicide (414) is selectively formed on the source/drain and diffusion layer (408), on the upper surface of the gate electrode (410) 0, and on the upper surface and sidewalls of the polysilicon interconnection I71 (409). At this time, the polysilicon wiring, Pt8i on the side wall and Pt5l on the diffusion layer (408) are interconnected and formed continuously.

Figure 4(f) - (- is an enlarged view of this part, where Pt5J (4
r4) layer is being formed (FIG. 4 (0)), and state II (FIG. 4 (t)) where the PtSi formation reaction has been completed. As is clear from the figure, the polysilicon wiring and The diffusion layer (40g) is a gate oxide film (402) of approximately 20OA
Although they are electrically insulated, they are connected by interconnecting the nine silicides formed on each surface. In this way, since the gate oxide film is not etched and removed before installing polysilicon at the contact point between the polysilicon wiring and the diffusion layer wiring, the etching of the polysilicon can be stopped on the gate oxide film. Unlike the conventional example, there is no possibility that the previously exposed silicon substrate is etched and tiles are formed. Therefore, the contact resistance may change depending on the polysilicon overetching time, or the contact resistance may change due to the polysilicon overetching time. This eliminates problems such as an increase in the leakage current when the diffusion layer has a pH of 1. Further, since the polysilicon wiring and the substrate silicon are separated by an oxide film, even if P+ polysilicon is used instead of N+ polysilicon, for example, there will be no short circuit with the substrate as in the conventional example.

The above is the gate electrode (410) and arrangement! (409)'t
We have described the case where it is formed at the time of M, but for example, as shown in FIG.
10) and then the source/drain and diffusion layers are made of As.
Formed by ion implantation, then polysilicon pattern (409
) via oxidation @(416), then
The same steps as described in FIGS. 4(b) to (@) may be performed. In this case, for example, even if the impurity of polysilicon (409) is P-type boron, it will be oxidized! 17: Since (416) is 6, no PH1 coupling is created with the N-type diffusion layer (408). Also, since ohmic contact can be made between silicide and v,P+ silicon, ohmic contact can always be made between the polysilicon wiring and the diffusion layer.

The above description was limited to the case of a p-type substrate, but even if an n-type substrate is used, it is also possible to have both p-type nfIi substrates at the same time.
It can be applied in exactly the same manner to the manufacture of CMO8 circuits.

Especially P+ wiring layer-N” poly7 silicon.

Direct contact between N+ wiring layer and P+ polysilicon becomes possible, making it possible to connect p"+ to both p-type and nm substrates.
Contact can be made using either polysilicon wiring.Also, in this example, only the case where both the gate electrode and the wiring are made of polysilicon is used, but this can be applied to, for example, a two-layer structure of polysilicon and silicide. This can be applied in exactly the same way to the so-called surplus side. Even in this case, silicide can be further grown on the silicide in the step shown in FIG. 4(e). Also, in the step shown in FIG. 4(b) Instead of depositing CVD 810°, the entire surface may be thermally oxidized.Also, only when forming PT silicide by thermal annealing, it is possible to use any metal such as Pd, Ni, W, Mo, Ta, C'o, etc. Silicide may also be used.1.Also, the formation method may be ion beam mixing using ion implantation, or annealing using a laser or electron beam.Ion beam mixing using phosphorus, As, etc. allows silicide formation and impurity doping. This can be done simultaneously.In this case, if the insulator on the gate sidewall is doped with an impurity in advance, the area around the gate pad can be doped.

The conductive film selectively provided on the page as shown in FIG. 4 etc. does not have to be silicide. It is also possible to deposit metal by reacting metal fluoride gas in a reducing atmosphere at a temperature lower than the temperature at which metal silicide is formed. For example, WF・andH
! J x t 400℃~g00υ Birth R111,8
When W is reacted with K, it is possible to deposit W selectively only on the silicon and polysilicon surfaces by the CVD method. The shape is shown in the 1m5 diagram.

yeah A hot gas of M%H can also be used.

It is preferable that the various modifications described in the first embodiment can be performed in the same manner by replacing all the steps of forming Pi silinide with the selective deposition step of this metal. Alternatively, instead of selective growth, after forming electrodes and wiring, an insulating film can be bonded over the entire surface, contact holes can be made, and the two can be connected using a compound film with metal or semiconductor.

As explained above, according to the present invention, the yield is excellent, and
It is possible to obtain a contact manufacturing method that can greatly increase the degree of freedom in designing L8I.

[Brief explanation of the drawing]

(a) Φ) is a cross-sectional view of the conventional example with #X clarity, Fig. 4 (a)
~(Q is a process cross-sectional diagram explaining the first embodiment of the present invention,
FIG. 5 is a sectional view illustrating a second embodiment of the present invention. In the figure, 101, 210, 310, 410, 510...
・Gate electrode, 102 , 209 , 309 , 409
, 509... polysilicon wiring, 103, 104
, 208 , 308 , 408 , 508...diffusion layer, 105...direct contact, 4
14...i'tst (platinum silicide) 500...W (tungsten). Agent: Patent attorney Noriyuki Chika and 1 other person No. 4vIA Fig. 4

Claims (1)

[Claims] An insulating thin film is formed in a large area with a field insulating film of a semiconductor substrate, and a semiconductor film is used on top of it to form wiring and MI8.
m! ) A step of forming a gate electrode of the Tunster, and doping a large area of the substrate with impurities in the field insulating film, and then forming the wiring layer and the wiring film with metal or metal-
A method for manufacturing a semiconductor device, comprising a step of connecting with a semiconductor compound film.