JPS6258663A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a polycrystalline silicon gate wiring layer without any undercut, by depositing and etching an amorphous silicon film, and heat treating for polycrystallizing the same. CONSTITUTION:A silicon oxide film 2 is deposited on a semiconductor substrate 1. An amorphous silicon film 3 is formed on the oxide film 2. A resist pattern 4 is formed as desired on the silicon film 3 and he silicon film 3 is dry etched with the pattern 4 used as a mask. After removing the pattern 4, the structure is heat treated in the atmosphere of nitrogen, for example at 900 deg.C for 30 minutes, whereby the silicon film 3 is crystallized and becomes a polycrystalline silicon film 3'. According to this method, the polycrystalline silicon gate wiring layer can be formed without any undercut.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a polycrystalline silicon gate element.

(Summary of the Invention) The present invention provides a method for manufacturing a semiconductor device, including a step of depositing an amorphous silicon film on a substrate, a step of completely forming a mask button on the amorphous silicon hood, and a dry etching method. The method further includes the step of selectively etching the amorphous silicon film, and the step of polycrystallizing the amorphous silicon film by performing heat treatment after removing the mask pattern. By doing so, it is possible to develop a method for manufacturing a semiconductor device having a highly precise silicon gate structure.

(Prior art and problems to be solved by the invention) In recent years, semiconductor integrated circuit manufacturing technology has progressed in the direction of further miniaturization, and dry etching is widely used as a high-precision processing technology for fine patterns. Reactive ion etching is now widely used for high-precision microfabrication of polycrystalline silicon films. This method requires tens to hundreds of e.g.
According to this method, the image is etched by the sputtering action of reactive ions having high energy of V.
It is possible to perform so-called directional etching with a small difference in baton conversion. However, this method utilizes the sputtering action of ions and requires careful etching with the underlying silicon oxide film.
The tortoise ratio cannot be made very high. In recent years, the miniaturization of semiconductor integrated circuits has progressed rapidly, and the thickness of the underlying silicon oxide film in polycrystalline silicon gate elements is becoming increasingly thinner. Therefore, a technology that can achieve a high etch rate ratio between the polycrystalline silicon film and the silicon oxide film is required.

There are methods that embody this, such as a method using ECR plasma flow and a reactive ion etching method that uses magnetron discharge. The former involves etching polycrystalline silicon by using a plasma stream with low energy, while the latter uses magnetron discharge to increase the plasma density and performs etching under a low electric field.Both methods involve less ion bombardment. It is possible to obtain a high selectivity with respect to the underlying silicon oxide film.

On the other hand, the processability of a polycrystalline silicon film is highly dependent on one pattern, and it is often experienced that the shape of the batten after dry etching differs depending on the method of forming the film and the method of subsequent processing of the film. For example, a film deposited by low-pressure CVD is doped with P atoms by ion implantation, heat-treated, and deposited by a vapor phase reaction of a doping gas containing P atoms. When etching is performed using a nine-reactive ion etching method using magnetron discharge, undercuts occur on the sidewalls of the batten no matter which film is etched.

As described above, when the above-mentioned two-type polycrystalline silicon film formed by the conventional method was etched by the above-mentioned dry etching method, clear undercuts were observed on the sidewalls of the batten. Semiconductor integrated circuits require increasingly finer and more precise batten forming techniques, and it is extremely important to determine how to reduce the overall size of undercuts. Therefore, the above-mentioned drawbacks of the prior art are fatal in the production of semiconductor integrated circuit devices.

(Means for Solving the Problems) The present invention has been made to address these problems, and its purpose is to provide a complete method for manufacturing a semiconductor device having a highly accurate silicon gate structure. It is in.

Hereinafter, one embodiment of the present invention will be described with reference to all the drawings.

In FIG. 1, a very thin silicon oxide film 2 with a thickness of 100 Å or less is formed on a semiconductor substrate 1, and an amorphous silicon film 3 is formed thereon by CVD using a mixed gas of disilane and phosphine. Deposited to a thickness of approximately 3500'A. Thereafter, a desired resist pattern 4 is formed on this amorphous silicon film 3, and using this as a mask, the entire amorphous silicon film 3 is dry etched (FIG. 2).

In this case, after the etching of the amorphous silicon film 3 is completed, the etch rate ratio of the amorphous silicon to the silicon oxide film is set to be sufficiently large so that the silicon oxide film remains even if the underlying silicon oxide film is overetched. Such an etching method is necessary. For example, when the uniformity of the amorphous silicon film thickness within the wafer surface is ±10%, when it is processed,
Assuming that the uniformity of the etch rate within the wafer surface is ±5%, the etch rate ratio (selectivity) of the amorphous silicon film to the silicon oxide film must be about 10 or more. Preferably, the remaining thickness of the silicon oxide film is 50λ or more, and for this purpose, a selectivity of more than 50% is required. Etching methods that can achieve such a high selectivity include ECR plasma etching and magnetron discharge reactive ion etching (low power range).

The etching process in plasma etching of polycrystalline silicon films is generally thought to proceed along grain boundaries. Therefore, when the crystal grain size increases due to heat treatment or the like, the amount of undercut generated on the batten side wall increases.

Ma7! : In the case of a polycrystalline silicon film containing n-type impurities, it is activated by heat treatment, and the reaction with neutral radicals increases, so the etch rate increases and the undercurrent i also increases. On the other hand, in amorphous silicon film, the silicon grain size is very small, and when it is plasma etched, no undercuts occur on the side walls of the amorphous silicon film 3, as shown in Figure 2. It has also been observed that the surface of the film during etching is smooth, and that the surface of the underlying silicon oxide film 2 is also very smooth at the end of etching. The sample having the amorphous silicon film bump thus formed is subjected to an ashing process in plasma for a predetermined period of time to remove the resist bump 4. Thereafter, this sample is heat-treated at, for example, 900° C. for 30 minutes in a nitrogen atmosphere, and the amorphous silicon film 3 is crystallized to become polycrystalline silicon 1 3' (FIG. 3). At this time, the P atoms doped in the amorphous silicon layer 3 are activated, the carrier density that controls electrical conduction increases, and the specific resistance of the polycrystalline silicon layer 3' decreases. By transforming the amorphous silicon film 3 into a polycrystalline silicon film 3' and lowering the specific resistance, this film functions as a gate electrode wiring of a silicon gate element. As a method for completely polycrystallizing an amorphous silicon film, in addition to the above-mentioned method of annealing in a nitrogen atmosphere, passing an oxidation process will inevitably result in polycrystalization.
In some cases, the annealing process can be omitted. FIG. 4 is a cross-sectional view of the polycrystalline silicon film baton 3 after the formation of the amorphous silicon film and the oxidation process.
The surface of ' is covered with an oxide film 5.

By the method described above, the amorphous silicon film 3 was heat-treated to polycrystallize it to fabricate a device, and when its electrical characteristics were measured, good results were obtained. According to the present invention, an amorphous silicon film is deposited, etched, and then heat treated.
By polycrystallizing amorphous silicon, a polycrystalline silicon gate wiring layer without undercuts can be formed.

[Brief explanation of drawings]

1 to 3 show an embodiment of the method for manufacturing a semiconductor device of the present invention, and are cross-sectional views showing the process of manufacturing a polycrystalline silicon gate, and FIG. FIG. 2 is a cross-sectional view showing an example of a crystallization method. 1...Silicon substrate 2...Silicon oxide film 3...Amorphous silicon film 3'...
・・・・・・Polycrystalline silicon film 4・・・・・・Resist baton 5・・・・・・・・・Oxide film Patent applicant Nippon Telegraph and Telephone Corporation Fig. 4

Claims (1)

[Claims] A step of depositing an amorphous silicon film on a substrate, a step of forming a mask pattern on the amorphous silicon film, a step of selectively etching the amorphous silicon film by a dry etching method, and then A method for manufacturing a semiconductor device, comprising the step of removing the mask pattern and then performing heat treatment to polycrystallize the amorphous silicon film.