JP3235549B2 - Conductive layer formation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a method of forming a conductive layer of a fine pattern to be used as electrodes or wiring of a semiconductor device, in particular at least the uppermost layer of a refractory metal silicide, tungsten silicide (WSi ₂₎ or the like The conductive material layer has a <200> orientation in Miller index notation .
By performing dry etching using the TiON layer as a mask, a conductive layer having a fine pattern can be formed with high dimensional accuracy.

[0002]

_2. Description of the Related Art Conventionally, a WSi ₂ / poly Si lamination (poly S
Polycide layer such as lamination of WSi ₂ layer on i layer)
It is known that a gate electrode layer having a fine pattern made of polycide is formed by dry etching using an antireflection layer made of iN or TiON as a mask (for example, see JP-A-8-17758).

[0003]

According to the research of the inventor, the prior art described above includes a WSi ₂ layer or a WSi ₂ /
It has been found that there is a problem that the TiN (or TiON) layer is etched when the poly-Si stack is dry-etched and does not function sufficiently as a mask.

That is, when dry etching is performed on a poly-Si layer by Cl ₂ + O ₂ plasma using a TiN layer as a mask, the following reaction occurs.

[0005]

## EQU1 ## 2Si + O ₂ + 2Cl ₂ → 2SiOCl ₂ TiN + O → TiO + N Since this reaction forms an oxide film on the surface of the TiN layer,
The etch rate of the TiN layer decreases. Therefore, the TiN layer can be used as a mask.

On the other hand, when dry etching the WSi ₂ / poly Si stack with Cl ₂ + O ₂ plasma using the TiN layer as a mask, the following equation 2 occurs.

[0007]

[Number 2] _{WSi + O 2 + 3Cl 2 →} WOCl 4 + SiOCl 2 TiN + O 2 → TiO 2 + N In this case, as compared with the case of the poly-Si layer, required amount of oxygen is large. Therefore, the oxygen supply amount for breaking the Ti-N bond becomes insufficient, and an oxide film that suppresses the progress of etching is not sufficiently generated.

An object of the present invention is to provide a novel conductive layer forming method capable of forming a conductive layer of a fine pattern in which at least the uppermost layer is made of a high melting point metal silicide with high dimensional accuracy.

[0009]

According to a method of forming a conductive material layer according to the present invention, a first conductive material layer having at least an uppermost layer made of a high melting point metal silicide is formed on an insulating film covering a substrate. <20 in Miller index notation on the first conductive material layer
Forming a second conductive material layer for anti-reflection made of 0> -oriented TiON, and forming a resist layer having a desired pattern on the second conductive material layer by photolithography; Patterning the second conductive material layer by dry etching using the resist layer as a mask to leave a part of the second conductive material layer; and removing the resist layer, Patterning the first conductive material layer by dry etching using the remaining portion of the conductive material layer as a mask to leave a part of the first conductive material layer, The laminated structure of the remaining portion of the layer and the remaining portion of the second conductive material layer is used as a conductive layer for an electrode or a wiring.

In such a method for forming a conductive layer, the thickness of the resist layer is set to a value that is sufficient for patterning the second conductive material layer but not sufficient for patterning the first conductive material layer. May be. After the patterning of the second conductive material layer, the first conductive material layer is removed by dry etching using the stack of the resist layer and the remaining portion of the second conductive material layer as a mask without removing the resist layer. Patterning may leave a part of the first conductive material layer and remove the resist layer.

According to the method of the present invention, at least the uppermost layer is made of a high-melting-point metal silicide such as WSi ₂ , and the second anti-reflection second layer made of TiON having a <200> orientation is formed on the first conductive layer. A conductive material layer is formed, and a resist layer having a desired pattern is formed on the second conductive material layer by photolithography. Then, the second conductive material layer is patterned by dry etching using the resist layer as a mask, and a part of the second conductive material layer is left.

The second conductive material layer functions as an anti-reflection layer in photolithography processing to enable formation of a fine resist pattern.
The thickness may be about 50 nm. Further, since the resist layer may be thin enough to pattern the second conductive material layer, the depth of focus can be improved by photolithography, and a fine resist pattern can be formed. Therefore, the second conductive material layer can be patterned as a fine pattern layer.

After removing the resist layer, the first conductive material layer is patterned by dry etching using the remaining portion of the second conductive material layer as a mask, and a part of the first conductive material layer is left. In the dry etching process at this time,
Since the etching mask formed of the remaining portion of the second conductive material layer is thin, the microloading effect is reduced, and the dimensional accuracy during patterning is improved.

Therefore, as the conductive layer for electrodes or wiring, a conductive layer of a fine pattern composed of a laminated portion of the remaining portion of the first conductive material layer and the remaining portion of the second conductive material layer is formed with high dimensional accuracy. can do.

According to the present invention, the <200> -oriented crystal is used as an etching mask when patterning the first conductive material layer .
A TiON layer is used. This is for the following reason.

For the <200> -oriented TiN layer,
It is known that the reactivity is lower and the etch rate is lower than that of a TiN layer having a 111> orientation (for example, Jpn.J. App.
l.Phys.Vol.36 p.21586 Tab.1,2). Therefore, it is suitable as an etching mask.

On the other hand, in the <200> -oriented TiON layer, since the magnitude relation of the binding energies of Ti—N, Ti—O, and Ti—Cl is Ti—O>Ti—N> Ti—Cl. It is expected that a layer having a Ti—O bond will have a lower etch rate. The TiON layer is made of Ti-
It contains O bonds, and it is considered that most of the Ti—O bonds exist as TiO ₂ . From the comparison of the binding energy (Ti-O>Ti-N> Ti-Cl), TiO
₂ is not spontaneously etched by Cl radicals. Therefore, the TiON layer has a low etch rate and is suitable as an etching mask.

As an example, the oxygen content is 20 [at%].
Is a of the TiON layer, since 20 [at%] as oxygen, 10 [%] of Ti in the layer has become TiO _2, considered 90% is present as a Ti-N Can be Therefore, although it is a TiON layer, it is close in composition to the TiN layer, and can be said to have low reactivity and a low etch rate like the TiN layer.

[0019]

1 to 15 show a method of manufacturing a MOS type IC according to an embodiment of the present invention. Steps (1) to (15) corresponding to the respective drawings will be sequentially described. I do.

(1) A field insulating film 32 made of silicon oxide is formed on the surface of a semiconductor substrate 30 made of, for example, silicon by a known selective oxidation process. The insulating film 32 has holes 32A, 3 for arranging active regions.
2B. The gate insulating films 34A, 34 made of silicon oxide are oxidized by oxidizing the substrate surfaces in the holes 32A, 32B.
4B is formed. As the insulating films 34A and 34B, Si
₃ N ₄ film may be used.

(2) Insulating films 32, 34A, 3 on the upper surface of the substrate
After depositing an electrode material layer 36 for the gate electrode covering 4B, a conductive material layer 38 for anti-reflection and etching mask is deposited on the electrode material layer 36. As the electrode material layer 36,
A WSi ₂ / poly Si stack is formed by a CVD (chemical vapor deposition) method, and a <200> -oriented TiON layer is formed as a conductive material layer 38 by a reactive sputtering method .

The thickness of the conductive material layer 38 can be set to a minimum thickness at which an anti-reflection effect can be obtained. For example , when using a TiON layer and using i-line or g-line light for exposure,
What is necessary is just about 30-50 nm.

As an example, the reactive sputtering method is used to make <2
00> Orientation of TiON layer was formed. For comparison, a TiN layer of <111> orientation was formed by a reactive sputtering method. FIG. 16 shows the TiN layer and the TN layer thus formed.
FIG. 4 shows an X-ray diffraction pattern of the iON layer;
(A) is a TiN layer (oxygen content 5 [at%]),
(B) is a TiON layer (oxygen content 20 [at%]). As described above, the oxygen content is 20 [at]
%] Of the TiON layer, 10% of Ti is TiO ₂
And 90 [%] exist as Ti-N, which is close to the TiN layer in composition. FIG.
It can be said that the X-ray diffraction pattern of the TiON layer of (B) reflects the crystal structure of TiN.

(3) In the steps of FIGS. 3 to 5, a desired resist pattern is formed by photolithography.
First, a resist layer 40 is formed by covering the conductive material layer 38 on the upper surface of the substrate by a spin coating method or the like.

(4) Next, an exposure process is performed. That is, light-shielding mask M _A, light UV for exposing the resist layer 40 through the M _B having a desired gate electrode formation pattern
Is irradiated. At this time, the conductive material layer 38 functions as an anti-reflection layer.

(5) Next, the resist layer 40 is subjected to a development process, so that the resist layers 40A and 40A having a desired pattern are formed.
B remains. The thickness of the resist layers 40A and 40B is
It may be thin enough to pattern the conductive material layer 38 but not enough to pattern the electrode material layer 36, and may be, for example, 0.5 μm. Therefore, a fine resist pattern can be formed.

(6) The conductive material layer 38 is patterned by dry etching using the resist layers 40A and 40B as masks to leave the conductive material layers 38A and 38B (both are part of the conductive material layer 38). At this time, Cl ₂ is preferably used as an etching gas.

As an example, an ECR as shown in FIG.
The conductive material layer 38 was dry-etched using a (electron cyclotron resonance) type plasma etcher.

In the etcher shown in FIG. 17, a solenoid coil 62 is provided around the plasma chamber 60 and the chamber 60 is 2.45 through a quartz window 64.
A microwave MW of [GHz] is supplied. Chamber 6
0, an electrode 6 for holding a wafer (substrate) WF to be processed.
6 is provided, and a high frequency source RF of 13.56 [MHz] is connected to the electrode 66. In the chamber 60, an etching gas G is supplied via a gas pipe 68,
The lower part of the chamber 60 is connected to the exhaust means VAC.
In the chamber 60, uniform and high-density plasma can be generated under a wide range of pressures by the synergistic action of the microwave and the magnetic field. Further, by adjusting the high-frequency power supplied to the electrode 66, the ion energy incident on the wafer WF can be controlled.

The etching conditions for dry-etching the conductive material layer 38 using the etcher of FIG. 17 are as follows: pressure: 1 [mTorr] microwave power: 600 [W] high-frequency power: 60 [W] gas flow rate: Cl ₂ = 25 [sccm]. As the conductive material layer 38, a <200> -oriented TiON layer formed by the reactive sputtering method in the step of FIG. 2 was dry-etched. For comparison, the TiN layer of <111> orientation formed in the step of FIG. 2 was also dry-etched. The O ₂ (oxygen) content, density and etch rate of these layers are shown in Table 1 below.

[0031]

[Table 1] (7) Resist layers 40A, 40B by ashing
Is removed. As another method, the resist layers 40A and 40B may be removed by a cleaning treatment using an organic solvent or the like.

(8) The electrode material layer 36 is patterned by dry etching using the conductive material layers 38A and 38B as a mask to leave the electrode material layers 36A and 36B (both are part of the electrode material layer 36). The lamination of the electrode material layer 36A and the conductive material layer 38A forms a gate electrode layer 42A, and the lamination of the electrode material layer 36B and the conductive material layer 38B forms a gate electrode layer 42B.

As an example, the electrode material layer 36 was dry-etched using the etcher of FIG. The film structure is TiO
N (O ₂ content 20 [at%]) / WSi ₂ / poly Si
/ SiO ₂ = 40/150/150/15 [nm]. The etching conditions for WSi ₂ were as follows: pressure: 1 [mTorr] microwave power: 1400 [W] high-frequency power: 40 [W] gas flow rate: Cl ₂ / O ₂ = 25/11 [sccm] The etching conditions were as follows: pressure: 1 [mTorr] microwave power: 1400 [W] high-frequency power: 40 [W] gas flow rate: Cl ₂ / O ₂ = 25/9 [sccm] 1 [mTorr] Microwave power: 1400 [W] RF power: 40 [W] gas flow rate: was _{Cl 2 / O 2 = 25/} 9 [sccm].

In such a dry etching process, the conductive material layer 38 of <200> -oriented TiON is used.
A and 38B were hardly etched and sufficiently functioned as an etching mask.

(9) Electrode layers 42A, 42B and insulating film 3
2 is used as a mask to selectively implant ions ION of a conductivity-determining impurity into the substrate surface, thereby forming a source region and a drain region having a low impurity concentration. Then, side spacers 44A, 44A are respectively provided on the electrode layers 42A, 42B.
After B is provided, the source region and the drain region having a high impurity concentration are formed by performing the selective ion implantation process again as described above. As a result, source regions 46S ₁ and 46S ₂ and drain regions 46D ₁ and 46D ₂ each having a low concentration portion are obtained. MOS type transistor T _A is the electrode layer 42A, is intended to include a source region 46S ₁ and the drain region 46D _1, MOS-type transistor T _B, the electrode layer 42B, is intended to include source regions 46S ₂ and the drain region 46D _2.

(10) An interlayer insulating film 48 is formed on the upper surface of the substrate so as to cover the transistors T _A and T _B and the insulating film 32 by a CVD method or the like. As the insulating film 48, a silicon oxide film, a silicon nitride film, a PSG (phosphosilicate glass) film, a BPSG (boron-phosphosilicate glass) film, or the like can be used.

(11) A resist layer 50 having a desired connection hole forming pattern is formed on the insulating film 48 by photolithography. When the insulating film 48 has transparency, the conductive material layers 38A, 38 constituting the gate electrode layers, respectively.
B functions as an antireflection film when the resist layer 50 is exposed to light, so that the dimensional accuracy of the resist pattern is good above the gate electrode layer.

(12) Source connection holes 48a and gate connection holes 48b and 48c are formed in the insulating film 48 by dry etching using the resist layer 50 as a mask. When an insulating film such as titanium oxide is formed on the surfaces of the conductive material layers 38A and 38B, the connection holes 48b and 48c are formed through the conductive material layers 38A and 38B to obtain good electrical contact. , 36B. When the insulating film is not formed on the surfaces of the conductive material layers 38A and 38B, the connection holes 48b and 48c are formed in the conductive material layers 38A and 38B.
A, 38B may be formed to reach the surface. After that, the resist layer 50 is removed.

(13) A wiring material layer 52 of Al or an Al alloy is deposited on the upper surface of the substrate so as to cover the insulating film 48 and the connection holes 48a to 48c. Then, on the wiring material layer 52, a conductive material layer 54 for anti-reflection and etching mask such as TiN or TiON is formed in the same manner as described in the step of FIG.

(14) A resist layer 56 having a desired wiring formation pattern is formed on the conductive material layer 54 by photolithography.

(15) The conductive material layer 54 is patterned by dry etching using the resist layer 56 as a mask to leave the conductive material layers 54A, 54B, 54C (all of which are part of the conductive material layer 54). After removing the resist layer 56, the wiring material layer 52 is patterned by dry etching using the conductive material layers 54A, 54B, 54C as a mask, and the wiring material layers 52A, 52B, 52C (all of the wiring material layers 52 are part of the wiring material layer 52). ) Remains. Lamination of the wiring material layer 52A and the conductive material layer 54A constitute a wiring layer 58S ₁ for the source of the transistor T _A. Lamination of the wiring material layer 52B and the conductive material layer 54B constitute a wiring layer 58G ₁ for the gate of the transistor T _A. Wiring material layer 52C and conductive material layer 5
4C lamination of the wiring layers for the gate of the transistor T _B 5
Constitute the 8G _2.

In the above-described embodiment, the electrode material layer 36 is removed while the resist layer is removed in the step of FIG. 8 or FIG.
Alternatively, the wiring material layer 52 is patterned, but the patterning may be performed without removing the resist layer, using the laminated layer of the resist layer and the conductive material layers 38A, 38B (or 54A, 54B, 54C) as a mask. By doing so, when patterning the electrode material layer 36 or the wiring material layer 52, the resist layer is removed by dry etching.
Therefore, an independent process for removing the resist layer becomes unnecessary.

The WSi ₂ / polySi stack is dry-etched using a resist layer of 1.8 [μm] thickness as a mask, and the <200> -oriented Ti of 40 [nm] thickness is used.
In order to compare the electron shading damage with the case where the WSi ₂ / poly Si stack is dry-etched using the ON layer as a mask, a damage test was performed using a test element as shown in FIGS.

18 and 19 are MNOS (M
(etal-Nitride-Oxide-Semiconductor) A line and space type dummy pattern is arranged around a capacitor. On the surface of the N-type silicon substrate 70, a rectangular poly-Si electrode layer 74 is formed via an insulating film 72. The insulating film 72 is formed by stacking a Si ₃ N ₄ film on a SiO ₂ film. Electrode layer 74 and insulating film 7
SiO ₂ film 76 is formed over the 2, SiO ₂ film 76
Is formed with a connection hole corresponding to the center of the electrode layer 74. By sequentially depositing a poly-Si layer 78a and a WSi ₂ layer 78 by CVD over the connection holes and the SiO ₂ film 76, a WSi ₂ / poly-Si stack 78 is formed.
A <200> -oriented TiON layer having a thickness of 40 [nm] is formed on the WSi ₂ / poly-Si laminate 78 by a reactive sputtering method. This TiON layer has a planar pattern as shown in FIG. The resist layers 82, 82A to 82D having a thickness of 1.8 [μm] are used as a mask and are patterned by dry etching, and portions 80, 80A to 80D (80B) of the TiON layer corresponding to the resist layers 82, 82A to 82D, respectively. , 80D are not shown).

By dry etching using the resist layers 82, 82A to 82D as masks, WSi ₂ / poly Si
The laminate 78 is patterned, and portions of the laminate 78 corresponding to the resist layers 82, 82A to 82D are left. Thereafter, the resist layers 82, 82A to 82D are removed. Such a method is referred to as a first patterning method for convenience.

As another method of patterning the WSi ₂ / poly Si laminate 78, there is the following method, which is referred to as a second patterning method for convenience. That is, after removing the resist layers 82, 82A to 82D, T
The WSi ₂ / polySi stack 78 is patterned by dry etching using the remaining portions 80, 80A to 80D of the iON layer as masks, and portions of the stack 78 corresponding to the remaining portions 80, 80A to 80D of the TiON layer are left. In either the first or second patterning method, the etcher of FIG. 17 is used, and the etching conditions are as follows: pressure: 1 [mTorr] microwave power: 1800 [W] high-frequency power: 40 [W] gas flow rate: Cl ₂ / O ₂ = 25/11 [sccm].

The MNOS type capacitor is a rectangular TiO.
N layer 80 and rectangular WSi remaining under this layer 80
₂ / Poly-Si layer 78A, poly-Si electrode layer 74, insulating film 72, and silicon substrate 70. A resist layer 82 is formed around such an MNOS capacitor.
Line and space type dummy patterns corresponding to A to 82D are arranged. The line of the dummy pattern is T
It is composed of iON layers 80A to 80D and WSi ₂ / poly Si layers remaining corresponding to these layers. Rectangular T
The size of the iON layer 80 is 500 [μm] × 500 [μ
m], and the line width and the space width in the dummy pattern were 1 μm and 1.5 μm, respectively.

A second type of test element was prepared separately from the first type of test element having a dummy pattern as described above. The second type of test element differs from the first type of test element only in having no dummy pattern.

For the first type of test element according to the first and second patterning methods, a WSi ₂ / poly Si lamination 78
Flat band voltage V before and after dry etching
_FB11, V _FB12 measured, the shift amount S ₁ = _V fb12 -V
_fb11 was determined. In addition, the second type test element according to the first and second patterning methods has WSi ₂ / poly Si
The flat band voltages V _fb21 and V _fb22 before and after the dry etching of the laminate 78 are measured, and the shift amount S ₂ = V
_fb22 - _Vfb21 was determined. Further, a difference ΔS = S ₁ −S ₂ between the shift amounts of the first and second types of test elements was determined. This difference is referred to as an increase in the V _fb shift for convenience.
Table 2 shows the first patterning method (1.8 [μm]).
The increase amount of the V _fb shift is shown in comparison between the method using a resist layer having a thickness of 10 nm as a mask) and the second patterning method (using a TiON layer having a thickness of 40 nm) as a mask. is there.

[0050]

[Table 2] The greater the increase in the V _fb shift, the greater the electronic shading damage. According to Table 2, it can be seen that the second patterning method according to the present invention has a lower damage process than the first patterning method.

FIG. 20 shows the dependence of the etching selectivity on the O ₂ flow rate. The horizontal axis shows the O ₂ flow rate [sccm] during etching, and the left vertical axis shows the WSi ₂ ratio with respect to TiON. Etching selectivity (WSi ₂ / TiON)
The vertical axis on the right side shows the etching selectivity of Si to TiN (Si / TiN).

As the TiON layer, T <200> -oriented T
An iON layer was formed by a dc (direct current) magnetron sputtering apparatus. The sputtering conditions at this time were as follows: pressure: 4 [mTorr] gas flow rate: N ₂ = 84 [sccm], Ar + O ₂ = 56
[Sccm] dc power: 5 [kW].

The O ₂ flow rate ratio (Ti
ON O ₂ flow ratio) is calculated according to the following equation (3).

[0054]

(Equation 3) The O ₂ flow rate is set to 0, 5, 10, 15 [%].
, Four types of samples were prepared. O ₂
A sample having a flow rate ratio of 0 [%] becomes a TiN layer instead of a TiON layer.

The etching was performed using the etcher shown in FIG. The etching conditions at this time were as follows: pressure: 1 [mTorr] microwave power: 1400 [W] high-frequency power: 45 [W] gas flow rate: Cl ₂ = 25 [sccm], O ₂ = 0 to 13
[Sccm].

FIG. 20 shows that the etching selectivity Si / TiN and the etching selectivity WSi ₂ / TiON are improved as the O ₂ flow rate is increased. Also, for the TiN layer in which the O ₂ flow rate ratio is 0 [%], it can be seen that the etching selectivity WSi ₂ / TiN is only slightly improved even if the O ₂ flow rate is increased.

The present invention is not limited to the above embodiment, but can be implemented in various modified forms. For example, the present invention is applicable not only to dry etching of a polycide layer such as a WSi ₂ / poly Si stack, but also to dry etching of a single layer of a high melting point metal silicide such as WSi ₂ or a stack of a high melting point metal silicide. .

[0058]

As described above, according to the present invention, at least the uppermost layer is made of a refractory metal silicide such as WSi _{2 and the} antireflection conductive material layer made of <200> -oriented TiON. Since dry etching is performed as a mask, an effect that a conductive layer of a fine pattern made of a high melting point metal silicide can be formed with high dimensional accuracy can be obtained.

In addition, when a laminate of an anti-reflection conductive material layer and a thin resist layer is used as an etching mask, there is an additional effect that an independent process for removing the resist layer is not required.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a substrate illustrating a step of forming a gate insulating film in a method of manufacturing a MOS IC according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a substrate showing a deposition process of an electrode material and a conductive material following the process of FIG.

FIG. 3 is a cross-sectional view of a substrate showing a resist deposition step following the step of FIG. 2;

FIG. 4 is a cross-sectional view of a substrate showing a resist exposure step following the step of FIG. 3;

FIG. 5 is a cross-sectional view of the substrate showing a resist developing step following the step of FIG. 4;

FIG. 6 is a cross-sectional view of the substrate showing a conductive material etching step following the step of FIG. 5;

FIG. 7 is a sectional view of the substrate showing a resist removing step following the step of FIG. 6;

8 is a cross-sectional view of the substrate showing an electrode material etching step following the step of FIG. 7;

FIG. 9 is a cross-sectional view of the substrate showing a source / drain formation step following the step of FIG. 8;

FIG. 10 is a cross-sectional view of the substrate showing an interlayer insulating film forming step following the step of FIG. 9;

FIG. 11 is a cross-sectional view of the substrate showing a resist pattern forming step following the step of FIG. 10;

FIG. 12 is a cross-sectional view of the substrate showing a connection hole forming step following the step of FIG. 11;

FIG. 13 is a cross-sectional view of the substrate showing a wiring material and a conductive material deposition process following the process of FIG. 12;

FIG. 14 is a cross-sectional view of the substrate showing a resist pattern forming step following the step of FIG. 13;

FIG. 15 is a substrate cross-sectional view showing a wiring patterning step that follows the step of FIG. 14;

FIG. 16 is a diagram showing an X-ray diffraction pattern of a TiN film and a TiON layer deposited by a reactive sputtering method.

FIG. 17 is a sectional view showing an ECR type plasma etcher used in the embodiment of the present invention.

FIG. 18 is a plan view showing a resist pattern of a test element used for an electronic shading damage test.

19 is a sectional view taken along the line X-X 'in FIG.

FIG. 20 is a graph showing the dependency of the etching selectivity on the flow rate of O ₂ .

[Explanation of symbols]

30: semiconductor substrate, 32, 34A, 34B, 48: insulating film, 36: electrode material layer, 38, 54: conductive material layer, 40, 5
0, 56: resist layer, 42A, 42B: electrode layer, 5
2: wiring material _{layer, 58S 1, 58G 1, 58G} 2: wiring layer, T _A, T _B: transistor.

Continuation of front page (56) References JP-A-8-17758 (JP, A) Jpn. J. Appl. Phys. , Part 1, Vol. 36, No. 3B, pp. 1586-1588, March 1997 (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3213 H01L 21/3205

Claims (2)

(57) [Claims] A first conductive material layer having at least an uppermost layer made of a refractory metal silicide formed on an insulating film covering the substrate, and then having a Miller index notation of <2 on the first conductive material layer.
Forming a second conductive material layer made of anti-reflection made of 00> -oriented TiON ; and forming a resist layer having a desired pattern on the second conductive material layer by photolithography, Patterning the second conductive material layer by dry etching using the resist layer as a mask to leave a part of the second conductive material layer; and removing the resist layer and removing the second conductive material layer. Patterning the first conductive material layer by dry etching using the remaining portion of the conductive material layer as a mask to leave a part of the first conductive material layer, A method for forming a conductive layer, wherein a stack of a remaining portion of a layer and a remaining portion of the second conductive material layer is used as a conductive layer for an electrode or a wiring. 2. A method according to claim 1, further comprising: forming a first conductive material layer having at least an uppermost layer made of a refractory metal silicide on the insulating film covering the substrate;
A second conductive material layer made of anti-reflection made of 00> oriented TiON ; and a step of forming a resist layer having a desired pattern on the second conductive material layer by photolithography. Setting the thickness of the resist layer to an extent that is sufficient for patterning the second conductive material layer but not sufficient for patterning the first conductive material layer; Patterning the second conductive material layer by dry etching to leave a part of the second conductive material layer; and laminating the resist layer and the remaining portion of the second conductive material layer. Patterning the first conductive material layer by dry etching using a mask to leave a part of the first conductive material layer and to remove the resist layer. The conductive layer forming method using the conductive layer for the electrode or the wiring lamination of the remaining portion of the first conductive material layer remaining portions and the second conductive material layer.