JPH01302747A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01302747A JPH01302747A JP9272488A JP9272488A JPH01302747A JP H01302747 A JPH01302747 A JP H01302747A JP 9272488 A JP9272488 A JP 9272488A JP 9272488 A JP9272488 A JP 9272488A JP H01302747 A JPH01302747 A JP H01302747A
- Authority
- JP
- Japan
- Prior art keywords
- silicon film
- film
- polycrystalline silicon
- oxide film
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000011261 inert gas Substances 0.000 claims description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 239000013078 crystal Substances 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 239000012080 ambient air Substances 0.000 abstract 2
- 230000008021 deposition Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 206010000060 Abdominal distension Diseases 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 208000024330 bloating Diseases 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は半導体装置の製造方法に関するもので、特に積
層構造の電極又は電極配線を有する半導体装置に使用さ
れるものである。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and is particularly used for a semiconductor device having a laminated structure of electrodes or electrode wiring. .
（従来の技術）
近年、半導体基板主面の絶縁膜上に第１の多結晶シリコ
ン膜が形成され、前記第１の多結晶シリコン膜上に絶縁
膜を介して第２の多結晶シリコン膜が形成される、積層
構造の多結晶シリコン膜を電極又は電極配線として利用
する半導体装置がよく用いられている。そこで、このよ
うな半導体装置としてＥＰＲＯＭを例にとりあげ、その
製造方法について第３図（ａ）、（ｂ）を参照して以下
説明する。(Prior Art) In recent years, a first polycrystalline silicon film is formed on an insulating film on the main surface of a semiconductor substrate, and a second polycrystalline silicon film is formed on the first polycrystalline silicon film via an insulating film. Semiconductor devices are often used in which a multi-layered polycrystalline silicon film is used as an electrode or electrode wiring. Therefore, taking an EPROM as an example of such a semiconductor device, a method for manufacturing the same will be described below with reference to FIGS. 3(a) and 3(b).
まず、ｐ−型シリコン基板３１の表面に、周知の技術に
よりフィールド酸化膜３２を形成し、前記フィールド酸
化膜３２により囲まれた素子領域上に、熱酸化により厚
さ５００人程０の第１の熱酸化膜３３を形成する。次に
、厚さ１０００人程度０第１の多結晶シリコン膜３４を
ＬＰＣＶＤ法により全面に堆積形成し、続いてリン（Ｐ
）を熱拡散によりドープする。次に、約１０００℃にて
熱酸化を行い、前記多結晶シリコン膜３４上に厚さ５０
０人程０の第２の熱酸化膜３５を形成し、さらに前記第
２の熱酸化膜３５上には第２の多結晶シリコン膜３Ｂを
堆積形成する（（ａ）図参照）。次に、写真蝕刻法によ
り前記第２の多結晶シリコン膜３６、第２の熱酸化膜３
５、第１の多結晶シリコン膜３４及び第１の熱酸化膜３
３を順次エツチングして、それぞれコントロールグー１
−３ｔｉ−１第２のゲート酸化膜３５′、フローティン
グゲート３４′及び第１のゲート酸化膜３３−を形成す
る。次に、これら積層膜をマスクとしてｎ型不純物をイ
オン注入した後、アニールを行なってｎ十型ドレイン領
域３７及びｎ＋型ソース領域３８を形成し、さらに熱酸
化膜３９を全面に形成する。次に、前記熱酸化膜３９上
にパッシベーション膜（たとえばＰＳＧ膜）４０を堆積
形成した後、所望の領域１マコンタクトホールを設ける
。そして、全面にＡＩ！”Ｓｉ膜を堆積形成した後、バ
ターニングしてドレイン電極４１、及びソース電極４２
を形成し、ＥＦＲＯＭを完成する。First, a field oxide film 32 is formed on the surface of a p-type silicon substrate 31 by a well-known technique, and a first film with a thickness of about 500 nm is formed by thermal oxidation on the device region surrounded by the field oxide film 32. A thermal oxide film 33 is formed. Next, a first polycrystalline silicon film 34 with a thickness of about 1000 yen is deposited over the entire surface by LPCVD, and then phosphorus (P
) is doped by thermal diffusion. Next, thermal oxidation is performed at about 1000° C. to form a 50% thick film on the polycrystalline silicon film 34.
A second thermal oxide film 35 having a thickness of approximately 0.0 nm is formed, and a second polycrystalline silicon film 3B is further deposited on the second thermal oxide film 35 (see figure (a)). Next, the second polycrystalline silicon film 36 and the second thermal oxide film 3 are etched by photolithography.
5. First polycrystalline silicon film 34 and first thermal oxide film 3
3 in sequence, control group 1 respectively.
-3ti-1 A second gate oxide film 35', a floating gate 34', and a first gate oxide film 33- are formed. Next, using these laminated films as a mask, n-type impurities are ion-implanted, and then annealing is performed to form an n+ type drain region 37 and an n+ type source region 38, and a thermal oxide film 39 is further formed on the entire surface. Next, a passivation film (for example, a PSG film) 40 is deposited on the thermal oxide film 39, and then a contact hole is formed in a desired area. And AI all over! ``After depositing and forming a Si film, patterning is performed to form a drain electrode 41 and a source electrode 42.
is formed to complete the EFROM.
このように形成されたＥＦＲＯＭは、セルトランジスタ
のｎゞ吟レイン領域３７とコントロールゲート３Ｂ′と
に正の高電圧を印加して、フローティングゲート３４′
に電子を注入し、情報の書き込みを行なうデバイスであ
る。よって、この注入電子は長期間に渡って蓄積される
必要がある。しかしながら、通常時に何らかの偶発的な
原因でコントロールゲート３６″に正の高電圧が印加さ
れると、フローティングゲート３４′に蓄積されていた
注入電子が第２のゲート酸化膜３５−を経てコントロー
ルゲート８Ｇ′に吸収され、情報が消去されてしまうこ
とがある。この現象は、第２のゲート酸化膜３５′のリ
ーク電流が大きいことに起因している。In the EFROM formed in this way, a high positive voltage is applied to the n-rain region 37 of the cell transistor and the control gate 3B' to close the floating gate 34'.
This is a device that writes information by injecting electrons into the memory. Therefore, these injected electrons need to be accumulated over a long period of time. However, when a positive high voltage is applied to the control gate 36'' for some accidental reason during normal operation, the injected electrons accumulated in the floating gate 34' pass through the second gate oxide film 35- to the control gate 8G. ', and information may be erased. This phenomenon is caused by the large leakage current of the second gate oxide film 35'.
前記リーク電流は、前記第２のゲート酸化膜３５′下の
フローティングゲート３４−に不純物拡散を行なった後
、表面に形成される凹凸に原因があることが知られてい
る。これに対して、前記フローティングゲート３４′に
１ｎ−ｓｉｔｕ ｄｏｐｅｄｐｏｌｙ Ｓｉ （
不純物をその場ドーピングした多結晶シリコン膜）を利
用するとこの問題はさけられる。しかし、これを利用す
ると第１のゲート酸化膜３３′の耐圧が低下することが
報告されている（Ｊ、Ｅｌｅｃｔｒｅｈｅｍ、Ｓｏｃ、
Ｖｏｌ。It is known that the leakage current is caused by irregularities formed on the surface after impurity diffusion is performed in the floating gate 34- under the second gate oxide film 35'. On the other hand, 1n-situ doped poly Si (
This problem can be avoided by using a polycrystalline silicon film doped with impurities in-situ. However, it has been reported that using this reduces the breakdown voltage of the first gate oxide film 33' (J, Electrehem, Soc.
Vol.
１３４．１９８７，６９８．Ｄｅｒｖ Ｆｌｏｗｅｒｓに記載）。134.1987,698. Derv (described in Flowers).
（発明が解決しようとする課題）
このように、従来の半導体装置の製造方法では、電極又
は電極配線表面の凹凸が問題であった。(Problems to be Solved by the Invention) As described above, in the conventional method of manufacturing a semiconductor device, unevenness on the surface of an electrode or an electrode wiring has been a problem.
この凹凸を減らすため、前記電極又は電極配線を１ｎ−
ｓｉｔｕ ｄｏｐｅｄ ｐｏｌｙ Ｓｔにより形
成すると前記電極又は電極配線直下の絶縁膜の耐圧が低
下する欠点があった。In order to reduce this unevenness, the electrode or electrode wiring is
When formed using in-situ doped polySt, there is a drawback that the withstand voltage of the insulating film directly under the electrode or electrode wiring decreases.
よって、本発明の目的は、電極又は電極配線を１ｎ−ｓ
ｉｔｕ ｄｏｐｅｄ ｐｏｌｙ Ｓｔにより形成
して前記電極又は電極配線上の絶縁膜の耐圧を向上させ
るとともに、前記電極又は電極配線下の絶縁膜の耐圧を
低下させることのない半導体装置の製造方法を提供する
ことである。Therefore, an object of the present invention is to improve the electrode or electrode wiring by 1ns.
To provide a method for manufacturing a semiconductor device in which the withstand voltage of an insulating film on the electrode or the electrode wiring is improved by forming it using doped polySt, and the withstand voltage of the insulating film under the electrode or the electrode wiring is not reduced. It is.
［発明の構成コ
（課題を解決するための手段とその作用）上記目的を達
成するために本発明の半導体装置の製造方法は、半導体
基板主面上に絶縁膜を形成し、前記絶縁膜上に非単結晶
シリコン膜を形成する。続けて不活性ガス中でアニール
を行い前記非単結晶シリコン膜を多結晶シリコン膜にす
る。[Structure of the Invention (Means for Solving the Problems and Their Effects) In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes forming an insulating film on the main surface of a semiconductor substrate, A non-single crystal silicon film is formed. Subsequently, annealing is performed in an inert gas to convert the non-single crystal silicon film into a polycrystalline silicon film.
さらに続けて前記多結晶シリコン膜上に不純物を含んだ
非単結晶シリコン膜を形成している。Subsequently, a non-single crystal silicon film containing impurities is formed on the polycrystalline silicon film.
また、半導体基板主面上に絶縁膜を形成し、前記絶縁膜
上に非単結晶シリコン膜を形成する。Further, an insulating film is formed on the main surface of the semiconductor substrate, and a non-single crystal silicon film is formed on the insulating film.
続けてＱ、１Ｔｏｒｒ以下の真空中でアニールを行い前
記非単結晶シリコン膜を多結晶シリコン膜にする。さら
に続けて前記多結晶シリコン膜上に不純物を含んだ非単
結晶シリコン膜を形成してもよい。Subsequently, annealing is performed in a vacuum of Q, 1 Torr or less to convert the non-single crystal silicon film into a polycrystalline silicon film. Further, a non-monocrystalline silicon film containing impurities may be subsequently formed on the polycrystalline silicon film.
このような半導体装置の製造方法によれば、非単結晶シ
リコン膜に不活性ガス中又は０．１Ｔｏｒｒ以下の真空
中でアニールを施して、前記非単結晶シリコン膜を結晶
の粒径が大きく粒界の数も少ない多結晶シリコン膜に変
換しているので、前記多結晶シリコン膜上に不純物を含
んだ非単結晶シリコン膜を形成しても、前記多結晶シリ
コン膜下の絶縁膜に不純物が拡散するのを緩和でき、前
記絶縁膜の耐圧の低下を防ぐことができる。According to such a method of manufacturing a semiconductor device, the non-single crystal silicon film is annealed in an inert gas or in a vacuum of 0.1 Torr or less, so that the non-single crystal silicon film has large crystal grains. Since the polycrystalline silicon film is converted into a polycrystalline silicon film with a small number of fields, even if a non-monocrystalline silicon film containing impurities is formed on the polycrystalline silicon film, impurities will not be introduced into the insulating film under the polycrystalline silicon film. Diffusion can be alleviated and a decrease in breakdown voltage of the insulating film can be prevented.
（実施例）
以下、図面を参照して本発明の一実施例を詳細に説明す
る。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は、本発明の半導体装置の製造方法をＥＰＲＯ〜
１のゲート部分に適用したものである。FIG. 1 shows a method for manufacturing a semiconductor device according to the present invention using EPRO~
This is applied to the gate part of No.1.
まず、シリコン基板ｌの主面に熱酸化により厚さ５００
人程０の第１のゲート酸化膜（絶縁膜）２を形成する。First, the main surface of the silicon substrate 1 is thermally oxidized to a thickness of 500 mm.
A first gate oxide film (insulating film) 2 having a thickness of 0 is formed.
次に、ＬＰＧＶＤ装置を用い、反応温度４００〜６００
℃で５ｉＨ４（ンラン）ガスを熱分解し、前記ゲート酸
化膜２上に非単結晶シリコン膜３を少なくとも３０人の
厚さで堆積形成する。なお、反応温度６００℃以下では
、Ｓｔ原子の結晶化が殆んど進行しないことから、大部
分が非晶質のシリコン膜が形成される。また、前記非単
結晶シリコン膜３の形成において、同時にＰＨ３ガスを
混ぜることにより濃度１×１０２０ｃｍ”以下のリン（
Ｐ）をドープしても良い。続いて、前記基板１を外気に
さらすことなく、炉の温度を９００℃程度に上げた後、
不活性ガス（たとえばＡｒガス）中で約３０分アニー・
ルを行い、前記非単結晶シリコン膜３に結晶粒を生じさ
せて結晶化する。この結晶は、６００℃以上の炉内で行
なうことにより多結晶シリコン膜３となる。さらに、前
記基板 １を外気にさらすことなく、ＰＨ３とＳｉＨ４
の混合ガス中において、Ｌ Ｐ ＣＶ Ｄ法により反応
温度約７００℃で濃度Ｉ Ｘ １０ ”ｃｍ”３以上の
リンがドープされた多結晶シリコン膜（非単結晶シリコ
ン膜）４を厚さ１０００人程度０なるように形成する（
ｉｎ−ｓｉｔｕ ｄｏｐｅｄｐｏｌｙ Ｓｔ）。な
お、下地へのリンの拡散は、結晶の粒径が大きく粒界の
数も少ない前記多結晶シリコン膜３が緩和している。次
に、約１０００℃で前記多結晶シリコン膜４を熱酸化し
、厚さ５００人程０の第２のゲート酸化膜５を形成する
。Next, using an LPGVD device, the reaction temperature was 400 to 600.
A non-single crystal silicon film 3 is deposited on the gate oxide film 2 to a thickness of at least 30 nm by thermally decomposing 5iH4 gas at .degree. Note that at a reaction temperature of 600° C. or lower, crystallization of St atoms hardly progresses, so that a mostly amorphous silicon film is formed. In addition, in forming the non-single crystal silicon film 3, by simultaneously mixing PH3 gas, a concentration of phosphorus (
P) may be doped. Subsequently, the temperature of the furnace was raised to about 900° C. without exposing the substrate 1 to the outside air, and then
Anneal for about 30 minutes in an inert gas (e.g. Ar gas).
Then, crystal grains are generated in the non-single crystal silicon film 3 and crystallized. This crystallization is performed in a furnace at a temperature of 600° C. or higher to form a polycrystalline silicon film 3. Furthermore, PH3 and SiH4 can be combined without exposing the substrate 1 to the outside air.
In a mixed gas of Form it so that the degree is 0 (
in-situ dopedpoly St). Note that the polycrystalline silicon film 3, which has a large crystal grain size and a small number of grain boundaries, eases the diffusion of phosphorus into the underlying layer. Next, the polycrystalline silicon film 4 is thermally oxidized at about 1000° C. to form a second gate oxide film 5 having a thickness of about 500°C.
次に、前記ゲート酸化膜５上に面抵抗的２０Ωの多結晶
シリコン膜６を厚さ３５００人程度０堆積形成する。次
に、写真蝕刻法により、前記多結晶シリコン膜６、第２
のゲート酸化膜５、多結晶シリコン膜４及び多結晶シリ
コン膜３を順次エツチングする。なお、前記多結晶シリ
コン膜６はコントロールゲートとなり、前記多結晶シリ
コン膜３゜４でフローティングゲートが構成される。Next, a polycrystalline silicon film 6 having a sheet resistance of 20 Ω is deposited on the gate oxide film 5 to a thickness of about 3,500 Ω. Next, by photolithography, the polycrystalline silicon film 6 and the second
Gate oxide film 5, polycrystalline silicon film 4, and polycrystalline silicon film 3 are sequentially etched. The polycrystalline silicon film 6 serves as a control gate, and the polycrystalline silicon film 3.4 constitutes a floating gate.
ところで、上記実施例では非単結晶シリコン膜３を形成
した後、続けて不活性ガス中でアニールを行っているが
、これに変えて０．１Ｔｏｒｒ以下の真空中でアニール
を行っても、結晶の粒径が大きく粒界の数も少ない多結
晶シリコン膜が形成できる。Incidentally, in the above embodiment, after forming the non-single crystal silicon film 3, annealing is performed in an inert gas, but even if the annealing is performed in a vacuum of 0.1 Torr or less, the crystalline A polycrystalline silicon film with a large grain size and a small number of grain boundaries can be formed.
次に、このように形成されるＥＦＲＯＭと従来の製造方
法により形成されるＥＰＲＯＭについて、ゲート酸化膜
の耐圧とブローティングゲート中のリン濃度との関係を
示したのが第２図（ａ）。Next, FIG. 2(a) shows the relationship between the breakdown voltage of the gate oxide film and the phosphorus concentration in the bloating gate for an EFROM formed in this manner and an EPROM formed by the conventional manufacturing method.
（ｂ）である。（ａ）図はフローティングゲート下のゲ
ート酸化膜（第１のゲート酸化膜）の耐圧とフローティ
ングゲート中のリン濃度の関係を示している。（ｂ）図
はフローティングデー１−上のゲート酸化膜（第２のゲ
ート酸化膜）の耐圧とフローティングゲート中のリン濃
度の関係を示している。なお、従来例１はフローティン
グゲー！・中へのリンの導入を熱拡散により行なった場
合であり、従来例２はフローティングゲート中へのリン
の導入を１ｎ−ｓｉｔｕ ｄｏｐｅｄ ｐｏｌｙＳ
ｉを利用することにより行なった場合である。(b). The figure (a) shows the relationship between the breakdown voltage of the gate oxide film (first gate oxide film) under the floating gate and the phosphorus concentration in the floating gate. The figure (b) shows the relationship between the withstand voltage of the gate oxide film (second gate oxide film) on the floating gate 1- and the phosphorus concentration in the floating gate. In addition, conventional example 1 is a floating game!・This is a case where phosphorus is introduced into the floating gate by thermal diffusion, and in conventional example 2, phosphorus is introduced into the floating gate using a 1n-situ doped polyS
This is a case where this is done by using i.
図示するように、本発明の製造方法によれば、第１のゲ
ート酸化膜と第２のゲート酸化膜のどちらの耐圧もフロ
ーティングゲート中のリン濃度によらず良好であること
がわかる。As shown in the figure, according to the manufacturing method of the present invention, the breakdown voltage of both the first gate oxide film and the second gate oxide film is good regardless of the phosphorus concentration in the floating gate.
なお、本発明は上記実施例に示した
ＥＦＲＯＭに限らず、積層構造の電極又は電極配線を有
する半導体装置に対して有効である。Note that the present invention is effective not only for the EFROM shown in the above embodiments but also for semiconductor devices having stacked electrodes or electrode wiring.
［発明の効果コ
以上、説明したように本発明によれば次のような効果を
奏する。[Effects of the Invention] As explained above, the present invention provides the following effects.
電極又は電極配線をｉｎ−ｓｉｔｕ
ｄｏｐｅｄ ｐｏｌｙ Ｓｉにより形成しているの
で前記電極又は電極配線上の絶縁膜の耐圧を向上させる
ことができる。それとともに、前記電極又ぼｒｉｂ配線
の形成において、まず非単結晶シリコン膜を不活性ガス
中又は０．１Ｔｏｒｒ以下の真空中でアニールすること
によりできる、結晶の粒径が大きく粒界の数も少ない多
結晶シリコン膜を不純物拡散防止用として形成している
ので、前記電極又は電極配線下の絶縁膜の耐圧も同時に
向上させることができる。Since the electrodes or electrode wirings are formed of in-situ doped poly Si, the withstand voltage of the insulating film on the electrodes or electrode wirings can be improved. At the same time, in forming the electrode or rib wiring, first, the non-single crystal silicon film is annealed in an inert gas or in a vacuum of 0.1 Torr or less, so that the crystal grain size is large and the number of grain boundaries is small. Since a small amount of polycrystalline silicon film is formed to prevent impurity diffusion, the withstand voltage of the insulating film under the electrode or electrode wiring can also be improved at the same time.
第１図は本発明の一実施例に係わる半導体装置の製造方
法について説明するための断面図、第２図は本発明及び
従来の半導体装置の製造方法により形成されたＥＦＲＯ
Ｍのゲート酸化膜の耐圧とフローティングゲート中のリ
ン濃度の関係を説明するための図。第３図は従来の半導
体装置の製造方法について説明するための断面図である
。
２・・・ゲート酸化膜（絶縁膜）、３・・・非単結晶シ
リコン膜（アニール後は多結晶シリコン膜）、４・・・
多結晶シリコン膜（非単結晶シリコン膜）。
出願人代理人 弁理士 鈴江武彦
第１図
７０−９４．；’、ｆ、’＋’ ； ｈ中 （ｘ ｌ
Ｏ”ｃｒｒ＋３）第２図FIG. 1 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of an EFRO formed by the method of manufacturing a semiconductor device of the present invention and the conventional method.
FIG. 3 is a diagram for explaining the relationship between the breakdown voltage of the gate oxide film of M and the phosphorus concentration in the floating gate. FIG. 3 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device. 2... Gate oxide film (insulating film), 3... Non-monocrystalline silicon film (polycrystalline silicon film after annealing), 4...
Polycrystalline silicon film (non-monocrystalline silicon film). Applicant's agent Patent attorney Takehiko Suzue Figure 1 70-94. ;', f, '+'; in h (x l
O”crr+3) Figure 2
Claims (2)
記絶縁膜上に非単結晶シリコン膜を形成する工程と、不
活性ガス中でアニールを行い前記非単結晶シリコン膜を
多結晶シリコン膜に変換する工程と、前記多結晶シリコ
ン膜上に不純物を含んだ非単結晶シリコン膜を形成する
工程とを具備することを特徴とする半導体装置の製造方
法。(1) A step of forming an insulating film on the main surface of a semiconductor substrate, a step of forming a non-monocrystalline silicon film on the insulating film, and annealing in an inert gas to convert the non-single-crystalline silicon film into a polycrystalline silicon film. A method for manufacturing a semiconductor device, comprising the steps of converting the polycrystalline silicon film into a silicon film, and forming a non-monocrystalline silicon film containing impurities on the polycrystalline silicon film.
記絶縁膜上に非単結晶シリコン膜を形成する工程と、０
．１Ｔｏｒｒ以下の真空中でアニールを行い前記非単結
晶シリコン膜を多結晶シリコン膜に変換する工程と、前
記多結晶シリコン膜上に不純物を含んだ非単結晶シリコ
ン膜を形成する工程とを具備することを特徴とする半導
体装置の製造方法。(2) forming an insulating film on the main surface of the semiconductor substrate; forming a non-single crystal silicon film on the insulating film;
．． The method includes a step of converting the non-single crystal silicon film into a polycrystalline silicon film by annealing in a vacuum of 1 Torr or less, and a step of forming a non-single crystal silicon film containing impurities on the polycrystalline silicon film. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63092724A JPH0687465B2 (en) | 1988-04-15 | 1988-04-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63092724A JPH0687465B2 (en) | 1988-04-15 | 1988-04-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01302747A true JPH01302747A (en) | 1989-12-06 |
| JPH0687465B2 JPH0687465B2 (en) | 1994-11-02 |
Family
ID=14062393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63092724A Expired - Lifetime JPH0687465B2 (en) | 1988-04-15 | 1988-04-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0687465B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004096093A (en) * | 2002-07-18 | 2004-03-25 | Hynix Semiconductor Inc | Manufacture of semiconductor memory element |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6258663A (en) * | 1985-09-09 | 1987-03-14 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPS6329954A (en) * | 1986-07-23 | 1988-02-08 | Toshiba Corp | Manufacture of semiconductor device |
-
1988
- 1988-04-15 JP JP63092724A patent/JPH0687465B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6258663A (en) * | 1985-09-09 | 1987-03-14 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPS6329954A (en) * | 1986-07-23 | 1988-02-08 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004096093A (en) * | 2002-07-18 | 2004-03-25 | Hynix Semiconductor Inc | Manufacture of semiconductor memory element |
| JP4669655B2 (en) * | 2002-07-18 | 2011-04-13 | 株式会社ハイニックスセミコンダクター | Manufacturing method of semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0687465B2 (en) | 1994-11-02 |
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