JPH0613473A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the amount of over etchinging by changing a hole area on the wiring layer depending on film thickness of a wiring layer. CONSTITUTION:A first insulating film 102 is formed on a first wiring layer 10, a second wiring layer 103 is formed on the first insulating film 102, a second insulating film 104 is formed on the second wiring layer 103 and holes are respectively formed on the first and second wiring layers 101, 103. In this case, areas of holes formed in the first wiring layer 101 and second wiring layer 103 are different depending on film thickness of the wiring layers 101, 103. For instance, the first wiring layer 101 is formed in the thickness of 0.1mum, the second wiring layer 103 is formed in the thickness of 0.04mum, the hole area on the first wiring layer 101 is set to 1.0mum<2> (hole diameter: 1.0mum) and the hole area of the second wiring layer 103 is set to 0.25mum<2> (hole diameter: 0.5mum). Thereby, the amount of over etching can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring layer having holes on the wiring and a method for etching the wiring layer.

[0002]

2. Description of the Related Art A conventional semiconductor device and its manufacturing method are shown in FIGS. In FIG. 7, 701 is the first
Wiring layer, 702 is a first insulating film, 703 is a second wiring layer, 704 is a second insulating film, and 705 is a resist.
FIG. 2 shows an RIE type dry etching apparatus in which a gas is introduced into a reaction chamber and a high frequency is applied between electrodes arranged in parallel to plasmaize the gas to perform etching. 201 is an application electrode and 202 is a ground. Electrodes, 203 are wafers, 204
Is an RF power supply.

In FIG. 7, the first substrate is placed above the Si substrate.
The wiring layer 701 is formed of, for example, a poly-Si wiring layer. The second wiring layer 703 is formed of, for example, a poly-Si wiring layer with a first insulating film 702 (for example, a silicon dioxide film formed by a chemical vapor deposition method using monosilane and oxygen) interposed therebetween. A second insulating film 704 (for example, phosphorus silicate glass by a chemical vapor deposition method using monosilane, oxygen, and phosphine) is formed thereon. The resist 705 is formed on the first wiring layer 701 and the second wiring layer 703 with a hole diameter of 0.8 μm.
Pattern on top. Holes are formed by anisotropic etching using the patterned resist 705 as a mask.

In FIG. 2, the pressure for forming the holes in the apparatus is, for example, 90 mTorr, the magnitude of the applied RF power is, for example, 900 W, and the etching process gas is, for example, C ₂ F _{6 10} sccm and CHF ₃ 90 sccm.
When etching is performed at a chamber temperature of, for example, 15 ° C., when the hole area is, for example, 0.64 μm ² , the etching rate is 8530.4 Å / min and the uniformity is 10.
7%, and the selection ratio to poly-Si was 14.57.

[0005]

However, as compared with the first poly-Si wiring layer 701, the second poly-Si wiring layer 703 has a larger etching amount corresponding to the thickness of the first insulating film 702, resulting in over-etching. There is a difference in etching amount. For example, when the film thickness of the first insulating film 702 is 0.2 μm and the film thickness of the second insulating film 704 is 1.2 μm, the holes formed on the first poly-Si wiring layer 701 are overfilled. When the etching amount is 30%, the second poly S
The over-etching amount of the holes formed on the i wiring layer 703 is 44%, and the first poly-Si wiring layer 701 is formed.
Is larger than the over-etching amount. Therefore, the second poly-Si wiring layer 703 is a thin film (for example, 400).
And the selection ratio with respect to the insulating film is small (for example, 14.57)
In this case, if the over-etching amount of the holes formed on the first poly-Si wiring layer 701 is set to 30%, the second poly-Si wiring layer 703 may be removed.

In order to prevent the formation of holes that escape the second poly-Si wiring layer 702, the formation of holes on the first poly-side wiring layer 701 and the formation of holes on the second poly-Si wiring layer 702. The holes may be formed separately. However, in that case, patterning the resist,
The process of forming a hole for performing anisotropic etching and peeling the resist is performed twice, which is complicated.

Therefore, the present invention solves such a conventional problem, and an object of the present invention is to perform etching by making the hole area on the wiring layer different depending on the film thickness of the wiring layer. The purpose is to control the speed and reduce the etching amount by overetching.

[0008]

The semiconductor device of the present invention comprises:
A first wiring layer formed on a semiconductor substrate; a first insulating film formed on the first wiring layer; a second wiring layer formed on the first insulating film; A second insulating film formed on the second wiring layer, on the first wiring layer, and on the second wiring film;
Areas of the holes formed on the wiring layer and the holes formed on the first wiring layer and the second wiring layer are different, and the size of the hole area is different depending on the film thickness of the wiring layer. It is characterized by Further, the method for manufacturing a semiconductor device of the present invention, a gas is introduced into the reaction chamber, the gas is turned into plasma,
In the dry etching method for etching a silicon oxide film, a gas represented by the general formula C _X F _Y and a gas represented by the general formula C _X H _Y F _Z are used as the etching gas.

[0009]

The etching rate can be slowed by reducing the hole area of the hole having the above structure to 1.0 μm ² or less. FIG. 6 shows a graph of the relationship between the hole area and the etching rate. In FIG. 6, the vertical axis represents the etching rate and the horizontal axis represents the hole area. In FIG. 6, the hole area is 2.25 μm ² (hole diameter 1.5 μm), 1.0 μm ² (hole diameter 0.5 μm),
When it becomes as small as 0.25 μm ² (hole diameter 0.5 μm), the etching rate is 9035.4 Å / min, 899
The etching rate becomes 1.0 Å / min and 7622.3 Å / min, and when the hole area becomes 1.0 μm ² or less, the etching rate rapidly decreases. Therefore, the second thin film
By making the hole area for the wiring layer smaller than the hole area for the first wiring layer, the etching rate can be slowed and the etching amount for overetching can be reduced.

Further, holes can be formed by using an etching gas or an apparatus which has conventionally been used for etching a silicon oxide film.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of an essential part showing an embodiment of a semiconductor device of the present invention, in which 101 is a first wiring layer and 102 is a first wiring layer.
Is an insulating film, 103 is a second wiring layer, 104 is a second insulating film, and 105 is a resist. FIG. 2 is a cross-sectional view of an essential part showing an embodiment of a semiconductor device of the present invention, in which a gas is introduced into a reaction chamber and a high frequency is applied between electrodes placed in parallel to turn the gas into a plasma to perform etching. This is a RIE type dry etching device. 201 is an application electrode, 202 is a ground electrode, 203 is a wafer, and 204 is an RF power supply.

In FIG. 1, the first substrate is provided above the Si substrate.
The wiring layer 101 is formed of, for example, a poly-Si wiring layer and has a film thickness of, for example, 0.1 μm. The first insulating film 10 is formed thereon.
2 (for example, a silicon dioxide film formed by a chemical vapor deposition method using monosilane and oxygen) with a film thickness of, for example, 0.2 μm, and the second wiring layer 103 is formed of, for example, a poly-Si wiring layer and the film thickness thereof. Of 0.04 μm, for example. The second insulating film 104 (for example, phosphorus silicate glass by a chemical vapor deposition method using monosilane, oxygen and phosphine) is formed thereon with a film thickness of 1.2 μm, for example. Then, the resist 105 is formed on the first wiring layer 101, for example, and the hole area is 1.0 μm ² (hole diameter 1.
And a hole having a hole area of 0.25 μm ² (hole diameter 0.5 μm) is patterned on the second wiring layer 103. The patterned resist 10
Holes are formed by anisotropic etching using 5 as a mask.

In FIG. 2, the holes are formed by setting the pressure in the apparatus at 90 mTorr and the magnitude of the applied RF power at 9 m.
00W, etching process gas is C ₂ F ₆ 10scc
m and CHF ₃ 90sccm, chamber temperature 15 ℃
When etching is performed under the conditions of, the etching rate is 899.
1.0Å / min (hole area 1.0μm ² ) and 76
22.3Å / min (hole area 0.25 μm ² ),
Uniformity is 10.7%, selection ratio to poly Si is 14.5
It was 7.

Since the hole areas are 1.0 μm ² and 0.25 μm ² , the etching rate is 89
If there is a difference between 91.0Å / min and 7622.3Å / min and the over-etching amount of holes formed on the first poly-Si wiring layer 101 is, for example, 30%, the second poly-Si wiring layer 103 is formed. The amount of overetching of the holes formed above is 25%, and the hole area is 0.
At 64 μm ² , the difference was small compared to 44% of the overetching amount at the same time. In addition, the second poly-Si
The etching amount of the wiring layer 103 is 240 Å, the hole area is 0.64 μm ² , and the etching amount of the same amount is 423.
It became smaller than Å. Therefore, by making the hole area to the second wiring layer having a small film thickness smaller than the hole area to the first wiring layer, it is possible to reduce the etching rate and reduce the etching amount for over etching. Therefore, it is possible to prevent the formation of holes that escape the second wiring layer. In addition, holes can be formed by using an etching gas or a device that conventionally etches a silicon oxide film.

The above is the description of the first embodiment.

FIG. 3 is a cross-sectional view of an essential part showing an embodiment of the semiconductor device of the present invention. 301 is a LOCOS (Locoal Oxidation of Silicon, hereinafter abbreviated as LOCOS), 302 is an oxide film, and 303 is First wiring layer, 30
4 is a source / drain region, 305 is a first insulating film, 3
Reference numeral 06 is a second wiring layer, 307 is a second insulating film, and 308 is a resist. FIG. 4 is a cross-sectional view of an essential part showing an embodiment of a semiconductor device of the present invention, in which a gas is introduced into a reaction chamber, the gas is turned into plasma by a microwave, and a high frequency is applied as necessary to perform etching. It is an ECR type dry etching device. 401 is an application electrode, 402 is a ground electrode,
Reference numeral 403 is a wafer, 404 is an RF power supply, 405 is a microwave power supply, and 406 is a magnet coil.

In FIG. 3, the LOCOS 30 is formed on the Si substrate.
After forming 1, the oxide film 302 is formed on the entire surface. A first wiring layer 303 is formed thereon as a gate electrode, for example, a poly-Si wiring layer, and its thickness is, for example, 0.2 μm. With the structure, using the first wiring layer 303 as a mask,
Source / drain regions 304 are formed by implanting ions, and the oxide film 302 other than the first wiring layer is removed by hydrofluoric acid etching. A first insulating film 305 (for example, a silicon dioxide film formed by chemical vapor deposition using monosilane and oxygen) is formed on the first insulating film 305, and the second wiring layer 306 is made of poly-Si with a film thickness of 0.4 μm. Wiring layer, its thickness is 0.05μ
It is formed by m. A second insulating film 307 (for example, phosphorus silicate glass by a chemical vapor deposition method using monosilane, oxygen, and phosphine) is formed on the second insulating film 307 with a thickness of 0.8 μm.
It is formed by m. The resist 308 is formed on the first
A hole having a hole area of 1.0 μm ² (hole diameter of 1.0 μm) and a hole area of 0.25 μm ² (hole diameter of 0.5 μm) are patterned on the second wiring layer 306. A hole is formed by anisotropic etching using the patterned resist 308 as a mask.

In FIG. 4, the holes are formed in the apparatus at a pressure of 2.0 mTorr, applied RF power of 300 W, microwave power of 200 mA, etching process gas of C ₃ F _{8 10} sccm and CH ₂ F _2. 15
When etching is performed under the conditions of sccm and chamber temperature of 20 ° C., the etching rate is 5440.0 Å / min
(Hole area is 1.0 μm ² ) and 4611.5Å / mi
n (hole area is 0.25 μm ² ), uniformity is 10.4
%, And the selection ratio with respect to poly-Si was 16.18. Here, since the hole areas are set to 1.0 μm ² and 0.25 μm ² , the etching rate is 5440.0 Å / mi.
n and 4611.5 Å / min, and when the over-etching amount of holes formed on the first poly-Si wiring layer 301 is, for example, 30%, the second poly-Si
The over-etching amount of the holes formed on the wiring layer 306 was 24%, which was smaller than the over-etching amount of 44% of the same area when the hole area was 0.64 μm ² . Further, the etching amount of the second poly-Si wiring layer 306 becomes 208Å, and the hole area is 0.64μ.
It becomes smaller than the 423Å etching amount of time same in m ^2. Therefore, by making the hole area to the second wiring layer having a small film thickness smaller than the hole area to the first wiring layer, it is possible to reduce the etching rate and reduce the etching amount for over etching. Therefore, it is possible to prevent the formation of holes that escape the second wiring layer. In addition, holes can be formed by using an etching gas or a device that conventionally etches a silicon oxide film.

The above is the description of the second embodiment.

FIG. 5 is a cross-sectional view of an essential part showing an embodiment of a semiconductor device of the present invention. 501 is LOCOS (Locoal Oxidation of Silicon, hereinafter abbreviated as LOCOS), 502 is an oxide film, and 503 is Gate electrode, 504
Is a first wiring layer as a source / drain region, 505 is a first insulating film, 506 is a second wiring layer, 507 is a second insulating film, and 508 is a resist.

In FIG. 5, a LOCOS 50 is formed on a Si substrate.
After forming No. 1, an oxide film 502 is formed on the entire surface. A gate electrode 503 is formed on it by, for example, poly-Si. In the structure, the first wiring layer 5 as a source / drain region is formed by implanting ions with the gate electrode 503 as a mask.
04 is formed, and the oxide film 502 other than the gate electrode is removed by hydrofluoric acid etching. A first insulating film 505 is formed thereon.
(For example, a silicon dioxide film formed by a chemical vapor deposition method using monosilane and oxygen), the second wiring layer 506 is a poly-Si wiring layer, and the film thickness is It is formed with a thickness of 0.05 μm. A second insulating film 507 (for example, phosphorus silicate glass by a chemical vapor deposition method using monosilane, oxygen, and phosphine) and a film thickness of 0.8 μm are formed thereon. Then, the resist 508 is formed on the first wiring layer 504 as the source / drain regions, and the hole area is 1.0 μm, for example.
A hole having a hole area of, for example, 0.25 μm ² (hole diameter of 0.5 μm) is patterned on the second wiring layer 506 and a hole of m ² (hole diameter of 1.0 μm). A hole is formed by anisotropic etching using the patterned resist 508 as a mask.

In the same manner as above, in FIG. 2, the formation of the holes is performed by setting the pressure in the apparatus at 1500 mTorr, the magnitude of the applied RF power at 825 W, and the etching process gas at C.
When etching was performed under the conditions of F ₄ 30 sccm and CHF ₃ 70 sccm and the chamber temperature of −7 ° C., the etching rate was 8540.7 Å / min (hole area 1.0 μm
m ² ) and 7239.9Å / min (hole area 0.2
5 μm ² ), the uniformity was 5.3%, and the selection ratio with respect to poly-Si was 13.64.

Since the hole areas are 1.0 μm ² and 0.25 μm ² , the etching rate is 85%.
If there is a difference between 40.7 Å / min and 7239.9 Å / min, and the over-etching amount of the holes formed on the first wiring layer 504 is, for example, 30%, then on the second poly-Si wiring layer 506. The over-etching amount of the formed hole is 44%, and the hole area is 0.64 μm.
Compared to 63% of the amount of overetching in the case of ² , the difference was small. In addition, the second poly-Si wiring layer 5
The etching amount of 06 was 387Å, which was smaller than the etching amount of 554Å at the same time when the hole area was 0.64 μm ² . Therefore, by making the hole area to the second wiring layer having a small film thickness smaller than the hole area to the first wiring layer, it is possible to reduce the etching rate and reduce the etching amount for over etching. Therefore, it is possible to prevent the formation of holes that escape the second wiring layer. In addition, holes can be formed by using an etching gas or a device that conventionally etches a silicon oxide film.

The above is the description of the third embodiment.

In addition to the above embodiment, the present invention can be applied to the case where the number of wiring layers is three or more.

The embodiment of the present invention has been described above with reference to the drawings.
I explained an example. However, it goes without saying that the present invention is not limited to this, and can be realized by changing the hole area by the film thickness of the wiring.

[0027]

As described above, the present invention reduces the etching rate by making the hole area to the thin second wiring layer smaller than the hole area to the first wiring layer. Since the etching amount for overetching can be reduced, it is possible to prevent the formation of holes that pass through the second wiring layer. In addition, holes can be formed by using an etching gas or a device that conventionally etches a silicon oxide film.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts showing a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part showing an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention.

FIG. 3 is a cross-sectional view of essential parts showing an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention.

FIG. 4 is a cross-sectional view of essential parts showing an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention.

FIG. 5 is a cross-sectional view of essential parts showing a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

FIG. 6 is a main part graph showing an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention.

FIG. 7 is a cross-sectional view of essential parts showing a conventional semiconductor device and a method for manufacturing the same.

[Explanation of symbols]

 101 ... 1st wiring layer 102 ... 1st insulating film 103 ... 2nd wiring layer 104 ... 2nd insulating film 105 ... Resist 201 ... Applied electrode 202 ... -Grounding electrode 203 ... Wafer 204 ... RF power supply 301 ... LOCOS 302 ... Oxide film 303 ... First wiring layer 304 ... Source / drain region 305 ... First insulation Film 306 ... Second wiring layer 307 ... Second insulating film 308 ... Resist 401 ... Applying electrode 402 ... Ground electrode 403 ... Wafer 404 ... RF power supply 405 ... Microwave power source 406 ... Magnet coil 501 ... LOCOS 502 ... Oxide film 503 ... Gate electrode 504 ... Source / drain region, first wiring layer 505 ... First insulating film 5 06 ... Second wiring layer 507 ... Second insulating film 508 ... Resist 701 ... First wiring layer 702 ... First insulating film 703 ... Second wiring layer 704 ... Second insulating film 705 ... Resist

Claims (7)

[Claims] 1. A first wiring layer formed on a semiconductor substrate, a first insulating film formed on the first wiring layer, and a second insulating film formed on the first insulating film. A wiring layer, a second insulating film formed on the second wiring layer, holes formed on the first wiring layer and the second wiring layer, on the first wiring layer, and on the first wiring layer A semiconductor device, wherein the areas of the holes formed on the second wiring layer are different, and the size of the hole area is different depending on the film thickness of the wiring layer. 2. A dry etching method in which a gas is introduced into a reaction chamber, the gas is turned into plasma, and a silicon oxide film is etched, and the etching gas has a general formula of C _X.
The method of manufacturing a semiconductor device according to claim 1, wherein a gas represented by F _Y and a gas represented by the general formula of C _X H _Y F _Z are used. 3. The method of manufacturing a semiconductor device according to claim 2, wherein CF ₄ is used as the gas represented by the general formula of C _X F _Y. 4. The method of manufacturing a semiconductor device according to claim 2, wherein C ₂ F ₆ is used as the gas represented by the general formula of C _X F _Y. 5. The method of manufacturing a semiconductor device according to claim 2, wherein C ₃ F ₈ is used as the gas represented by the general formula of C _X F _Y. 6. The method of manufacturing a semiconductor device according to claim 2, wherein CHF ₃ is used as the gas represented by the general formula of C _X H _Y F _Z. 7. The method of manufacturing a semiconductor device according to claim 2, wherein CH ₂ F ₂ is used as the gas represented by the general formula of C _X H _Y F _Z.