JPH0642484B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a polycrystalline silicon gate element.

(Summary of the Invention) The present invention is a method for manufacturing a semiconductor device, which comprises depositing an amorphous silicon film doped with impurities on a substrate, and forming a mask pattern on the impurity-doped amorphous silicon film. , A step of selectively etching the impurity-doped amorphous silicon film by a dry etching method, and then performing a heat treatment after removing the mask pattern to polycrystallize the impurity-doped amorphous silicon film Another object of the present invention is to obtain a method of manufacturing a semiconductor device, which comprises the steps of:

(Problems to be solved by the conventional technology and the invention) In recent years, semiconductor integrated circuit manufacturing technology has been progressing toward further miniaturization, and as a highly precise processing technology for fine patterns,
The dry etching method is being widely used, and the reactive ion etching method is widely used for highly precise microfabrication of a polycrystalline silicon film. This method etches the film by the sputtering action of reactive ions having a high energy of several tens to several hundreds of ev. According to this method, so-called directional etching with a small pattern conversion difference is possible. . However, since this method utilizes the sputtering action of ions, it is not possible to obtain a very high etch rate ratio with the underlying silicon oxide film. In recent years, miniaturization of semiconductor integrated circuits has rapidly progressed, and the thickness of the underlying silicon oxide film in a polycrystalline silicon gate element tends to become thinner. Therefore, a processing technique capable of obtaining a high etch rate ratio between the polycrystalline silicon film and the silicon oxide film is required. Methods that can realize this include a method using an ECR plasma flow and a reactive ion etching method using a magnetron discharge. The former etches a polycrystalline silicon film with a plasma flow having low energy, and the latter enhances the plasma density by using magnetron discharge and etches in a low electric field.
In either method, since the ion bombardment is small, the selection ratio with respect to the underlying silicon oxide film can be made high.

On the other hand, the workability of the polycrystalline silicon film has a great dependence on the film quality, and depending on the film forming method and the subsequent film processing method,
We often experience different pattern shapes after dry etching. For example, the film deposited by the low pressure CVD method is doped with P atoms by the ion implantation method, and the film subjected to the heat treatment and the film subjected to the gas phase reaction of the doping gas containing the P atom are deposited, and the film subjected to the heat treatment is subjected to the magnetron discharge. When the etching is performed by the reactive ion etching method using the, an undercut occurs on the side wall of the pattern in any film.

Thus, when the two types of polycrystalline silicon films formed by the conventional method were etched by the dry etching method, a clear undercut was observed on the side wall of the pattern. As semiconductor integrated circuits require finer and more precise pattern formation technology, how to make the undercut smaller is extremely important. Therefore, the above-mentioned drawbacks of the prior art are fatal in manufacturing a semiconductor integrated circuit device.

(Means for Solving Problems) The present invention has been made in view of these problems, and an object thereof is to provide a method of manufacturing a semiconductor device having a highly accurate silicon gate structure. is there.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, a very thin silicon oxide film 2 having a film thickness of 100 Å or less is formed on a semiconductor substrate 1, and a CVD method using a mixed gas of disilane and phosphine is formed thereon.
An amorphous silicon film 3 doped with impurities is deposited to a thickness of about 3500Å. After that, a desired resist pattern 4 is formed on the amorphous silicon film 3, and the amorphous silicon film 3 is dry-etched using this as a mask (FIG. 2).
In this case, after the etching of the amorphous silicon film 3, the etch rate ratio of the amorphous silicon film to the silicon oxide film can be made sufficiently large so that the silicon oxide film remains even if the underlying silicon oxide film is overetched. Etching method is necessary. For example, if the in-wafer uniformity of the amorphous silicon film thickness is ± 10% and the in-wafer uniformity of the etchant is ± 5% when it is processed, the amorphous silicon film with respect to the silicon oxide film is An ethylate ratio (selection ratio) of about 10 or more is required. Desirably, the remaining thickness of the silicon oxide film is preferably 50 Å or more, and for this purpose, a selection ratio of 20 or more is required. As an etching method that can realize such a high selection ratio, E
Examples include CR plasma flow etching or magnetron discharge type reactive ion etching (low power region).

It is considered that the etching process in plasma etching of a polycrystalline silicon film usually proceeds along the boundaries of crystal grains. Therefore, when the crystal grain size increases due to heat treatment or the like, the amount of undercuts generated on the side wall of the pattern increases. Further, in the case of a polycrystalline silicon film containing an n-type impurity, it is activated by heat treatment, and the reaction with neutral radicals is enhanced, so that the etch rate increases and the undercut amount also increases. On the other hand, the amorphous silicon film has a very small silicon grain size, and when plasma etching is performed on the amorphous silicon film, an undercut is not formed on the side wall of the amorphous silicon film 3, as shown in FIG.
It was also observed that the state of the film surface during etching was smooth, and the surface of the underlying silicon oxide film 2 at the end of etching was also very smooth. The sample having the amorphous silicon film pattern thus formed is subjected to an ashing treatment in O ₂ plasma for a predetermined time to remove the resist pattern 4. After that, when this sample is heat-treated at 900 ° C. for 30 minutes in a nitrogen atmosphere, the amorphous silicon film 3 is crystallized and becomes a polycrystalline silicon film 3 ′ (third part).
Figure). At this time, the P atoms doped in the amorphous silicon film 3 are activated, the carrier density that controls electrical conduction is increased, and the resistivity of the polycrystalline silicon film 3'is reduced. By transforming the amorphous silicon film 3 into a polycrystalline silicon film 3'and reducing the specific resistance, this film functions as a gate electrode wiring of a silicon gate element. As a method of polycrystallizing the amorphous silicon film, an oxidization step is performed in addition to the method of annealing treatment in a nitrogen atmosphere as described above, so that the film is inevitably polycrystallized.
In some cases, the annealing process can be omitted. FIG. 4 is a cross-sectional view after an amorphous silicon pattern is formed and an oxidation process is performed. The surface of the polycrystalline silicon film pattern 3 ′ is covered with the oxide film 5.

By the method described above, the amorphous silicon film 3 was heat-treated to be polycrystallized to manufacture a device, and the electrical characteristics were measured, and good results were obtained.

As described above, according to the present invention, an amorphous silicon film doped with impurities is deposited, etched, and then heat-treated to polycrystallize the amorphous silicon film. A polycrystalline silicon gate wiring layer free from undercut can be formed.

In other words, when a silicon film doped with a high concentration of impurities is dry-etched, it is less susceptible to side etching, so that the pattern conversion difference can be reduced and highly accurate gate processing can be performed.

[Brief description of drawings]

1 to 3 show an embodiment of a method of manufacturing a semiconductor device according to the present invention, which is a cross-sectional view showing a polycrystalline silicon gate processing step, and FIG. 4 shows an amorphous silicon film. It is sectional drawing which shows an example of the method of crystallizing. 1 ... Silicon substrate 2 ... Silicon oxide film 3 ... Amorphous silicon film 3 '... Polycrystalline silicon film 4 ... Resist pattern 5 ... Oxide film

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Claims (1)

[Claims] 1. A step of depositing an impurity-doped amorphous silicon film on a substrate, a step of forming a mask pattern on the impurity-doped amorphous silicon film, and the impurity-doped amorphous film by a dry etching method. A step of selectively etching the high-quality silicon film and a step of removing the mask pattern and then performing a heat treatment to polycrystallize the impurity-doped amorphous silicon film. Manufacturing method of semiconductor device.