JPS6035536A - Manufacture of multilayer interconnection - Google Patents

Abstract

PURPOSE:To improve the adhesive property of an upper layer wiring as well as to upgrade the reliability of a multilayer interconnection member by a method wherein the top surface part of the upper layer wiring is flatened by forming the film thickness of the lower layer wiring and that of a first insulating film in an almost same thickness. CONSTITUTION:An insulating film 2 and a polycrystalline Si film 3 are formed on a semiconductor substrate 1 and a thermal treatment is selectively performed for forming a first insulating film (SiO2 film) 5. When a first-layer wiring 6 consisting of platinum silicide is formed on the exposed part of the polycrystalline Si film 3 using platinum, the top surface part thereof becomes nearly flat. A second insulating film 7 is formed, a connecting hole 8 is provided and a second- layer wiring 9 is selectively formed. As a result, as the top surface part of the second insulating film 7 has been almost flatened, the adhesive property of the wiring 9 is remarkably improved.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique that is effective when applied to multilayer wiring technology, and in particular to a technique that is effective when applied to multilayer wiring technology for semiconductor integrated circuit devices. It is something to do.

[Background technology]

Lead 1 on the top of the semiconductor substrate! In a semiconductor integrated circuit device having a multilayer wiring structure in which layers and insulating layers are alternately overlapped to form a plurality of layers, a steep step shape of the lower wiring is transmitted to the upper surface of an interlayer insulating film formed above. Ru. If an upper layer wiring such as aluminum is formed on the upper surface of this interlayer insulating film, its adhesion is extremely poor, especially at steep stepped portions, resulting in disconnection and electromigration.
This causes deterioration of the semiconductor integrated circuit device, resulting in a reduction in the reliability of the semiconductor integrated circuit device. Therefore, in a semiconductor integrated circuit device having a multilayer wiring structure, it is particularly necessary to improve the adhesion of upper layer wiring (8emicon
ductor World * 1983 + 2.

P34-P39. Especially PSG).

As a result of experiments and studies on such technology, the present inventor has found that in the current multilayer wiring technology, an insulating film that electrically separates adjacent wirings in the same conductive layer, lower layer wiring and upper layer wiring in different conductive layers. Since the insulating film and the insulating film that provide electrical isolation from the two are formed of the same insulating film, it is assumed that it will be extremely difficult to alleviate the steep step shape of the lower wiring.

[Purpose of the invention]

An object of the present invention is to provide a multilayer wiring technology that can improve reliability.

Another object of the present invention is to provide a multilayer wiring technology that can improve the absolute tif formed above the lower layer wiring and the flattening of the upper surface of the film when forming the upper layer wiring.

The above and other objects and novel features of the present invention will become clear from the description of the present invention #liF and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by forming the first insulating film for electrically isolating between the lower wirings of the same conductive layer, it is possible to alleviate the steep step shape that the lower wirings may have, and Even if the second insulating film is formed on the second insulating film, there is no steep step shape on the upper surface of the second insulating film, so the detectability of the upper layer wiring is improved and the reliability of the multilayer wiring technology can be improved. .

〔Example〕

Hereinafter, the configuration of the present invention will be explained in detail together with one embodiment.

In this embodiment, a semiconductor integrated circuit device having a two-layer helded structure will be explained.

1 to 6 are sectional views of essential parts of a semiconductor isolation circuit device in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention.

In addition, in all figures, those having the same function are marked with the same number, and repeated explanations will be omitted.

First, in order to construct a semiconductor stacked circuit device, a semiconductor substrate l of a predetermined conductivity type made of silicon single crystal is prepared.

Semiconductor elements (not shown) such as insulated gate field effect transistors and pibo-2 transistors are formed on this semiconductor substrate l! ! - form.

Then, an insulating film 2t- is formed on the main surface of the semiconductor substrate 1 in order to electrically isolate the semiconductor element from the first layer wiring formed in a later step. This insulating film 2
For example, phosphorus silicate glass (PSG) M
The thickness of the film may be approximately 8,000 to 10,000 [A1]. After this.

a 1Nth wiring electrically connecting the semiconductor elements;
Then, in order to form an insulating film that electrically isolates the first layer wiring, a polycrystalline silicon (hereinafter referred to as polySi) film 3 is formed on the insulating film 2, as shown in FIG. . This Po1y5iIII3 may be made of a material that has conductivity in advance, or a material that obtains conductivity by performing phosphorus treatment afterward, and the film thickness may be set to 3,000 mm, for example.
What is necessary is just to form it to about 4000(A).

After the process shown in FIG. 1, t'! As shown in FIG. 2, a mask 4 for heat-resistant treatment is formed on the portion of the poly 8i film 3 where the first-layer wiring is to be formed. This mask 4 uses, for example, a nitride (si, N4) film produced by plasma deposition technology, and its width, that is, the width of the first layer σ] is 1 to 3.
It may be formed to about [μn1].

After the process shown in FIG. 2, selective VC heat treatment is applied to the other exposed poly-Si film 3 using a mask 4 to electrically connect between the first layer wirings to be formed in a later process. 1st f of separation! form filA5.

For example, 1 is applied to the first insulating film 5ti and the PolySi film 3.
By applying heat treatment to about 1,000 degrees Celsius.

It is formed as a silicon dioxide (8i 0s) film, and #1 is twice as thick due to volume expansion, that is, 60
00 to 5ooo (A). After this, as shown in FIG. A mask for heat-resistant treatment, for example, a nitride mask, may be provided at the intervening portion between the film 2 and the polySi[1113].

After the step shown in FIG. 3, a conductive material, such as platinum, constituting 7 reside is formed on the entire surface in order to form a first layer of wiring having a low resistance value. This platinum is, for example, 300
It may be formed with a film thickness of about 0 to 4000 (A). Thereafter, in order to form silicide, a heat treatment is performed at about 450 [° C.] to form platinum silicide in the exposed portion of the Poly 8i film 3. Thereafter, unreacted platinum other than the platinum silicide is selectively removed using aqua regia or the like to form a first layer wiring 6 made of platinum silicide, as shown in FIG. This first
The layered wiring 6 is formed of the poly Si film 3 and the platinum to have a thickness of about 6000 to 5000 cm. That is, the upper surface portions constituted by the first layer wiring 6 and the second insulating film 5 are substantially flattened. In addition, in this example, platinum was used as the conductive material constituting the silicide, but molybdenum (MO), tungsten (W), titanium (Ti
), a conductive material constituting silicide such as palladium (Pd) may be used.

After the step shown in FIG. 4, a second insulating R film 7 is applied over the entire surface in order to electrically isolate the first layer wiring 6 from the second layer wiring formed in a later step. Form. This second
Since the base of the insulating film 7 is substantially flattened, there is no steep step shape on the upper surface thereof. The second insulation M7 is made of, for example, phosphor silicate glass,
It is sufficient to form the film to have a thickness of about 1 [μm]. and,
The second insulating film 7 above the first layer wiring 6 is selectively removed in order to electrically connect the first layer wiring 6 and the second layer wiring formed in a later step. Then, as shown in FIG. 5, connection holes 8 are formed.

These eight connection holes may be formed by, for example, isotropic etching so as not to have a steep stepped shape. In addition, the first insulating film 5, the first layer wiring 6 and the second insulating film 7
By controlling the etching rate of the first layer wiring 6 and the first insulating film 5, even if the connection hole 8 is misaligned with the mask of the first W4 wiring 6, as shown in the figure, serves as an etching stopper when forming the connection hole 8, prevents the crevice step, etc., and prevents the second etching to be formed in a later process.
The adhesion of layer wiring can be improved.

After the step shown in FIG. 5, as shown in FIG. Wiring 9 is selectively formed. Since the upper surface of the second insulating film 7 serving as the underlying layer of the second layer wiring 9 is flattened in tl, its adhesion is extremely good. As the 61° line 9 of the second layer, an aluminum film may be used, for example, and the film thickness may be formed to be about 1 [μm].

These series of 11! ! ! After completing the manufacturing process, the semiconductor waste-free circuit device of this embodiment is completed. In addition, after this,
A treatment step such as a membrane may also be applied.

〔effect〕

In a multilayer wiring member in which conductive layers and insulating layers are alternately stacked on a substrate to form a plurality of layers, the following effects can be obtained.

(1) Between adjacent lower layer wirings in the same predetermined conductive layer, those t1! By providing a first insulating film for gaseous isolation and making the thickness of the wiring and the first insulating film substantially the same, the upper surface portion formed by them can be flattened. As a result, the upper surface portion of the second insulating film provided between the lower layer wiring and the upper layer wiring of the upper conductive layer is flattened, so that the adhesion of the upper layer wiring is improved. Therefore, disconnection of upper layer wiring,
Since an increase in migration can be prevented, the reliability of the multilayer wiring member can be improved.

(2) A first isolation r1. is provided between directly adjacent lower layer wirings in the same predetermined conductive layer to electrically isolate them. Membrane metal provided,
By providing a second insulating film between the lower wiring and the upper wiring of the upper conductive layer to electrically isolate them, and controlling the etching rate of the first insulating film and the second insulating film, The first insulating film serves as an etching stopper when forming a connection hole in the WJ2 insulating film. As a result, it is possible to prevent the occurrence of a flat path step in the connection hole and improve the adhesion of the upper layer wiring. Therefore, disconnection of the upper layer wiring, increase in migration, etc. can be prevented, and the reliability of the multilayer wiring member can be improved.

As above, the invention made by the present inventor has been specifically explained based on the examples, but the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, although the above embodiments have been described with respect to a semiconductor integrated circuit device having a two-layer wiring structure, the present invention may also be applied to a semiconductor integrated circuit device having a three-layer wiring structure or a multilayer wiring structure of more than three layers.

[Application field]

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the multilayer wiring technology of semiconductor integrated circuit devices, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, and can be applied to, for example, multilayer wiring technology for grain distribution boards.

[Brief explanation of the drawing]

1 to 6 are sectional views of essential parts of a semiconductor integrated circuit device in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention. In the figure, l... - semiconductor substrate, 2... insulating film, 3...
polySi film, 4... mask, 5... first insulating film, 6... first layer wiring, 7... second insulating film, 8...
... Connection hole, 9... Second layer wiring. Fig. 1r4 Fig. 2 Fig. 3 Fig. 4 m (rh

Claims (1)

[Claims] 1. A step of forming a conductive layer on the substrate, and selectively forming the conductive layer in a region other than the region where the first layer wiring is to be formed as a first insulating film in a subsequent step. A step of forming a conductive material constituting silicate on the entire surface, and forming a first/? a step of selectively removing the conductive material in a region other than the region where the v-th wiring is to be formed to form a silicided first R-th wiring; and a step of forming a second insulating film on the entire surface. , selectively removing the second insulating film in a predetermined soil portion of the first layer wiring to form a connection hole, and electrically connecting to the first layer wiring through the connection hole. A method for manufacturing a multilayer interconnection comprising the step of selectively forming a second layer interconnection above the second insulating film. 2. The method for manufacturing a multilayer wiring according to claim 1, wherein the conductive layer in the step of forming the conductive layer is a polycrystalline silicon film.