JPH0529483A - Semiconductor integrated device - Google Patents

Abstract

PURPOSE:To eliminate complexity from wiring on the surface of a semiconductor substrate by forming the wiring on the rear surface of the substrate via through holes formed through the semiconductor substrate so as to connect the front surface with the rear surface of the substrate. CONSTITUTION:In order to connect wiring on the front surface of a semiconductor substrate 13 with wiring on the rear surface of the substrate 13, through holes 11 are formed from the rear surface side of the substrate 13 by etching the substrate 13 with an Si etching solution of, for example, KOH, a mixture of hydrofluoric acid and nitric acid, etc. For insulating the Si substrate 12 from the rear-surface wiring 2, an insulating film 4 is formed by the CVD method, etc. Then, in order to connect wiring and a device on the front surface of the substrate 13 with the wiring 2 on the rear surface of the substrate 13, contacts 14 and 15 are formed and an Al film 2 which becomes the wiring on the rear surface is patterned by vapor deposition or sputtering. In addition, in order to protect the wiring and device on the front surface and wiring on the rear surface from moisture and metallic contamination, protective films 9 and 10 are respectively formed on the front and rear surfaces of the substrate 13. Therefore, direct connecting sections 14 and 15 are respectively formed between the front surface wiring and rear surface wiring and between the device and rear surface wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device in which a large number of electronic elements such as Tr, C and R are provided on one surface of a semiconductor substrate, and more particularly to a wiring structure of the semiconductor integrated device.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated device, a large number of electronic devices are formed on one surface of a semiconductor substrate, and wiring is performed between electronic devices on the same surface of the semiconductor substrate. If it becomes complicated, form an insulating film on one wire and then form a second wire on it.
It had a multilayer wiring structure.

As described above, in the conventional wiring structure, as the number of elements in the semiconductor integrated device increases and the number of wirings formed on the surface also increases, in order to avoid the complexity of the wirings, the wirings are formed on the wirings. Second wiring or third
Wiring was done, but such multilayer wiring,
A sharp step is formed on the surface of the semiconductor, and the step causes problems such as difficulty in forming an insulating film and disconnection of wiring.

[0004]

Therefore, in this type of semiconductor integrated device, wiring of a large number of electronic elements provided on one surface of a semiconductor substrate with each other and with external terminals is complicated, and sometimes the mutual wiring is sometimes difficult. There is a defect that a large parasitic capacitance is generated between them, and this solution has been demanded.

[0005]

In order to solve the above-mentioned problems, the present invention provides wiring on the back surface through a through hole formed so as to extend between the front surface and the back surface of a semiconductor substrate so as to connect the front surface and the back surface. Wiring is possible on both sides, and the wiring structure on both sides avoids the complexity of the wiring on one surface of the semiconductor substrate.

That is, the semiconductor integrated device according to the present invention includes a semiconductor electronic device group formed on one surface of a semiconductor substrate, wiring formed on the front surface for connecting the semiconductor electronic device group, and a front surface and a back surface. It comprises a through hole formed in the semiconductor substrate so as to pass through both sides for connection, and a wiring on the back surface connected to the wiring on the front surface of the semiconductor substrate through the through hole.

In the semiconductor integrated device of the present invention having the above-described structure, the wiring in the integrated circuit device can be provided not only on the front surface but also on the back surface, so that the step of the insulating layer on the front surface becomes gentle and the wiring It will increase reliability. Further, since the power supply line, the GND line, etc., which have taken a particularly large area on the front surface wiring, can be routed to the back surface wiring, the wiring area can be reduced and the chip area can be reduced. Further, by rotating the wiring on the front surface to the back surface, there is an advantage that the space between the element and the wiring is expanded, and the parasitic capacitance generated between the both can be reduced.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention shown in the drawings will be described below. FIG. 1 shows a sectional view of a semiconductor integrated device using the present invention. In FIG. 1, the N ⁺ diffusion layers 5 and 6 and the MOSTr are formed on one surface of the Si substrate 13 by a conventionally known method.
7, diffusion resistance layer 8, diffusion layer 6 for taking the potential of the substrate, Nwe
The 11 diffusion layer 12 is formed. In order to electrically connect these elements, a contact hole is formed in the insulating film 3 and the surface wiring layer 1 is formed thereon to connect the elements.

In the semiconductor integrated device of the present invention, the through-hole 11 is formed from the back surface of the substrate 13 in order to connect the wiring on the back surface to the wiring on the front surface. This through hole 11 is
For example, the Si substrate is etched from the back surface with a Si etching solution such as KOH or hydrofluoric nitric acid. Insulating film 4 is formed by a method such as CVD in order to maintain insulation between backside wiring 2 and Si substrate 13 in which through hole 11 is formed.
In order to connect the wiring on the front surface and the device to the wiring on the back surface, contacts 14 and 15 are formed and wiring is formed on the back surface.
Is vapor-deposited or sputtered and patterned by photolithography technique.

Further, protective films 9 and 10 are formed on the front surface and the back surface, respectively, in order to protect the wiring on the front surface, the device, and the wiring on the back surface from moisture and metal contamination. With the wiring structure as described above, for example, the direct connection portion 14 between the front surface wiring and the back surface wiring or the direct connection 15 between the device and the back surface wiring can be performed.

Not only the through holes can be formed from the back surface, but also holes can be formed from the front surface side by a method similar to the TRENCH technique, and the same effect can be obtained with the same structure as the through holes.

As described above, the semiconductor integrated device according to the present invention is a semiconductor integrated device in which electronic devices such as MOSTr, Bip-Tr, resistors and capacitors are formed on one surface of a semiconductor substrate such as Si or GaAs substrate. Wiring that connects the elements is provided on both the front and back surfaces of the semiconductor substrate, and wiring on the back surface and wiring formed on the front surface, or to connect to the device, wiring from the back surface to the front surface, device To form a through hole leading to the
If necessary, the wiring provided on the back surface may be wiring (not patterned) on the entire back surface.

[0013]

According to the semiconductor integrated circuit of the present invention having the above-described structure, the wiring in the integrated circuit device is performed not only on the front surface but also on the back surface, so that the step on the surface becomes gentle and the reliability of the wiring is improved. Since the power supply line, the GND line, etc. can be routed to the backside wiring, the wiring area can be reduced, the chip area can be reduced, and the frontside wiring can be routed to the backside. This has the advantage that the space between the wirings is widened and the parasitic capacitance conventionally generated between the two can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor integrated circuit according to the present invention.

[Explanation of symbols]

1 Front Wiring (Al) 2 Back Wiring (Al) 3 Front Insulating Film (SiO ₂ ) 4 Back Insulating Film (SiO ₂ ) 5 N ⁺ Diffusion Layer (1) 6 N ⁺ Diffusion Layer (2) 7 MOSTr 8 P ⁺ Diffusion Layer 9 Surface protective film 10 Backside protective film 11 Through hole 12 Nwell 13 P substrate 14 Surface wiring and backside wiring contact 15 Device and backside wiring contact

Claims (3)

[Claims] 1. A semiconductor integrated device in which a plurality of electronic elements are formed on one surface of a semiconductor substrate, wherein wiring connecting the electronic elements is provided on both one surface and the back surface of the semiconductor substrate. Integrated device. 2. The semiconductor integrated device according to claim 1, wherein a wiring provided on the back surface of the semiconductor substrate is connected to a wiring formed on the front surface or an electronic element, so that a through hole communicating from the back surface side to the front surface side is formed. Then, the semiconductor integrated device in which the wiring on the back surface and the wiring on the front surface or the electronic element are tangentially connected to each other through the through hole. 3. The semiconductor integrated device according to claim 1, wherein wiring is provided on the entire back surface of the semiconductor substrate.