JP2019004104A - Through electrode substrate and method of manufacturing the same - Google Patents

Abstract

To provide a through electrode substrate capable of forming a passive element while suppressing influences by a substrate without increasing the number of steps.SOLUTION: A through electrode substrate 100 includes: a conductive part 113 provided on a first surface of a semiconductor substrate 110 and having conductivity; a through-hole 115 provided on the semiconductor substrate 110; a through electrode 120 provided in the through-hole 115; an insulating layer 130 provided so as to cover the first surface and a second surface of the semiconductor substrate 110 and a side wall of the through-hole 115; and wiring 140 provided at the first surface side of the semiconductor substrate 110 and on the insulating layer 130. In the through electrode substrate 100, a plurality of wirings 140 are arranged, and may have at least any one of a portion electrically connected with the conductive part 113, a portion opposed to the conductive part 113, and a portion electrically connected with the through electrode 120.SELECTED DRAWING: Figure 2

Description

  The present disclosure relates to a through electrode substrate and a method for manufacturing the through electrode substrate.

  A three-dimensional mounting technique in which high-frequency elements including semiconductor elements including integrated circuits and RF (Radio Frequency) elements are vertically stacked is widely used. In this technique, an interposer substrate (sometimes referred to as a wiring substrate or a through electrode substrate) on which a through electrode is formed is used (see Patent Document 1). Thereby, the semiconductor element and the RF element are electrically connected on both sides of the substrate.

  On the other hand, in the case of the above connection, since all elements need to be mounted, the size of the through electrode substrate tends to increase. For this reason, technical development is proceeding to form passive elements (inductors, capacitive elements, resistive elements, etc.) used as RF elements on the through electrode substrate. For example, Patent Document 2 discloses a technique for forming a passive element using a glass substrate.

Japanese Patent No. 4634735 JP-T-2006-518702

  However, when a glass substrate is used as in Patent Document 2, the type or size of passive elements that can be formed may be limited because warpage of the substrate occurs in the manufacturing process of the through electrode substrate. In the case of a glass substrate, when the wiring is provided in the same layer, the passive element may become large due to the problem of wiring processing accuracy. In addition, in order to form a wiring serving as a member of the passive element, it is necessary to newly provide a conductive layer or an insulating layer, which may increase the number of processes.

  In view of such problems, an object of the embodiment of the present disclosure is to provide a through electrode substrate capable of forming a passive element while suppressing the influence of the substrate without increasing the number of steps.

  According to an embodiment of the present disclosure, a semiconductor substrate having a first surface and a second surface opposite to the first surface, a conductive portion provided on the first surface of the semiconductor substrate and having a predetermined resistivity, A through hole provided in the semiconductor substrate; a through electrode provided in the through hole; an insulating layer provided to cover the first and second surfaces of the semiconductor substrate and the side wall of the through hole; There is provided a through electrode substrate including a wiring on one surface side and provided on an insulating layer.

  In the through electrode substrate, the wiring may include a plurality of wirings and at least one of a part electrically connected to the conductive part, a part facing the conductive part, and a part electrically connected to the through electrode. .

  In the through electrode substrate, the semiconductor substrate may be a silicon substrate, and the insulating layer may be a silicon oxide film.

  In the through electrode substrate, the resistivity of the conductive portion may be 0.1 Ω · cm or more and 10000 Ω · cm or less.

  In the through electrode substrate, the conductive portion may include a group III or group V element.

  The through electrode substrate may further include a second conductive portion that is provided so as to cover the conductive portion and has a polarity different from that of the conductive portion.

  The penetration electrode substrate may further include a third conductive portion provided on the second surface of the semiconductor substrate and having the same polarity as the second conductive portion.

  In the through electrode substrate, the wiring includes at least one of a first wiring, a second wiring, and a third wiring, the inductor in which the first wiring is arranged in a loop, a part of the conductive part, and a part of the conductive part And at least one of a passive element including a capacitive element having a second wiring disposed opposite to the first wiring element and a resistive element having another part of the conductive portion electrically connected to the third wiring.

  According to an embodiment of the present disclosure, a semiconductor substrate having a first surface and a second surface opposite to the first surface is used, and a conductive portion is selectively formed on a part of the first surface of the semiconductor substrate. A through hole is formed in the semiconductor substrate, an insulating layer is formed on the first and second surfaces of the semiconductor substrate and the side wall of the through hole, a through electrode is formed in the through hole of the semiconductor substrate, and a wiring is formed on the insulating layer There is provided a method of manufacturing a through electrode substrate.

  In the method for manufacturing the through electrode substrate, the semiconductor substrate may be a silicon substrate, and the insulating layer may be a silicon oxide film.

  In the method for manufacturing the through electrode substrate, the insulating layer may be formed by a thermal oxidation method.

  In the method for manufacturing the through electrode substrate, the conductive portion may be formed by an ion implantation method.

  In the method for manufacturing the through electrode substrate, the conductive portion may include a group III or group V element.

  According to an embodiment of the present disclosure, it is possible to provide a through electrode substrate capable of forming a passive element without increasing the number of steps and without being affected by the substrate.

It is a top view explaining a penetration electrode substrate concerning one embodiment of this indication. It is a sectional view explaining a penetration electrode substrate concerning one embodiment of this indication. It is a circuit diagram explaining a penetration electrode substrate concerning one embodiment of this indication. It is a top view and a sectional view explaining a manufacturing method of a penetration electrode substrate concerning one embodiment of this indication. It is a top view and a sectional view explaining a manufacturing method of a penetration electrode substrate concerning one embodiment of this indication. It is a top view and a sectional view explaining a manufacturing method of a penetration electrode substrate concerning one embodiment of this indication. It is a top view and a sectional view explaining a manufacturing method of a penetration electrode substrate concerning one embodiment of this indication. It is a top view and a sectional view explaining a manufacturing method of a penetration electrode substrate concerning one embodiment of this indication. It is a top view and a sectional view explaining a manufacturing method of a penetration electrode substrate concerning one embodiment of this indication. It is a top view and a sectional view explaining a manufacturing method of a penetration electrode substrate concerning one embodiment of this indication. It is a top view explaining a penetration electrode substrate concerning one embodiment of this indication. It is a sectional view explaining a penetration electrode substrate concerning one embodiment of this indication. It is a top view explaining a penetration electrode substrate concerning one embodiment of this indication. It is a sectional view explaining a penetration electrode substrate concerning one embodiment of this indication. It is a top view explaining a penetration electrode substrate concerning one embodiment of this indication. It is a sectional view explaining a penetration electrode substrate concerning one embodiment of this indication. It is a top view explaining a penetration electrode substrate concerning one embodiment of this indication. It is a sectional view explaining a penetration electrode substrate concerning one embodiment of this indication. It is a sectional view explaining a semiconductor device containing a circuit element concerning one embodiment of this indication. It is a perspective view explaining the electric equipment containing the semiconductor device concerning one embodiment of this indication. It is a sectional view explaining a penetration electrode substrate concerning one embodiment of this indication.

  Hereinafter, a through electrode substrate, a passive element, and the like according to each embodiment of the present disclosure will be described in detail with reference to the drawings. In addition, each embodiment shown below is an example of embodiment of this indication, Comprising: This indication is limited to these embodiment and is not interpreted. Note that in the drawings referred to in the present embodiment, the same portions or portions having similar functions are denoted by the same reference symbols or similar reference symbols (symbols in which numbers such as -1, -2 etc. are added after numbers), The repeated description may be omitted. In addition, the dimensional ratio in the drawing may be different from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

<First Embodiment>
(1-1. Configuration of the through electrode substrate)
FIG. 1 shows a top view of the through electrode substrate 100. FIG. 2 shows a cross-sectional view of the through electrode substrate 100 between A1 and A2. As shown in FIGS. 1 and 2, the through electrode substrate 100 includes a substrate 110, a conductive portion 113, a through electrode 120, an insulating layer 130, a wiring 140 and a wiring 240.

  The substrate 110 has a first surface 110A and a second surface 110B opposite to the first surface 110B. The substrate 110 is provided with a through hole 115. As shown in FIG. 1, the through-hole 115 when viewed from above has a circular shape or a rectangular shape.

  A semiconductor material is used for the substrate 110. For example, the substrate 110 is a silicon substrate, more specifically, a P-type silicon substrate. The thickness of the substrate 110 may be set as appropriate in the range of 100 μm to 700 μm. For example, 400 μm is used as the thickness of the substrate 110.

  Note that the material of the substrate 110 is not limited to the above, and a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, a gallium arsenide (GaAs) substrate, or a stack of these substrates is used as the substrate 110. May be.

The conductive portion 113 is provided on or inside the first surface 110 </ b> A of the substrate 110. In addition, although the electroconductive part 113 contains the electroconductive part 113-1 and the electroconductive part 113-2, when it is not necessary to distinguish, it demonstrates as the electroconductive part 113. FIG. The conductive portion 113 mainly contains a Group III or Group V metal. In the case where the substrate 110 is a P-type silicon substrate, the conductive portion 113 contains phosphorus (P) or arsenic (As). The conductive portion 113 has a predetermined resistivity. The predetermined resistivity is controlled by the amount of phosphorus (P) or arsenic (As) contained in the conductive portion 113. At this time, phosphorus (P) or arsenic (As) is included in a range of 1 × 10 ¹⁶ atoms / cm ^{3 to} 1 × 10 ²¹ atoms / cm ³ . The resistivity of the conductive portion 113 is preferably 0.1 Ω · cm to 10000 Ω · cm.

  The through electrode 120 is provided in the through hole 115. A low resistance material is used for the through electrode 120. For example, copper (Cu) is used for the through electrode 120. Note that the material is not limited to copper (Cu), and a material containing gold (Au), silver (Ag), nickel (Ni), or tin (Sn) may be used. As shown in FIG. 2, when the through electrode 120 is viewed from a cross section, the electrode width of the through electrode 120 is appropriately set in a range of 5 μm or more and less than 100 μm.

  The insulating layer 130 is provided so as to cover the first surface 110 </ b> A, the second surface 110 </ b> B, and the side wall of the through electrode 120 of the substrate 110. In this example, a silicon oxide film is used for the insulating layer 130. Note that the insulating layer 130 may be a single layer or a stacked layer of an inorganic insulating material such as a silicon nitride film or an aluminum oxide film in addition to a silicon oxide film. For the insulating layer 130, an organic insulating material such as an acrylic resin or an epoxy resin may be used. The thickness of the insulating layer 130 is appropriately set in the range of 50 nm to 10 μm, preferably 100 nm to 5 μm.

  The wiring 140 is provided on the insulating layer 130 on the first surface 110 </ b> A side of the substrate 110. Note that the wiring 140 includes the wiring 140-1, the wiring 140-2, the wiring 140-3, and the wiring 140-4. Copper (Cu) is used for the wiring 140. Note that the wiring 140 is not limited to copper (Cu), and the same metal material as the through electrode 120 may be used, or aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), or the like. The material may be used.

  The wiring 240 is provided on the insulating layer 130 on the second surface 110 </ b> B side of the substrate 110. A material similar to that of the wiring 140 is used for the wiring 240.

(1-2. Configuration of passive element)
As shown in FIGS. 1 and 2, the through electrode substrate 100 includes an inductor 101, a capacitive element 103, and a resistive element 105. The inductor 101, the capacitive element 103, and the resistance element 105 function as passive elements. In the through electrode substrate 100, the wiring 140 is used as a member that forms a passive element together with the insulating layer 130 and the conductive portion 113. Note that the inductor 101, the capacitor 103, and the resistor 105 are not necessarily all provided, and may be arranged according to functions.

  For example, the wiring 140-1 of the wiring 140 is used for the inductor 101. The wiring 140-1 is arranged in a loop shape (more specifically, a spiral shape).

  In addition, the capacitor 103 includes the insulating layer 130 as a dielectric, the wiring 140-2 of the wiring 140 as one electrode of the capacitor 103, and the conductive portion 113-1 of the conductive portion 113 is the other of the capacitor 103. Used as an electrode. The wiring 140-2 and the conductive portion 113-1 are arranged to face each other with the insulating layer 130 interposed therebetween. The conductive portion 113-1 is connected to the wiring 140-4.

  The resistance element 105 includes the wiring 140-3 and the conductive portion 113-2. The wiring 140-3 and the conductive portion 113-2 have a portion that is electrically connected.

  Note that the wiring 140-1 and the wiring 140-3 have a portion connected to the through electrode 120. Further, the through electrode 120 is connected to the wiring 240 on the second surface 110 </ b> B side of the substrate 110. Thereby, the inductor 101 and the resistance element 105 are electrically connected. In addition, the wiring 140-1 and the wiring 140-2 have a portion that is electrically connected. Thereby, the inductor 101 and the capacitive element 103 are electrically connected.

  FIG. 3 is a circuit diagram of the through electrode substrate 100 including the passive elements shown in FIGS. 1 and 2. In this example, the inductor 101, the capacitive element 103, and the resistance element 105 are arranged in series in the through electrode substrate 100 based on the connection relationship described above. At this time, the resistance element 105 is connected to the terminal 107. In addition, the capacitor 103 is connected to the terminal 109. The terminal 107 and the terminal 109 may be disposed on the insulating layer 130 similarly to the wiring 140. At this time, the terminal 109 and the wiring 140-4 may be connected. The through electrode substrate 100 can function as a bandpass filter in the through electrode substrate 100 by using a combination of the inductor 101, the capacitor 103, and the resistor 105.

(1-3. Manufacturing method of through electrode substrate)
Next, a method for manufacturing the through electrode substrate 100 shown in FIGS. 1 and 2 will be described with reference to FIGS.

  First, as shown in the top view of FIG. 4A and the cross-sectional view of FIG. 4B, a substrate 110 having a first surface 110A and a second surface 110B opposite to the first surface 110A is used. For example, a semiconductor substrate (specifically, a P-type silicon substrate) is used for the substrate 110. In this example, the thickness of the substrate 110 is appropriately set in the range of 100 μm to 700 μm.

Next, as shown in a top view in FIG. 5A and a cross-sectional view in FIG. 5B, a resist film 111 is formed on the first surface 110A of the substrate 110. The resist film 111 is formed by a photolithography method. Ions 112 are added to the opened region 114 by an ion implantation method. As ion implantation conditions, processing is performed with an acceleration voltage of 10 keV to 300 keV and an ion implantation amount of 1 × 10 ¹² atoms / cm ^{2 to} 1 × 10 ¹⁶ atoms / cm ² . In this example, the same amount of ions is added to the region 114-1 and the region 114-2 of the region 114. In addition, it is desirable to heat after ion addition. Thereby, a substitution reaction occurs between the silicon atoms in the silicon substrate and the added ions, and the added ions diffuse in the silicon substrate, so that the resistivity of a part of the silicon substrate can be lowered. Accordingly, the conductive portion 113 is selectively formed on a part of the substrate 110. After the ions 112 are added, the resist film 111 is removed.

Next, as illustrated in a top view in FIG. 6A and a cross-sectional view in FIG. 6B, a through hole 115 is formed after a resist film 116 is formed on the substrate 110 by a photolithography method. The through hole 115 is formed by a dry etching method such as a reactive ion etching method or a deep reactive ion etching method. As a gas for etching, sulfur hexafluoride (SF ₆ ), tetrafluoromethane (CF ₄ ), hydrogen trifluoride methane (CHF ₃ ), hydrogen (H ₂ ), or argon (Ar) is used in combination. After the through hole 115 is formed, the resist film 116 is removed.

  Next, as shown in the top view of FIG. 7A and the cross-sectional view of FIG. 7B, the insulating layer 130 covers the first surface 110A and the second surface 110B of the substrate 110 and the sidewalls of the through holes 115. Form. The thickness of the insulating layer 130 is set in the range of 50 nm to 10 μm, preferably 100 nm to 5 μm. The insulating layer 130 is formed by a thermal oxidation method when a silicon substrate is used as the substrate 110. A wet thermal oxidation method is used as the thermal oxidation method at this time. By using the wet thermal oxidation method, the oxidation rate of the silicon substrate is increased. In addition to the wet thermal oxidation method, any one of the hydrochloric acid oxidation method, the dry thermal oxidation method, and the pyrogenic thermal oxidation method may be used as the thermal oxidation method of the silicon substrate.

  Next, as shown in the top view of FIG. 8A and the cross-sectional view of FIG. 8B, the through electrode 120 is formed in the through hole 115. The through electrode 120 includes nickel (Ni), gold (Au), silver (Ag), tin (Sn) and the like in addition to copper (Cu). The through electrode 120 may be formed by an electrolytic plating method or an electroless plating method. For example, when the through electrode 120 is formed using copper (Cu), a copper (Cu) thin film is formed by a sputtering method. Next, a copper (Cu) film is formed by electrolytic plating using the copper (Cu) thin film as a seed layer. Finally, the first surface 110A and the second surface 110B of the substrate 110 are formed by chemical mechanical polishing (CMP) on the copper (Cu) film formed on the first surface 110A and the second surface 110B of the substrate 110. By removing the upper copper (Cu), the through electrode 120 is filled and formed.

  Next, as shown in a top view in FIG. 9A and a cross-sectional view in FIG. 9B, an opening 135 is formed over the conductive portion 113 in the insulating layer 130. The opening 135 is formed by using a photolithography method, an etching method, or the like.

  Next, as shown in the top view of FIG. 10A and the cross-sectional view of FIG. 10B, the wiring 140 is formed on the top surface of the insulating layer 130 on the first surface 110A side of the substrate 110 and the opening 135. . Of the wiring 140, the wiring 140-1 and the wiring 140-3 are formed so as to be in contact with the through electrode 120. Further, the wiring 140-3 is formed so as to be connected to the conductive portion 113-2 in the conductive portion 113. In addition, the wiring 140-1 is formed in a spiral shape in this example. Note that the wiring 140-1 is not limited to a spiral shape, and may be a loop shape. Further, the wiring 140-2 is formed so as to face the conductive portion 113-1 in the conductive portion 113. In this example, the wiring 140 is formed by a plating method.

  For example, when the wiring 140 is formed by a plating method, the following method is used. First, a copper (Cu) thin film is formed on the top surfaces of the through electrode 120, the opening 135, and the insulating layer 130 by electroless plating. Next, a resist film is formed on the copper thin film so as to overlap the insulating layer 130. Next, a resist pattern is formed by photolithography. Next, the wiring 140 is formed by electrolytic plating. Finally, the resist pattern and the copper thin film under the resist pattern are removed. The above method is called a semi-additive method. After forming the wiring 140, the wiring 240 is formed on the second surface 110B side of the substrate 110. The wiring 240 is formed by the same method as the wiring 140. With the above method, the through electrode substrate 100 shown in FIGS. 1 and 2 is manufactured.

  The through electrode substrate manufactured by the above method is used as a conductive portion by controlling the resistance of a part of the substrate. Thereby, it is not necessary to newly provide a conductive layer and an insulating layer. That is, the through electrode substrate can be manufactured without increasing the number of steps. Further, since the passive element member is formed together with the processing of the through electrode substrate, it is not necessary to mount the passive element on the through electrode substrate. That is, it is not necessary to provide a mounting space, and the through electrode substrate can be made small. Furthermore, by manufacturing a through electrode substrate using a silicon substrate, the influence of the warpage of the substrate during the process is suppressed compared to a glass substrate, and it is easier to finely process than a glass substrate (that is, the line width is reduced, The opening can be made smaller.) Accordingly, it is possible to form a small passive element on the through electrode substrate while suppressing the influence of the substrate in manufacturing the through electrode substrate.

Second Embodiment
Next, through electrode substrates having different structures will be described. In addition, about the structure, material, and method which were shown in 1st Embodiment, the description is used.

  FIG. 11 shows a top view of the through electrode substrate 100-1. FIG. 12 is a cross-sectional view taken along the line A1-A2 of the through electrode substrate 100-1. As shown in FIGS. 11 and 12, the through electrode substrate 100-1 includes a conductive portion 117 in addition to the substrate 110, the conductive portion 113, the through electrode 120, the insulating layer 130, the wiring 140 and the wiring 240.

  The conductive portion 117 is provided so as to cover the conductive portion 113. Of the conductive portion 117, the conductive portion 117-1 covers the conductive portion 113-1. The conductive portion 117-2 covers the conductive portion 113-2. The conductive portion 117 functions as an element isolation layer of the conductive portion 113 used as a part of the passive element. The conductive portion 117 has a polarity different from that of the conductive portion 113. In this example, the substrate 110 is P-type. Further, the conductive portion 113 includes a group III atom such as boron (that is, the conductive portion 113 has a P type), and the conductive portion 117 includes a group V atom such as phosphorus or arsenic (that is, the conductive portion 117 is N type).

  As shown in FIGS. 11 and 12, by providing the conductive portion 117, element isolation is ensured. For this reason, each passive element can function appropriately in the through electrode substrate even when the passive elements become smaller and the passive elements are arranged close to each other.

<Third Embodiment>
Next, through electrode substrates having different structures will be described. In addition, about the structure, material, and method shown in 1st Embodiment and 2nd Embodiment, the description is used.

  FIG. 13 shows a top view of the through electrode substrate 100-2. FIG. 14 is a cross-sectional view taken along the line A1-A2 of the through electrode substrate 100-2. As shown in FIGS. 13 and 14, the through electrode substrate 100 includes a conductive portion 119 in addition to the substrate 110, the conductive portion 113, the through electrode 120, the insulating layer 130, the wiring 140, the wiring 240, and the conductive portion 117. .

  The conductive part 119 is provided on the second surface 110 </ b> B of the substrate 110. The conductive portion 119 includes the same type of material (Group III or Group V metal) as the conductive portion 117 and has the same polarity as the conductive portion 117. In this example, the substrate 110 functions as a P-type, the conductive portion 113 as a P-type, the conductive portion 117 as an N-type, and the conductive portion 119 as an N-type conductive portion. The resistivity of the conductive portion 119 may be controlled to the same extent as that of the conductive portion 117, but is not limited thereto. The resistivity of the conductive portion 119 may be different from the resistivity of the conductive portion 117. At this time, the resistance element can use the conductive portion 113 on the first surface 110A side, and the capacitive element can use the conductive portion 119 on the second surface 110B side. Further, by providing the conductive portion 119, the through-electrode substrate 100-2 can be provided with passive elements at a higher density.

<Fourth embodiment>
Next, through electrode substrates having different structures will be described. In addition, about the structure, material, and method shown in 1st-3rd embodiment, the description is used.

  FIG. 15 shows a top view of the through electrode substrate 100-3. FIG. 16 is a cross-sectional view taken along the line A1-A2 of the through electrode substrate 100-3. As shown in FIGS. 15 and 16, the through electrode substrate 100-3 includes a substrate 110, a conductive portion 113, a through electrode 121, an insulating layer 130 and a wiring 140.

  In the through electrode substrate 100-3, the through electrode 121 is provided not only on the through hole 115 but also on the first surface 110A side and the second surface 110B side of the substrate 110. At this time, the through electrode 121 is formed by a conformal plating method. Portions of the through electrode 121 provided on the first surface 110 </ b> A side and the second surface 110 </ b> B side of the substrate 110 can have the same function as the wiring 140. Further, the through electrode 121 and the wiring 140 may be formed at the same time. Thereby, the number of processes for forming the passive element on the through electrode substrate can be further reduced.

<Fifth Embodiment>
Next, through electrode substrates having different structures will be described. In addition, about the structure, material, and method shown in 1st-4th embodiment, the description is used.

  FIG. 17 shows a top view of the through electrode substrate 100-4. FIG. 18 is a cross-sectional view taken along the line A1-A2 of the through electrode substrate 100-4. As shown in FIGS. 17 and 18, the through electrode substrate 100-4 includes a substrate 110-4, a through electrode 120, an insulating layer 130, and a wiring 140.

  The through electrode substrate 100-4 includes a substrate 110-4 having a predetermined resistivity without providing the conductive portion 113. Specifically, a silicon substrate to which ions are added so that the resistivity is 0.1 Ω · cm or more and 10000 Ω · cm or less when the silicon substrate is manufactured is used. At this time, the substrate 110-4 is used as a part of the passive element. The through electrode substrate 100-4 can further reduce the number of steps in forming a passive element on the through electrode substrate because the conductive portion 113 does not need to be provided.

<Sixth Embodiment>
In the present embodiment, a semiconductor device including the through electrode substrate described in the first to fifth embodiments will be described.

  FIG. 19 is a cross-sectional view of the semiconductor device 500. As shown in FIG. 19, the semiconductor device 500 includes a semiconductor element 600 and a semiconductor element 620 that are formed into a chip including a transistor, a through electrode substrate 100, and a package substrate 800. The semiconductor element 600 and the semiconductor element 620 have a function as a central processing unit (CPU) or a function as a storage device. The through electrode substrate 100 has a function of relaying between the semiconductor element 600 and the semiconductor element 620 and the package substrate 800. The semiconductor element 600 and the semiconductor element 620 and the through electrode substrate 100 are electrically connected using gold bumps 690 or the like. The through electrode substrate 100 and the package substrate 800 are connected using solder bumps 750 containing tin, silver, or the like. Further, the gap between the through electrode substrate 100 and the package substrate 800 may be sealed by being filled with an underfill resin. As described above, the through electrode substrate 100 includes passive elements such as the inductor 101, the capacitive element 103, and the resistive element 105. Therefore, in the semiconductor device 500, the passive element provided on the through electrode substrate 100 may be used for noise elimination or may be used for a signal filter.

<Seventh embodiment>
In this embodiment, an example in which the semiconductor device 500 described in the sixth embodiment is applied to an electric device will be described.

  FIG. 20 is a diagram illustrating an electrical device. The semiconductor device 500 including the semiconductor element 600, the semiconductor element 620, and the passive element includes, for example, a portable terminal (a mobile phone, a smartphone, a notebook personal computer, a game machine, etc.), an information processing device (a desktop personal computer, a server, a car, etc.). Navigation, etc.), household electric appliances (microwave oven, air conditioner, washing machine, refrigerator), automobiles and other various electric appliances. FIG. 20A illustrates a smartphone 4000. FIG. 20B illustrates a portable game machine 5000. FIG. 20C illustrates a laptop personal computer 6000.

  In these electric appliances, the semiconductor device 500 including the semiconductor element 600, the semiconductor element 620, and the passive element is controlled by a noise filter, a signal filter, a CPU that executes various application programs to realize various functions, and the like. Functions.

(Modification 1)
In the first embodiment of the present disclosure, the conductive portion 113-1 and the conductive portion 113-2 have been described as having the same resistivity by ion addition, but the present disclosure is not limited thereto. Different amounts of ions may be added to the conductive portion 113-1 and the conductive portion 113-2. Thereby, it has an appropriate resistivity for every passive element, and can make a passive element function in an optimal state.

(Modification 2)
In the first embodiment of the present disclosure, the inductor 101, the capacitor element 103, and the resistor element 105 have been described as being arranged in series, but it is not always necessary to be connected in series. For example, the inductor 101, the capacitor element 103, and the resistor element 105 may be provided in parallel or may be provided in a branched manner, and may be appropriately changed according to circuit design.

(Modification 3)
In the first embodiment of the present disclosure, the insulating layer 130 has been described as being formed by a thermal oxidation method, but is not limited thereto. For example, a CVD (Chemical Vapor Deposition) method, a sputtering method, a vapor deposition method, or an immersion method may be used.

(Modification 4)
In 1st Embodiment of this indication, although the wiring 140 showed the example formed by the plating method, it is not limited to this. The wiring 140 may be formed by a CVD method, a sputtering method, a vapor deposition method, or a printing method. At this time, the wiring 140 may be processed by a photolithography method and an etching method. For the wiring 140, a material such as aluminum, tungsten, titanium, or molybdenum may be used.

(Modification 5)
In 1st Embodiment of this indication, although the example which has the shape (what is called a parallel flat plate) in which the electroconductive part 113-1 and the wiring 140-2 were located in parallel in the capacitive element 103 was shown, it is not limited to this. FIG. 21 is a cross-sectional view of the through electrode substrate 100-5. The through electrode substrate 100-5 includes a substrate 110, a conductive portion 113, a through electrode 120, an insulating layer 130-5, a wiring 140, and a wiring 240. The through electrode substrate 100-5 includes a capacitive element 103-5. The capacitive element 103-5 includes a recess 118 in the substrate 110. At this time, the insulating layer 130-5 is arranged according to the shape of the recess 118, and the wiring 140-2 is also provided in the recess 118. Accordingly, the capacitor 103-5 can have a trench shape. Since the capacitor 103-5 has the above shape, the amount of stored charge can be increased.

  DESCRIPTION OF SYMBOLS 100 ... Through-electrode board | substrate, 101 ... Inductor, 103 ... Capacitance element, 105 ... Resistance element, 107 ... Terminal, 109 ... Terminal, 110 ... Substrate, 111 ... Resist film, 112... Ion, 113... Conductive portion, 114... Region, 115... Through-hole, 116. ... Conductive part, 120 ... Through electrode, 121 ... Through electrode, 130 ... Insulating layer, 135 ... Opening part, 140 ... Wiring, 240 ... Wiring, 500 ...・ Semiconductor device 600... Semiconductor element 620... Semiconductor element 690... Gold bump 750... Bump 800. Game machine, 6000 ... PC

Claims (13)

A semiconductor substrate having a first surface and a second surface opposite to the first surface;
A conductive portion provided on a surface of or inside the first surface of the semiconductor substrate and having a predetermined resistivity;
A through hole provided in the semiconductor substrate;
A through electrode provided in the through hole;
An insulating layer provided so as to cover the first surface and the second surface of the semiconductor substrate and a side wall of the through hole;
Wiring provided on the insulating layer on the first surface side of the semiconductor substrate;
A through electrode substrate. The wiring is arranged in a plurality, and has at least one of a part electrically connected to the conductive part, a part facing the conductive part, and a part electrically connected to the through electrode,
The through electrode substrate according to claim 1. The semiconductor substrate is a silicon substrate,
The insulating layer is a silicon oxide film;
The through electrode substrate according to claim 1. The resistivity of the conductive part is 0.1 Ω · cm or more and 10000 Ω · cm or less.
The through electrode substrate according to any one of claims 1 to 3. The conductive portion includes a group III or group V element,
The through electrode substrate according to claim 1. A second conductive portion provided to cover the conductive portion and having a polarity different from that of the conductive portion;
The through electrode substrate according to claim 5. A third conductive part provided on the surface of or inside the second surface of the semiconductor substrate and having the same polarity as the second conductive part;
The through electrode substrate according to claim 6. The wiring includes at least one of a first wiring, a second wiring, and a third wiring,
An inductor in which the first wiring is arranged in a loop;
A capacitive element having a part of the conductive part and the second wiring arranged to face a part of the conductive part;
And at least one passive element of a resistance element having another part of the conductive portion electrically connected to the third wiring,
The through electrode substrate according to claim 1. Using a semiconductor substrate having a first surface and a second surface opposite to the first surface,
Forming a conductive portion selectively on a part of the first surface of the semiconductor substrate;
Forming a through hole in the semiconductor substrate;
Forming an insulating layer on the first surface and the second surface of the semiconductor substrate and the side wall of the through hole;
Forming a through electrode in the through hole of the semiconductor substrate;
Forming a wiring on the insulating layer;
A method of manufacturing a through electrode substrate. The semiconductor substrate is a silicon substrate,
The insulating layer is a silicon oxide film;
The manufacturing method of the penetration electrode substrate of Claim 9. The insulating layer is formed by a thermal oxidation method.
The manufacturing method of the penetration electrode substrate of Claim 10. The conductive portion is formed by an ion implantation method.
The manufacturing method of the penetration electrode substrate as described in any one of Claims 9 thru | or 11. The conductive portion includes a group III or group V element,
The manufacturing method of the penetration electrode substrate as described in any one of Claims 9 thru | or 12.