JP6881066B2 - Manufacturing method of through silicon via substrate and through silicon via substrate - Google Patents

Description

The present disclosure relates to a through silicon via substrate and a method for manufacturing a through silicon via substrate.

A three-dimensional mounting technique in which high-frequency elements including semiconductor elements including integrated circuits and RF (Radio Frequency) elements are vertically laminated is widely used. In this technique, an interposer substrate on which a through electrode is formed (sometimes referred to as a wiring substrate or a through electrode substrate) is used (see Patent Document 1). As a result, the semiconductor element and the RF element are electrically connected on both sides of the substrate.

On the other hand, in the case of the above connection, since it is necessary to mount all the elements, the size of the through silicon via substrate tends to increase. Therefore, technological development for forming a passive element (inductor, capacitive element, resistance element, etc.) used as an RF element on a through electrode substrate is underway. For example, Patent Document 2 discloses a technique for forming a passive element using a glass substrate.

Japanese Patent No. 4634735 Special Table 2016-518702

However, when a glass substrate is used as in Patent Document 2, the type or size of the passive element that can be formed may be limited because the substrate warps or the like occurs in the manufacturing process of the through electrode substrate. Further, in the case of a glass substrate, when the wiring is provided in the same layer, the passive element may become large due to the problem of wiring processing accuracy. Further, in order to form the wiring to be a member of the passive element, it is necessary to newly provide a conductive layer and an insulating layer, which may increase the number of steps.

In view of such a problem, an object of the embodiment of the present disclosure is to provide a through electrode substrate capable of forming a passive element while suppressing the influence of the substrate without increasing the number of steps.

According to one embodiment of the present disclosure, a semiconductor substrate having a first surface and a second surface opposite to the first surface, and a conductive portion provided on the first surface of the semiconductor substrate and having a predetermined resistance. A through hole provided in the semiconductor substrate, a through electrode provided in the through hole, an insulating layer provided so as to cover the first and second surfaces of the semiconductor substrate and the side wall of the through hole, and a first of the semiconductor substrate. A through electrode substrate is provided that includes a wiring provided on an insulating layer on one side.

In the through electrode substrate, a plurality of wirings may be arranged and may have at least one of a portion electrically connected to the conductive portion, a portion facing the conductive portion, and a portion electrically connected to the through electrode. ..

In the through silicon via substrate, the semiconductor substrate may be a silicon substrate and the insulating layer may be a silicon oxide film.

In the through silicon via substrate, the resistivity of the conductive portion may be 0.1 Ω · cm or more and 10,000 Ω · cm or less.

In the through electrode substrate, the conductive portion may contain a group III or group V element.

The through silicon via substrate may further include a second conductive portion that is provided so as to cover the conductive portion and has a polarity different from that of the conductive portion.

In the through electrode substrate, a third conductive portion provided on the second surface of the semiconductor substrate and having the same polarity as the second conductive portion may be further included.

In the through electrode substrate, the wiring includes at least one of the first wiring, the second wiring, and the third wiring, and the inductor in which the first wiring is arranged in a loop, a part of the conductive part, and a part of the conductive part. It may include at least one passive element of a capacitive element having a second wiring arranged so as to face the third wiring and a resistance element having another part of a conductive portion electrically connected to the third wiring.

According to one embodiment of the present disclosure, a semiconductor substrate having a first surface and a second surface on the opposite side of the first surface is used, and a conductive portion is selectively formed on a part of the first surface of the semiconductor substrate. Through holes are formed in the semiconductor substrate, insulating layers are formed on the first and second surfaces of the semiconductor substrate and the side walls of the through holes, through electrodes are formed in the through holes of the semiconductor substrate, and wiring is formed on the insulating layer. A method of manufacturing a through electrode substrate is provided, which comprises the above.

In the method for manufacturing a through silicon via substrate, the semiconductor substrate may be a silicon substrate and the insulating layer may be a silicon oxide film.

In the method for manufacturing the through silicon via substrate, the insulating layer may be formed by a thermal oxidation method.

In the method for manufacturing the through electrode substrate, the conductive portion may be formed by an ion implantation method.

In the method for producing a through electrode substrate, the conductive portion may contain a Group III or Group V element.

According to one embodiment of the present disclosure, it is possible to provide a through silicon via substrate capable of forming a passive element without increasing the number of steps and without being affected by the substrate.

It is a top view explaining the through silicon via substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the through electrode substrate which concerns on one Embodiment of this disclosure. It is a circuit diagram explaining the through silicon via substrate which concerns on one Embodiment of this disclosure. It is a top view and sectional view explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view and sectional view explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view and sectional view explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view and sectional view explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view and sectional view explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view and sectional view explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view and sectional view explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view explaining the through silicon via substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view explaining the through silicon via substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view explaining the through silicon via substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view explaining the through silicon via substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the semiconductor device including the circuit element which concerns on one Embodiment of this disclosure. It is a perspective view explaining the electric apparatus including the semiconductor device which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the through electrode substrate which concerns on one Embodiment of this disclosure.

Hereinafter, the through electrode substrate, the passive element, and the like according to each embodiment of the present disclosure will be described in detail with reference to the drawings. It should be noted that each of the embodiments shown below is an example of the embodiments of the present disclosure, and the present disclosure is not construed as being limited to these embodiments. In the drawings referred to in the present embodiment, the same part or a part having a similar function is given the same code or a similar code (a code in which -1, -2, etc. are simply added after the numbers). The repeated description may be omitted. In addition, the dimensional ratio of the drawing may differ from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

<First Embodiment>
(1-1. Structure of through silicon via substrate)
FIG. 1 shows a top view of the through silicon via substrate 100. FIG. 2 shows a cross-sectional view of the through silicon via substrate 100 between A1 and A2. As shown in FIGS. 1 and 2, the through electrode substrate 100 includes a substrate 110, a conductive portion 113, a through electrode 120, an insulating layer 130, wiring 140, and wiring 240.

The substrate 110 has a first surface 110A and a second surface 110B opposite to the first surface 110B. Further, the substrate 110 is provided with a through hole 115. As shown in FIG. 1, the through hole 115 when viewed from the upper surface has a circular shape or a rectangular shape.

A semiconductor material is used for the substrate 110. For example, a silicon substrate, more specifically a P-type silicon substrate, is used for the substrate 110. The plate thickness of the substrate 110 may be appropriately set in the range of 100 μm or more and 700 μm or less. For example, 400 μm is used as the plate thickness of the substrate 110.

The material of the substrate 110 is not limited to the above, and the substrate 110 is a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, a gallium arsenide (GaAs) substrate, or a laminate of these substrates. May be done.

The conductive portion 113 is provided on or inside the first surface 110A of the substrate 110. The conductive portion 113 includes the conductive portion 113-1 and the conductive portion 113-2, but when it is not necessary to distinguish them, the conductive portion 113 will be described as the conductive portion 113. The conductive portion 113 mainly contains a metal of Group III or Group V. When the substrate 110 is a P-type silicon substrate, the conductive portion 113 contains phosphorus (P) or arsenic (As). The conductive portion 113 has a predetermined resistivity. The predetermined resistivity is controlled by the amount of phosphorus (P) or arsenic (As) contained in the conductive portion 113. At this time, phosphorus (P) or arsenic (As) is contained in the range of ^{1 × 10 16} atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ^{3 or less.} Further, it is desirable that the resistivity of the conductive portion 113 is 0.1 Ω · cm or more and 10000 Ω · cm or less.

The through electrode 120 is provided in the through hole 115. A low resistance material is used for the through electrode 120. For example, copper (Cu) is used for the through electrode 120. The material is not limited to copper (Cu), and a material containing gold (Au), silver (Ag), nickel (Ni) or tin (Sn) may be used. As shown in FIG. 2, when the through electrode 120 is viewed from a cross section, the electrode width of the through electrode 120 is appropriately set in the range of 5 μm or more and less than 100 μm.

The insulating layer 130 is provided so as to cover the first surface 110A, the second surface 110B, and the side wall of the through electrode 120 of the substrate 110. In this example, a silicon oxide film is used for the insulating layer 130. As the insulating layer 130, in addition to the silicon oxide film, an inorganic insulating material such as a silicon nitride film or an aluminum oxide film may be used as a single layer or in a laminated manner. Further, an organic insulating material such as an acrylic resin or an epoxy resin may be used for the insulating layer 130. The thickness of the insulating layer 130 is appropriately set in the range of 50 nm or more and 10 μm or less, preferably 100 nm or more and 5 μm or less.

The wiring 140 is provided on the insulating layer 130 on the first surface 110A side of the substrate 110. The wiring 140 includes the wiring 140-1, the wiring 140-2, the wiring 140-3, and the wiring 140-4, but when it is not necessary to distinguish them, the wiring 140 will be described as the wiring 140. Copper (Cu) is used for the wiring 140. The wiring 140 is not limited to copper (Cu), and the same metal material as the through electrode 120 may be used, such as aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), and the like. Materials may be used.

The wiring 240 is provided on the insulating layer 130 on the second surface 110B side of the substrate 110. The same material as the wiring 140 is used for the wiring 240.

(1-2. Configuration of passive element)
As shown in FIGS. 1 and 2, the through silicon via substrate 100 includes an inductor 101, a capacitance element 103, and a resistance element 105. The inductor 101, the capacitive element 103 and the resistance element 105 function as passive elements. In the through electrode substrate 100, the wiring 140 is used as a member for forming a passive element together with the insulating layer 130 and the conductive portion 113. The inductor 101, the capacitance element 103, and the resistance element 105 do not necessarily have to be all provided, and may be arranged according to the function.

For example, for the inductor 101, wiring 140-1 of the wiring 140 is used. The wiring 140-1 is arranged in a loop shape (more specifically, a spiral shape).

Further, in the capacitance element 103, the insulating layer 130 is used as a dielectric, the wiring 140-2 of the wiring 140 is one electrode of the capacitance element 103, and the conductive portion 113-1 of the conductive portion 113 is the other of the capacitance element 103. It is used as an electrode of. The wiring 140-2 and the conductive portion 113-1 are arranged so as to face each other via the insulating layer 130. The conductive portion 113-1 is connected to the wiring 140-4.

Further, as the resistance element 105, the wiring 140-3 and the conductive portion 113-2 are used. The wiring 140-3 and the conductive portion 113-2 have a portion that is electrically connected.

The wiring 140-1 and the wiring 140-3 have a portion connected to the through electrode 120. Further, the through electrode 120 is connected to the wiring 240 on the second surface 110B side of the substrate 110. As a result, the inductor 101 and the resistance element 105 are electrically connected. Further, the wiring 140-1 and the wiring 140-2 have a portion that is electrically connected. As a result, the inductor 101 and the capacitive element 103 are electrically connected.

FIG. 3 is a circuit diagram of the through electrode substrate 100 including the passive elements shown in FIGS. 1 and 2. In this example, the inductor 101, the capacitance element 103, and the resistance element 105 are arranged in series in the through electrode substrate 100 based on the connection relationship described above. At this time, the resistance element 105 is connected to the terminal 107. Further, the capacitance element 103 is connected to the terminal 109. The terminals 107 and 109 may be arranged on the insulating layer 130 in the same manner as the wiring 140. At this time, the terminal 109 and the wiring 140-4 may be connected. By using the through electrode substrate 100 in combination with the inductor 101, the capacitance element 103, and the resistance element 105, the through electrode substrate 100 can obtain a function as a bandpass filter.

(1-3. Manufacturing method of through silicon via substrate)
Next, a method of manufacturing the through silicon via substrate 100 shown in FIGS. 1 and 2 will be described with reference to FIGS. 4 to 10.

First, as shown in the top view of FIG. 4A and the cross-sectional view of FIG. 4B, a substrate 110 having a first surface 110A and a second surface 110B on the opposite side of the first surface 110A is used. For example, a semiconductor substrate (specifically, a P-type silicon substrate) is used as the substrate 110. In this example, the plate thickness of the substrate 110 is appropriately set in the range of 100 μm or more and 700 μm or less.

Next, as shown in the top view of FIG. 5A and the cross-sectional view of FIG. 5B, the resist film 111 is formed on the first surface 110A of the substrate 110. The resist film 111 is formed by a photolithography method. Ions 112 are added to the opened region 114 by ion implantation. As conditions for ion implantation, the treatment is performed in a range where the acceleration voltage is 10 keV or more and 300 keV or less, and the ion implantation amount is 1 × 10 ¹² atoms / cm ² or more and 1 × 10 ¹⁶ atoms / cm ^{2 or less.} In this example, the same amount of ions is added to regions 114-1 and 114-2 of the regions 114. It is desirable to heat after adding ions. As a result, a substitution reaction occurs between the silicon atom in the silicon substrate and the added ion, and the added ion diffuses in the silicon substrate, so that the resistivity of a part of the silicon substrate can be lowered. Therefore, the conductive portion 113 is selectively formed on a part of the substrate 110. After the ions 112 are added, the resist film 111 is removed.

Next, as shown in the top view of FIG. 6A and the cross-sectional view of FIG. 6B, a resist film 116 is formed on the substrate 110 by a photolithography method, and then a through hole 115 is formed. The through hole 115 is formed by a dry etching method such as a reactive ion etching method or a deep-drilling reactive ion etching method. Sulfur hexafluoride (SF ₆ ), methane tetrafluoride (CF ₄ ), methane hydrogen _{trifluoride (CHF 3} ), hydrogen (H ₂ ) or argon (Ar) are used in combination as the etching gas. After the through hole 115 is formed, the resist film 116 is removed.

Next, as shown in the top view of FIG. 7A and the cross-sectional view of FIG. 7B, the insulating layer 130 covers the first surface 110A and the second surface 110B of the substrate 110 and the side wall of the through hole 115. To form. The thickness of the insulating layer 130 is set in the range of 50 nm or more and 10 μm or less, preferably 100 nm or more and 5 μm or less. The insulating layer 130 is formed by a thermal oxidation method when a silicon substrate is used for the substrate 110. As the thermal oxidation method at this time, a wet thermal oxidation method is used. By using the wet thermal oxidation method, the oxidation rate of the silicon substrate is increased. As the thermal oxidation method for the silicon substrate, any one of a hydrochloric acid oxidation method, a dry thermal oxidation method, and a pyrogenic thermal oxidation method may be used in addition to the wet thermal oxidation method.

Next, as shown in the top view of FIG. 8A and the cross-sectional view of FIG. 8B, the through electrode 120 is formed in the through hole 115. The through silicon via 120 contains nickel (Ni), gold (Au), silver (Ag), tin (Sn), and the like, in addition to copper (Cu). The through electrode 120 may be formed by an electrolytic plating method or an electroless plating method. For example, when the through electrode 120 is formed using copper (Cu), a thin film of copper (Cu) is formed by a sputtering method. Next, a copper (Cu) film is formed by an electrolytic plating method using a copper (Cu) thin film as a seed layer. Finally, the copper (Cu) films formed on the first surface 110A and the second surface 110B of the substrate 110 are subjected to a chemical mechanical polishing (CMP) method to obtain the first surface 110A and the second surface 110B of the substrate 110. By removing the copper (Cu) above, the through electrode 120 is filled and formed.

Next, as shown in the top view of FIG. 9A and the cross-sectional view of FIG. 9B, the opening portion 135 is formed on the conductive portion 113 with respect to the insulating layer 130. The opening portion 135 is formed by using a photolithography method, an etching method, or the like.

Next, as shown in the top view of FIG. 10A and the cross-sectional view of FIG. 10B, the wiring 140 is formed on the upper surface of the insulating layer 130 on the first surface 110A side of the substrate 110 and the opening 135. .. Of the wiring 140, the wiring 140-1 and the wiring 140-3 are formed so as to be in contact with the through electrode 120. Further, the wiring 140-3 is formed so as to be connected to the conductive portion 113-2 of the conductive portion 113. Further, the wiring 140-1 is formed so as to have a spiral shape in this example. The wiring 140-1 is not limited to the spiral shape, and may be a loop shape. Further, the wiring 140-2 is formed so as to face the conductive portion 113-1 of the conductive portion 113. The wiring 140 is formed by the plating method in this example.

For example, when the wiring 140 is formed by a plating method, the following method is used. First, a copper (Cu) thin film is formed on the upper surfaces of the through electrode 120, the perforated portion 135, and the insulating layer 130 by an electroless plating method. Next, a resist film is formed on the copper thin film so as to be superimposed on the insulating layer 130. Next, a resist pattern is formed by a photolithography method. Next, the wiring 140 is formed by the electrolytic plating method. Finally, the resist pattern and the copper thin film under the resist pattern are removed. The above method is called a semi-additive method. After forming the wiring 140, the wiring 240 is formed on the second surface 110B side of the substrate 110. The wiring 240 is formed by the same method as the wiring 140. By the above method, the through silicon via substrate 100 shown in FIGS. 1 and 2 is manufactured.

The through silicon via substrate manufactured by the above method is used as a conductive portion by controlling the resistance of a part of the substrate. As a result, it is not necessary to newly provide a conductive layer and an insulating layer. That is, the through silicon via substrate can be manufactured without increasing the number of steps. Further, since the member of the passive element is manufactured together with the processing of the through electrode substrate, it is not necessary to mount the passive element on the through electrode substrate. That is, it is not necessary to provide a space for mounting, and the through electrode substrate can be made smaller. Furthermore, by manufacturing the through silicon via substrate using a silicon substrate, the influence of warpage of the substrate during the process is suppressed as compared with the glass substrate, and microfabrication is easier than with the glass substrate (that is, the line width is narrowed). The opening can be made smaller.) Therefore, it is possible to form a small passive element on the through electrode substrate while suppressing the influence of the substrate in the manufacture of the through electrode substrate.

<Second Embodiment>
Next, a through electrode substrate having a different structure will be described. The description of the structure, material and method shown in the first embodiment will be incorporated.

FIG. 11 shows a top view of the through silicon via substrate 100-1. FIG. 12 shows a cross-sectional view between A1 and A2 of the through silicon via substrate 100-1. As shown in FIGS. 11 and 12, the through electrode substrate 100-1 includes a substrate 110, a conductive portion 113, a through electrode 120, an insulating layer 130, wiring 140 and wiring 240, as well as a conductive portion 117.

The conductive portion 117 is provided so as to cover the conductive portion 113. Of the conductive portions 117, the conductive portion 117-1 covers the conductive portion 113-1. The conductive portion 117-2 covers the conductive portion 113-2. The conductive portion 117 has a function as an element separation layer of the conductive portion 113 used as a part of the passive element. The conductive portion 117 has a polarity different from that of the conductive portion 113. In this example, the substrate 110 is P-shaped. Further, the conductive portion 113 contains a group III atom such as boron (that is, the conductive portion 113 has a P type), and the conductive portion 117 contains a group V atom such as phosphorus or arsenic (that is, the conductive portion 117 has a P type). Has N type).

As shown in FIGS. 11 and 12, the element separation is ensured by providing the conductive portion 117. Therefore, the passive elements become smaller, and even when the passive elements are arranged close to each other, each passive element can function appropriately on the through electrode substrate.

<Third Embodiment>
Next, a through electrode substrate having a different structure will be described. The explanations of the structures, materials and methods shown in the first embodiment and the second embodiment will be incorporated.

FIG. 13 shows a top view of the through silicon via substrate 100-2. FIG. 14 shows a cross-sectional view of the through silicon via substrate 100-2 between A1 and A2. As shown in FIGS. 13 and 14, the through electrode substrate 100 further includes a conductive portion 119 in addition to the substrate 110, the conductive portion 113, the through electrode 120, the insulating layer 130, the wiring 140, the wiring 240, and the conductive portion 117. ..

The conductive portion 119 is provided on the second surface 110B of the substrate 110. The conductive portion 119 contains the same kind of material (metal of Group III or V) as the conductive portion 117, and has the same polarity as the conductive portion 117. In this example, the substrate 110 functions as a P-type, the conductive portion 113 functions as a P-type, the conductive portion 117 functions as an N-type, and the conductive portion 119 functions as an N-type conductive portion. The resistivity of the conductive portion 119 may be controlled to the same extent as that of the conductive portion 117, but is not limited thereto. The resistivity of the conductive portion 119 may be different from the resistivity of the conductive portion 117. At this time, the resistivity element required for each passive element can be obtained, such as using the conductive portion 113 on the first surface 110A side as the resistance element and using the conductive portion 119 on the second surface 110B side as the capacitive element. Further, by providing the conductive portion 119, the through electrode substrate 100-2 can be provided with the passive element at a higher density.

<Fourth Embodiment>
Next, a through electrode substrate having a different structure will be described. The explanations of the structures, materials and methods shown in the first to third embodiments are incorporated.

FIG. 15 shows a top view of the through silicon via substrate 100-3. FIG. 16 shows a cross-sectional view between A1 and A2 of the through silicon via substrate 100-3. As shown in FIGS. 15 and 16, the through electrode substrate 100-3 includes a substrate 110, a conductive portion 113, a through electrode 121, an insulating layer 130, and a wiring 140.

In the through electrode substrate 100-3, the through electrode 121 is provided not only on the through hole 115 but also on the first surface 110A side and the second surface 110B side of the substrate 110. At this time, the through electrode 121 is formed by a conformal plating method. Of the through electrodes 121, the portions provided on the first surface 110A side and the second surface 110B side of the substrate 110 can have the same functions as the wiring 140. Further, the through electrode 121 and the wiring 140 may be formed at the same time. As a result, the number of steps for forming the passive element on the through electrode substrate can be further reduced.

<Fifth Embodiment>
Next, a through electrode substrate having a different structure will be described. The explanations of the structures, materials and methods shown in the first to fourth embodiments are incorporated.

FIG. 17 shows a top view of the through silicon via substrate 100-4. FIG. 18 shows a cross-sectional view between A1 and A2 of the through silicon via substrate 100-4. As shown in FIGS. 17 and 18, the through electrode substrate 100-4 includes a substrate 110-4, a through electrode 120, an insulating layer 130, and wiring 140.

The through silicon via substrate 100-4 has a substrate 110-4 having a predetermined resistivity without providing the conductive portion 113. Specifically, a silicon substrate to which ions are added so that the resistivity is 0.1 Ω · cm or more and 10,000 Ω · cm or less at the time of manufacturing the silicon substrate is used. At this time, the substrate 110-4 is used as a part of the passive element. Since the through electrode substrate 100-4 does not need to be provided with the conductive portion 113, the number of steps for forming the passive element on the through electrode substrate can be further reduced.

<Sixth Embodiment>
In this embodiment, the semiconductor device including the through electrode substrate described in the first to fifth embodiments will be described.

FIG. 19 is a cross-sectional view of the semiconductor device 500. As shown in FIG. 19, the semiconductor device 500 includes a chipped semiconductor element 600 including a transistor, a semiconductor element 620, a through electrode substrate 100, and a package substrate 800. The semiconductor element 600 and the semiconductor element 620 have a function as a central processing unit (CPU) or a function as a storage device. The through silicon via substrate 100 has a function of relaying the semiconductor element 600, the semiconductor element 620, and the package substrate 800. The semiconductor element 600 and the semiconductor element 620 and the through silicon via substrate 100 are electrically connected to each other by using a gold bump 690 or the like. Further, the through electrode substrate 100 and the package substrate 800 are connected by using a solder bump 750 or the like containing tin, silver or the like. Further, the gap between the through electrode substrate 100 and the package substrate 800 may be sealed by filling with an underfill resin. As described above, the through silicon via substrate 100 includes a passive element such as an inductor 101, a capacitance element 103, or a resistance element 105. Therefore, in the semiconductor device 500, the passive element provided on the through electrode substrate 100 may be used for noise elimination or as a signal filter.

<7th Embodiment>
In this embodiment, an example in which the semiconductor device 500 described in the sixth embodiment is applied to an electric device will be described.

FIG. 20 is a diagram illustrating an electric device. The semiconductor device 500 including the semiconductor element 600, the semiconductor element 620, and the passive element includes, for example, a mobile terminal (mobile phone, smartphone and notebook personal computer, game device, etc.), an information processing device (desktop personal computer, server, car, etc.). It is installed in various electric devices such as navigation systems), home electric appliances (microwaves, air conditioners, washing machines, refrigerators), automobiles, etc. FIG. 20A shows a smartphone 4000. FIG. 20B shows a portable game machine 5000. FIG. 20C is a notebook personal computer 6000.

In these electric devices, the semiconductor device 500 including the semiconductor element 600, the semiconductor element 620, and the passive element is controlled by a noise filter, a signal filter, a CPU that executes an application program to realize various functions, and the like. It can have a function such as a part.

(Modification example 1)
In the first embodiment of the present disclosure, it has been described that the conductive portion 113-1 and the conductive portion 113-2 have the same resistivity due to the addition of ions, but the present invention is not limited to this. Different amounts of ions may be added to the conductive portion 113-1 and the conductive portion 113-2. As a result, each passive element has an appropriate resistivity, and the passive element can function in an optimum state.

(Modification 2)
In the first embodiment of the present disclosure, the inductor 101, the capacitance element 103, and the resistance element 105 have been described as being arranged in series, but they do not necessarily have to be connected in series. For example, the inductor 101, the capacitance element 103, and the resistance element 105 may be provided in parallel or branched, and may be appropriately changed according to the circuit design.

(Modification example 3)
In the first embodiment of the present disclosure, the insulating layer 130 has been described as being formed by a thermal oxidation method, but the present invention is not limited thereto. For example, a CVD (Chemical Vapor Deposition) method, a sputtering method, a vapor deposition method, or a dipping method may be used.

(Modification example 4)
In the first embodiment of the present disclosure, the wiring 140 shows an example of being formed by a plating method, but the wiring 140 is not limited thereto. The wiring 140 may be formed by a CVD method, a sputtering method, a vapor deposition method, or a printing method. At this time, the wiring 140 may be processed by a photolithography method and an etching method. Further, a material such as aluminum, tungsten, titanium, or molybdenum may be used for the wiring 140.

(Modification 5)
In the first embodiment of the present disclosure, an example in which the conductive portion 113-1 and the wiring 140-2 are arranged in parallel in the capacitance element 103 (so-called parallel flat plate) is shown, but the present invention is not limited to this. FIG. 21 is a cross-sectional view of the through silicon via substrate 100-5. The through electrode substrate 100-5 includes a substrate 110, a conductive portion 113, a through electrode 120, an insulating layer 130-5, wiring 140, and wiring 240. Further, the through silicon via substrate 100-5 has a capacitive element 103-5. The capacitive element 103-5 has a recess 118 in the substrate 110. At this time, the insulating layer 130-5 is arranged according to the shape of the recess 118, and the wiring 140-2 is also provided in the recess 118. As a result, the capacitive element 103-5 can have a trench shape. By having the above-mentioned shape, the capacitance element 103-5 can increase the amount of electric charge stored.

100 ... through electrode substrate, 101 ... inductor, 103 ... capacitive element, 105 ... resistance element, 107 ... terminal, 109 ... terminal, 110 ... substrate, 111 ... Resist film, 112 ... ion, 113 ... conductive part, 114 ... region, 115 ... through hole, 116 ... resist film, 117 ... conductive part, 118 ... recess, 119 ... Conductive part, 120 ... Through electrode, 121 ... Through electrode, 130 ... Insulation layer, 135 ... Opening part, 140 ... Wiring, 240 ... Wiring, 500 ... -Semiconductor device, 600 ... semiconductor element, 620 ... semiconductor element, 690 ... gold bump, 750 ... bump, 800 ... package substrate, 4000 ... smartphone, 5000 ... portable Game machine, 6000 ... Personal computer

Claims (12)

A semiconductor substrate having a first surface and a second surface opposite to the first surface,
A conductive portion provided on the surface or inside of the first surface of the semiconductor substrate and having a predetermined resistivity, and
Through holes provided in the semiconductor substrate and
Through electrodes provided in the through holes and
An insulating layer provided so as to cover the first surface and the second surface of the semiconductor substrate and the side wall of the through hole, and
Wiring provided on the insulating layer on the first surface side of the semiconductor substrate and
Only including,
The wiring includes at least one of a first wiring, a second wiring, and a third wiring.
An inductor in which the first wiring is arranged in a loop,
A capacitive element having the second wiring arranged so as to face a part of the conductive portion and a part of the conductive portion.
And at least one passive element of the resistance element having the other part of the conductive part electrically connected to the third wiring.
The through electrode and the wiring are provided in series.
Through electrode substrate. A plurality of the wirings are arranged and have at least one of a portion electrically connected to the conductive portion, a portion facing the conductive portion, and a portion electrically connected to the through electrode.
The through silicon via substrate according to claim 1. The semiconductor substrate is a silicon substrate and
The insulating layer is a silicon oxide film.
The through silicon via substrate according to claim 1 or 2. The resistivity of the conductive portion is 0.1 Ω · cm or more and 10000 Ω · cm or less.
The through silicon via substrate according to any one of claims 1 to 3. The conductive portion contains a Group III or Group V element.
The through silicon via substrate according to any one of claims 1 to 4. A second conductive portion that is provided so as to cover the conductive portion and has a polarity different from that of the conductive portion is further included.
The through silicon via substrate according to claim 5. A third conductive portion provided on the surface or inside of the second surface of the semiconductor substrate and having the same polarity as the second conductive portion is further included.
The through silicon via substrate according to claim 6. A semiconductor substrate having a first surface and a second surface on the opposite side of the first surface is used.
A conductive portion is selectively formed on a part of the first surface of the semiconductor substrate to form a conductive portion.
A through hole is formed in the semiconductor substrate to form a through hole.
An insulating layer is formed on the first surface and the second surface of the semiconductor substrate and the side wall of the through hole.
A through electrode is formed in the through hole of the semiconductor substrate, and the through electrode is formed.
It looks including forming a wiring on the insulating layer,
The wiring includes at least one of a first wiring, a second wiring, and a third wiring.
An inductor in which the first wiring is arranged in a loop,
A capacitive element having the second wiring arranged so as to face a part of the conductive portion and a part of the conductive portion.
And to form a passive element of at least one of the resistance elements having the other part of the conductive portion electrically connected to the third wiring.
The through electrode and the wiring are formed at the same time.
Manufacturing method of through silicon via substrate. The semiconductor substrate is a silicon substrate and
The insulating layer is a silicon oxide film.
The method for manufacturing a through silicon via substrate according to claim 8. The insulating layer is formed by a thermal oxidation method.
The method for manufacturing a through silicon via substrate according to claim 9. The conductive portion is formed by an ion implantation method.
The method for manufacturing a through silicon via substrate according to any one of claims 8 to 10. The conductive portion contains a Group III or Group V element.
The method for manufacturing a through silicon via substrate according to any one of claims 8 to 11.

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