JP2002057037A - Composite integrated circuit and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small composite integrated circuit by integrating a thin film capacitor which is large in capacity and a thin film coil on a semiconductor substrate where an integrated circuit has been provided. SOLUTION: A capacitor and a thin film coil are laminated on the surface of a semiconductor substrate opposite to its other surface on which an integrated circuit has been formed for the formation of a composite integrated circuit, or another semiconductor substrate on which a capacitor and a thin film coil have been formed is pasted on the semiconductor substrate for the formation of a composite integrated circuit. Furthermore, the composite integrated circuit is made a distributed constant circuit, by which a circuit of lower ESR can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a composite integrated circuit including a capacitor and an inductance used in a power converter such as a DC-DC converter.

[0002]

2. Description of the Related Art With the development of integrated circuits, the miniaturization of electronic circuits has been more and more advanced. Along with this, miniaturization of capacitors, which are essential circuit elements for various circuits, has become even more important. At present, for example, LC filters for power supply ICs are formed using small chip capacitors and chip coils.

In order to further reduce the size, a composite with an integrated circuit formed on a silicon (hereinafter referred to as Si) substrate has been considered. As a conventional thin film capacitor, for example, as disclosed in JP-A-63-49385, silicon dioxide (Si) is used as a dielectric.
O ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), etc.
It is common to use a material having a relative dielectric constant of at most 20.

Recently, in order to increase the capacity of capacitors, lead zirconium titanate [Pb (Zr _0.5 Ti _0.5 ) O ₃ , hereinafter referred to as PZT] and lead magnesium niobate [Pb ( Mg _0.5 Nb
_0.5 ) O ₃ , hereinafter referred to as PMN]. When making a thin film capacitor using such a composite perovskite oxide,
The lower electrode is required to withstand high temperatures, to have good crystallinity in order to increase the crystallinity of the oxide, and to be able to prevent the diffusion of lead. Currently, platinum (Pt) having strong self-orientation is used as such a lower electrode material. Pt is S
Since the adhesion to the i-wafer is weak, the Si wafer and P
A method of interposing a titanium layer as a buffer layer between the electrode and the t electrode has been used.

In order to further improve crystallinity and oxidation resistance, strontium ruthenate (SrRuO ₃ ,
A method of using a metal oxide such as SRO for the lower electrode has also been studied. On the other hand, electronic information devices, in particular, various types of portable electronic information devices have been remarkably spread. Many of these electronic information devices use a battery as a power source, and DC-DC
It has a built-in power converter such as a converter. Usually, the power conversion device includes magnetic induction components such as a coil and a transformer. With the demand for smaller and lighter electronic information devices, there is also a strong demand for the integration of magnetic induction components such as coils and transformers. However, since these devices are much larger in volume than integrated circuits, It is the biggest bottleneck for miniaturization.

The future direction for miniaturization of these magnetic induction components is to make them as small as chip components without limit.
There are two directions, that is, a direction in which the entire power supply is reduced by surface mounting and a direction in which a thin film is formed on a Si substrate. In recent years, there has been reported an example in which a magnetic induction component is mounted on a semiconductor substrate by applying semiconductor technology in response to a demand for downsizing of the magnetic induction component. The present applicant has already filed Japanese Patent Application No. 8-14962.
In No. 6, such a planar magnetic induction component was devised.

FIG. 6 is a partial sectional view of a composite integrated circuit in which a thin film coil is integrated on a semiconductor chip. Another Si substrate 18 in which a thin film coil 11 in which a coil conductor 7 is sandwiched between magnetic layers 6 is formed on the surface of an Si substrate 1 on which an integrated circuit 12 such as a switching element and a control circuit is fabricated by a thin film technique.
Are joined. The coil conductor 7 and the electrode of the integrated circuit 12 are connected by a connection conductor 21. Reference numeral 5 denotes an insulating layer for insulating the magnetic layer 6.

[0008]

However, when a thin film metal electrode is used as a lower electrode for a capacitor using a thin film process, the equivalent series resistance (hereinafter referred to as E) of the capacitor is reduced.
SR). The use of the above-mentioned lead-based composite perovskite oxide is expected to be restricted from the viewpoint of recycling.

Therefore, if the relative dielectric constant is increased by using a lead-free material such as barium strontium titanate [(Ba _0.5 Sr _0.5 ) TiO ₃ , hereinafter referred to as BST], very high crystallinity is obtained. A film must be formed. In order to produce a capacitor using a dielectric thin film having good crystallinity, a substrate or buffer layer having good crystallinity and a high substrate temperature of about 800 ° C. are required. However, when an attempt is made to form a composite integrated circuit with an integrated circuit on a Si substrate, the aluminum alloy wiring currently used on the integrated circuit cannot withstand this temperature.

[0010] Furthermore, there is a problem in that when a thin film coil is to be integrated on a semiconductor integrated circuit substrate, the utilization efficiency of the Si substrate is reduced. In view of such various problems, an object of the present invention is to provide a small-sized composite integrated circuit by integrating a small-diameter, large-capacity dielectric thin-film capacitor and a thin-film coil in an integrated circuit. It is in.

[0011]

In order to solve the above-mentioned problems, a composite integrated circuit according to the present invention comprises a semiconductor substrate having an integrated circuit formed on a surface layer on one principal surface and a dielectric material on the other principal surface of the semiconductor substrate. It is assumed that a capacitor having a thin film and an electrode thin film laminated thereon, and a thin film coil composed of a coil-shaped conductor and a magnetic thin film on at least one side thereof are further laminated. For example, a dielectric thin film and an electrode thin film are stacked on the other main surface of a semiconductor substrate having an integrated circuit formed on a surface layer on one main surface side, and a coil-shaped conductor and a magnetic thin film on at least one side thereof are further formed. And a thin film coil composed of

In this case, the utilization efficiency of the Si substrate can be increased, and at the same time, the ESR of the capacitor can be reduced.
A dielectric layer may be epitaxially grown directly on the other main surface of the semiconductor substrate, or a dielectric layer may be epitaxially grown via a buffer layer. If the dielectric layer is epitaxially grown through the buffer layer, a dielectric layer with better crystal quality can be epitaxially grown.

Particularly, if the buffer layer is conductive, Si
The substrate can be used as one electrode of the capacitor. At least a surface layer on the other main surface side of the semiconductor substrate has a lower resistivity than a portion of the semiconductor substrate on which an integrated circuit is formed. By making the surface layer on the other main surface side have a low specific resistance, the Si substrate can be used as one electrode of the capacitor, and the ESR of the capacitor can be further reduced.

The surface layer on the other main surface side can be made low in resistivity by ion implantation of impurities and heat treatment. The other main surface of the first semiconductor substrate on which the integrated circuit is formed on the surface layer on one main surface side, a dielectric thin film and an electrode thin film are formed on one main surface in a superposed manner, and a coil conductor and at least one of them are further formed. The above-described composite integrated circuit can also be formed by laminating the other main surface of the second semiconductor substrate formed by laminating a thin film coil composed of the magnetic layer on the side of the second semiconductor substrate. Also, this bonding method can be applied to a substrate having only a capacitor without a coil.

A conductive magnetic layer may be interposed between the coil conductor of the thin-film coil and the ferroelectric layer, or the coil conductor of the thin-film coil may be formed in direct contact with the dielectric layer. In the case where a conductive magnetic layer having a high magnetic susceptibility is interposed between the coil conductor of the thin film coil and the dielectric layer, the magnetic flux is concentrated. On the other hand, when the coil conductor is formed directly in contact with the ferroelectric layer, not only the metal electrode layer and the insulating layer can be omitted, but also a distributed constant circuit type ESR
Can be lowered.

If the insulating magnetic material is filled between the coil conductors of the thin film coil, the magnetic susceptibility can be increased. If the electrode provided at one end of the coil conductor of the thin-film coil and one electrode of the integrated circuit are connected by an embedded electrode provided through the silicon substrate, the size of the mounting can be reduced. it can.

As a method of manufacturing a composite integrated circuit as described above, a method of manufacturing a composite integrated circuit includes a method of manufacturing a semiconductor substrate in which a junction structure of an integrated circuit on a surface layer on one main surface and an embedded electrode penetrating the semiconductor substrate are formed. After forming the dielectric thin film and the electrode thin film on the side, forming the metal wiring of the integrated circuit, forming the thin film coil, it is preferable to connect the embedded electrode to the metal wiring of the integrated circuit and the electrode of the thin film coil.

In order to obtain a high quality dielectric thin film having a large relative dielectric constant by the epitaxial growth method, a film forming temperature of 80
A high temperature of 0 ° C. or higher is required. On the other hand, a typical metal wiring of an integrated circuit is an aluminum alloy having a melting point of 70%.
0 ° C. or less. Therefore, after forming the junction structure of the integrated circuit, it is desirable to form a high-quality dielectric thin film by the epitaxial growth method, and then to form the metal wiring of the integrated circuit.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on examples with reference to the drawings. [First Embodiment] FIG. 1 is a sectional view of a composite integrated circuit according to a first embodiment of the present invention. On one side of the Si substrate 1, a MOS
An integrated circuit 12 is formed (in the figure, a single MOSF
ET). As the Si substrate 1 for a MOS integrated circuit, an epitaxial wafer having a high specific resistance layer grown on a low specific resistance substrate is used. A ferroelectric layer 3 is formed on the back surface of the low specific resistance of the Si substrate 1 by a gallium nitride (GaN) buffer layer 2 having a thickness of, for example, 100 nm by an epitaxial growth method, and a metal electrode layer 4 is formed thereon. The thin film capacitor 10 is provided. The ferroelectric layer 3 is made of, for example, Ba _0.5 Sr having a thickness of 200 nm.
_0.5 TiO ₃ (BST), and the metal electrode layer 4 is, for example, platinum (Pt) having a thickness of 200 nm. Further, a thin-film coil 11 composed of a metal magnetic layer 6, a coil conductor 7, and an insulating magnetic layer 9 is formed thereon with an insulating layer 5 interposed therebetween.
Each of the insulating layer 5, the metal magnetic layer 6, the coil conductor 7, and the insulating magnetic layer 9 is, for example, a polyimide film having a thickness of 5 μm,
200 nm thick cobalt tantalum ruhafnium palladium (CoTaHfPd), 30 μm thick copper (Cu),
This is a magnetic gel containing permalloy powder having a thickness of 40 μm. 8 b and 8 c are extraction electrodes of the coil conductor 7, one of which is an embedded wiring 1 penetrating the Si substrate 1.
3 is connected to one of the electrodes of the MOS integrated circuit 12. Reference numeral 14 denotes an insulating layer for insulating the embedded electrode 10. Reference numeral 15 denotes a mold resin of an epoxy resin. MOS
The thickness of the composite integrated circuit including the integrated circuit 12, the capacitor 10, and the thin film coil 11 is about 350 μm.

Hereinafter, a method of manufacturing the composite integrated circuit of FIG. 1 will be described. A MOS integrated circuit 12 is formed on the surface layer of the Si substrate 1 by forming an oxide film, patterning by photolithography, doping impurities by ion implantation, heat treatment, and the like.
Is formed. Further, a through hole is provided in the Si substrate 1, a buried wiring 13 of a polycrystalline Si layer is buried in the through hole via an insulating layer 14, and a polycrystalline Si layer is formed on the surface of the MOS integrated circuit 12 for protection.

Next, through a buffer hydrofluoric acid solution (BHF) cleaning step, the back surface of the Si substrate 1 is set as a hydrogen-terminated clean surface, and the Si substrate 1 is immediately carried into the film forming apparatus.
The substrate temperature is heated to 800 ° C. or more, and the degree of vacuum is set to 10 ^−6.
When the pressure is higher than Pa, the hydrogen on the surface and the thin native oxide (SiO ₂ ) film are dissociated from the Si substrate 1 and the surface of the Si substrate 1 is reconstructed to form a 2 × 1 structure. You.

Further, S is deposited on the surface by electron beam evaporation or the like.
By supplying i atoms, the flatness of the outermost surface of the Si substrate 1 can be further improved. After obtaining a clean flat surface, the buffer layer 2 is formed. In order to epitaxially grow the ferroelectric layer 3 on the Si substrate 1, the buffer layer 2 must have good lattice matching with the Si substrate 1, be an oxygen barrier layer, be conductive, and the like. . Here, a film was formed by pulsed laser irradiation deposition (PLD) using GaN. Cerium oxide (CeO ₂ ), titanium nitride (TiN), yttrium saturated zirconia (YSZ), or the like is used for the buffer layer 2, and the buffer layer 2 can be formed by a molecular beam epitaxy (MBE) method, a sputtering method, or the like.

This buffer layer is not always necessary when the ferroelectric layer 3 is formed directly on the Si substrate 1. In that case, in order to suppress the activity of the clean Si surface, a process of terminating with strontium (Sr), arsenic (As), or the like is required. BST was formed as the ferroelectric layer 3 by the PLD method. The film can also be formed by an MBE method, a sputtering method, or the like. By the lattice matching, the ferroelectric layer 3 grows epitaxially, and in the case of BST, a thin film having a relative dielectric constant of 400 or more can be obtained.

After the formation of the ferroelectric layer 3, the metal electrode layer 4 is formed. It is desired that the ferroelectric layer 3 and the metal electrode layer 4 have high adhesion. Here, a Pt film is formed by a sputtering method. Thereafter, the Si substrate 1 is transported from the film forming chamber, and Al wiring and the like of the MOS integrated circuit 12 on the front surface side of the Si substrate 1 are applied.
In order to further reduce the resistance of the upper electrode layer, A
1 may be deposited, or may be plated with Cu or the like.

Thereafter, as shown below, the thin film coil 1
1 is formed on the metal electrode layer 4. First, a polyimide is applied on the metal electrode layer 4, the insulating layer 5 is formed and patterned, and then the coil electrode 8a is formed by Al evaporation or plating of Cu or the like. Next, a metal magnetic layer 6 of CoTaHfPd is formed by sputtering and patterned. Then apply a photosensitive polyimide to a thickness of, for example, 30 μm,
Here, a coil-shaped recess is formed. Using this polyimide layer as a mold, Cu is plated by electroplating to form a coil conductor 7.

After the polyimide layer is removed by plasma etching or the like, the space between the coil conductors 7 and the upper portion thereof are filled with an insulating magnetic material gel containing permalloy or the like and cured to form an insulating magnetic material layer 9. In addition, epoxy resin mold resin 1
After molding with 5, a window for forming an electrode is opened, and coil electrodes 8b and 8c are provided.

Finally, the embedded wiring 13, the coil electrode 8c at the center of the coil, and one electrode of the MOS integrated circuit 12 are connected, and the manufacturing process of the composite integrated circuit is completed. With such a structure, the utilization efficiency of the semiconductor substrate surface can be tripled. An example in which a capacitor is provided on the back side of a semiconductor substrate on which an integrated circuit is formed is described in JP-A-56-56664. However, in this example, the semiconductor substrate is separated from the semiconductor substrate by an insulating film, and the substrate is not used as an electrode as in the present invention.

In terms of the performance of the composite integrated circuit of the first embodiment, a high dielectric constant is obtained in the capacitor portion because the ferroelectric layer 3 is grown epitaxially, and is 1 μF or more in the case of an element having a side of 5 mm. Is obtained. Moreover, since the low-resistance Si substrate 1 is directly used as the lower electrode, the equivalent series resistance (ESR) is about 150 mΩ, which is about half as low as the conventional value. For the thin-film coil 11, the manufacturing process is simplified by using the magnetic gel to form the insulating magnetic layer 9, and a coil having an inductance of 1H or more can be obtained.

Instead of using a magnetic gel, the structure may be formed by forming a ferromagnetic thin film on a coil in the same manner as a conventional thin film coil, and then performing a heat treatment in a magnetic field to increase the magnetic susceptibility. . Second Embodiment FIG. 2 is a sectional view of a composite integrated circuit according to a second embodiment.

The difference from the first embodiment is that a heavily doped layer 18 is formed on the back surface of the Si substrate 1. Si
A high-concentration doped layer 18 having a low resistivity is formed on the rear surface of the substrate 1 by ion implantation of impurities and heat treatment, and is used as a lower electrode of the ferroelectric layer 3. The other parts are manufactured in the same manner as in the first embodiment.

By providing the highly doped layer 18,
The potential of the Si substrate 1 can be more reliably grounded,
Further, by connecting to the housing-side ground, it is possible to prevent noise from getting on the signal line. Alternatively, it can be connected to the MOS integrated circuit 12 on the surface or the embedded electrode 10. Third Embodiment FIG. 3 is a sectional view of a composite integrated circuit according to a third embodiment.

In this example, the MOS integrated circuit 12, the capacitor 10, and the thin-film coil 11 are each independently formed of a different Si.
Substrates 1, 18 are formed and later they are
It is the one that was bonded at 5. The other parts are manufactured in the same manner as in the first embodiment. Embedded wiring 1 of polycrystalline Si, etc.
3 connects the electrode of the MOS integrated circuit 12 and the electrode of the thin film coil 11 as in the above two examples. Both substrates may be thinned using a chemical mechanical polishing (CMP) method. Further, although low-resistance Si is used for the capacitor-side substrate, it is not limited to the Si substrate.

The MOS integrated circuit 12, the capacitor 10,
The thin-film coil 11 and the other Si substrates 1, 1
9, the process conditions such as the film forming temperature can be optimally selected without concern for each other. Furthermore, since the steps can be performed in parallel, there is an advantage that the period required for manufacturing can be shortened. The performance of the third embodiment is such that a high dielectric constant is obtained in the capacitor portion because the ferroelectric layer is grown epitaxially, and a dielectric constant of 1 μF or more is obtained when the device has a side of 5 mm. And M
Since the low-resistance substrate is used directly as the lower electrode without worrying about the OS process, the equivalent series resistance (ES
R) is as low as about 120 mΩ.

On the coil side, the use of a magnetic material gel simplifies the manufacturing process, and allows obtaining a coil having an inductance of 1H or more. This performance is, for example, a DC-voltage of about 5 V for the input voltage and about 3 V for the output voltage.
This is sufficient as an output filter of the DC converter. In addition, the thickness of the composite circuit including the capacitor and the thin-film coil MOS can be as large as that of the first and second embodiments, about 300 μm, by using the CMP in the third embodiment. The miniaturization can be achieved.

[Fourth Embodiment] FIG. 4 is a sectional view of a composite integrated circuit according to a fourth embodiment. The difference from the previous embodiments is that the metal electrode layer 4 and the insulating layer 5 are eliminated, the metal magnetic layer 6 is formed directly on the ferroelectric layer 3, and the coil conductor 7 is formed directly above the metal magnetic layer 6. Is a point.

The equivalent circuit of the LC filter circuit shown in FIGS. 1 to 3 is a lumped constant type circuit as shown in FIG.
On the other hand, the equivalent circuit of the fourth embodiment is of a distributed constant type as shown in FIG. By employing the distributed constant type in this way, the low ES of about 100 mΩ compared to the first to third embodiments.
R conversion can be realized. In addition, there is an advantage that the manufacturing process is simplified and the cost is reduced.

[0037]

As described above, according to the present invention, a capacitor and a thin-film coil are formed on the other side of a semiconductor substrate on which an integrated circuit is formed, or a capacitor and a thin-film coil are formed on the other side. By using a composite integrated circuit in which another substrate is bonded, the utilization efficiency of the semiconductor substrate can be increased and the equivalent series resistance, which is a drawback of the conventional thin film capacitor, can be reduced.

Further, by using a distributed constant circuit,
A circuit with a lower ESR can be configured. Further, by forming a dielectric layer at a high substrate temperature and then forming a metal wiring of an integrated circuit, a large-capacity capacitor is realized while being integrated with an integrated circuit process. Thus, for example, the functions required for the DC-DC converter can be constituted by one chip, and the size of a portable device or the like provided with the functions can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a composite integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a composite integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a composite integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a sectional view of a composite integrated circuit according to a fourth embodiment of the present invention.

5A is an equivalent circuit of the composite integrated circuit according to the first, second, and third embodiments; FIG. 5B is an equivalent circuit of the composite integrated circuit according to the fourth embodiment;

FIG. 6 is a cross-sectional view of a conventional composite integrated circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Si substrate 2 buffer layer 3 ferroelectric layer 4 metal electrode layer 5 insulating layer 6 metal magnetic layer 7 coil conductor 8 a, 8 b, 8 c coil electrode 9 insulating magnetic layer 10 capacitor 11 thin film coil 12 MOS integrated circuit 13 embedded Wiring 14 Insulating layer 15 Mold resin 16 Protective film 17 Connection wiring 18 Highly doped layer 19 Si substrate 20 Joint

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Eiichi Yonezawa 1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Inventor Ken Suzuki 1st Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 F term in Fuji Electric Co., Ltd. (reference) 5E070 AA05 AB01 AB10 BA12 BB03 CB12 EA01 5E082 AA01 AB03 BB03 BC40 DD11 5F038 AC05 AC07 AC14 AC15 AC18 AZ04 BH10 BH19 EZ14 EZ20

Claims (20)

[Claims] 1. A capacitor provided with a dielectric thin film and an electrode thin film on the other main surface side of a semiconductor substrate having an integrated circuit formed on a surface layer on one main surface side, a coil conductor and at least one side thereof. And a thin film coil having a magnetic layer of the above. 2. A capacitor provided with a dielectric thin film and an electrode thin film is formed on the other main surface of a semiconductor substrate having an integrated circuit formed on a surface layer on one main surface side, and a coil conductor and at least one of the coil conductor are provided. 2. The composite integrated circuit according to claim 1, wherein a thin-film coil composed of the magnetic layer on the side is superposed. 3. The composite integrated circuit according to claim 2, wherein a dielectric layer is directly epitaxially grown on the other main surface of said semiconductor substrate. 4. The composite integrated circuit according to claim 2, wherein a dielectric layer is epitaxially grown on the other main surface of said semiconductor substrate via a buffer layer. 5. The composite integrated circuit according to claim 4, wherein the buffer layer is conductive. 6. The semiconductor device according to claim 2, wherein at least a surface layer on the other main surface side of the semiconductor substrate has a lower specific resistance than a semiconductor substrate in a portion where an integrated circuit is formed. A composite integrated circuit as described. 7. The composite integrated circuit according to claim 6, wherein the surface layer on the other main surface side of the semiconductor substrate has an impurity distribution formed by ion implantation and heat treatment. 8. A first semiconductor substrate having an integrated circuit formed on a surface layer on one main surface side and a capacitor having a dielectric thin film and an electrode thin film formed on one main surface. A composite integrated circuit, wherein the other main surface of the two semiconductor substrates is bonded together. 9. The composite integrated circuit according to claim 8, wherein a dielectric layer is directly epitaxially grown on one main surface of the second semiconductor substrate. 10. The composite integrated circuit according to claim 8, wherein a dielectric layer is epitaxially grown on one main surface of the second semiconductor substrate via a buffer layer. 11. The composite integrated circuit according to claim 10, wherein the buffer layer is conductive. 12. A semiconductor device according to claim 8, wherein at least a surface layer on one main surface side of said second semiconductor substrate has a lower specific resistance than a semiconductor substrate in a portion where an integrated circuit is formed. The composite integrated circuit according to any one of the above. 13. The composite integrated circuit according to claim 12, wherein the surface layer on one main surface side of the second semiconductor substrate has an impurity distribution formed by ion implantation and heat treatment. 14. A thin film coil comprising: a capacitor provided with a dielectric thin film and an electrode thin film on one main surface of a second semiconductor substrate; and a coil conductor and a magnetic layer on at least one side thereof formed thereon. And the other main surface of the second semiconductor substrate is bonded to the other main surface of the first semiconductor substrate. A composite integrated circuit as described. 15. A thin film coil comprising a conductive magnetic layer interposed between a coil conductor and a dielectric layer.
15. The composite integrated circuit according to any one of claims 8 to 14. 16. The composite integrated circuit according to claim 1, wherein the coil conductor of the thin film coil is formed in direct contact with the dielectric layer. 17. The composite integrated circuit according to claim 15, wherein the coil conductor of the thin-film coil is covered with an insulating magnetic material. 18. An electrode according to claim 17, wherein an electrode provided at one end of the thin film coil and one electrode of the integrated circuit are connected by an embedded electrode provided through the silicon substrate. Composite integrated circuit. 19. The composite integrated circuit according to claim 1, wherein the dielectric thin film is a lead-free oxide having a perovskite crystal structure. 20. A dielectric thin film and an electrode thin film are formed on the other main surface of a semiconductor substrate having an integrated circuit formed on a surface layer on one main surface side, and a coil conductor and at least one side thereof are formed. A method of manufacturing a composite integrated circuit in which thin-film coils each comprising a magnetic layer are superposed, wherein a semiconductor having a junction structure of an integrated circuit on a surface layer on one main surface side and an embedded electrode penetrating a semiconductor substrate is formed. After forming a dielectric thin film and an electrode thin film on the other main surface side of the substrate, a metal wiring of the integrated circuit is formed, a thin film coil is formed, and the embedded electrode, the metal wiring of the integrated circuit, and the electrode of the thin film coil are formed. A method of manufacturing a composite integrated circuit, comprising forming a connection wiring to be connected.