JPH11220103A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable superhigh integrated FRAME/DRAM capable of being produced in high volume and a method for manufacturing the FRAME/DRAM. SOLUTION: A semiconductor storage device incorporates at least a first semiconductor substrate 11 on which a transistor is arranged, a second semiconductor substrate 51 having epitaxial capacitors (52, 54, 55, and 56) corresponding to the transistor, and connecting sections (31, 47, and 59) which electrically connects the main electrode area 21 of the transistor to the epitaxial capacitors (52, 53, 54, 55 and 56). After a first laminated layer 47 and a second laminated layer 59 are respectively formed on the entire surfaces of the first semiconductor substrate 11 and second semiconductor substrate 51 and the layers 47 and 59 are bonded to each other in a butted state, and thereafter a capacitor is patterned.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device suitable for realizing an ultra-high integration density of 1 gigabit or more, and more particularly to a semiconductor device using an epitaxial capacitor having a dielectric thin film layer of a perovskite type crystal structure. The present invention relates to a storage device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Recently, a ferroelectric random access memory (FRAM) has been developed.
trick Random Access Memor
A storage device (ferroelectric memory) using a ferroelectric thin film layer referred to as y) has been developed, and some have already been put to practical use. A ferroelectric memory (FRAM) is non-volatile and has a feature that stored contents are not lost even after power is turned off. In addition, when the thickness of the ferroelectric thin film layer is sufficiently small, the spontaneous polarization is rapidly inverted, and a semiconductor memory device using a thin film capacitor formed of the ferroelectric thin film layer is a MOS DRAM (hereinafter referred to as a "DRAM"). Abbreviated.) Writing and reading can be performed at the same high speed.
In addition, since a 1-bit memory cell can be formed with one transistor and one ferroelectric capacitor as in the case of a DRAM, it is suitable for increasing the capacity.

A ferroelectric thin film suitable for a ferroelectric memory needs to have a large remanent polarization, a small temperature dependence of the remanent polarization, and a capability of retaining the remanent polarization for a long time (retention). It is.

At present, lead zirconate titanate (PZT) is mainly used as a ferroelectric material for a ferroelectric memory.
Despite the magnitude of spontaneous polarization,
Diffusion and evaporation are likely to occur at relatively low temperatures (5
For example, it is said that it is difficult to cope with miniaturization.

On the other hand, the present inventors have proposed an oxide substrate such as strontium titanate (SrTiO ₃ , hereinafter abbreviated as “STO”) single crystal as a substrate.
For example, strontium ruthenate (SrRuO ₃ , hereinafter abbreviated as “SRO”) is used as the lower electrode layer, and barium strontium titanate (Ba _x Sr _1-x TiO 2) is used as a dielectric, which has a lattice constant slightly larger than SRO. _{3. In} the following, "BSTO"
Abbreviated. ) Was selected, and all of these layers were epitaxially grown to form a thin film capacitor. For the multilayer epitaxial growth of this thin film capacitor, a film formation method called a RF magnetron sputtering method, in which misfit dislocations are relatively unlikely to be formed during the film formation process, is adopted. Also found that the c-axis length of BSTO can be artificially controlled by using BSTO as a strain lattice by the “epitaxial effect”. That is, Ba
By growing a single crystal BSTO having a rich composition on an oxide substrate such as strontium titanate (STO),
It has been found that the ferroelectric Curie temperature can be shifted to a higher temperature side by using the stress caused by the mismatch of the lattice constant with the oxide substrate. As a result, it was found that a large remanent polarization was exhibited in a room temperature region, and that a sufficiently large remanent polarization could be maintained even when the temperature was increased to about 85 ° C.

Further, the present inventors have proposed that a single crystal BSTO having an Sr-rich composition can be used, for example, to have a film thickness of 20 nm.
It has been experimentally confirmed that a very high dielectric property, which is a dielectric constant of 800 or more, which is very preferable for a DRAM capacitor, can be realized. On the other hand, the dielectric constant of a capacitor made of a polycrystalline film having the same film thickness is about 200 at most. This means that a twice as large high dielectric thin film was obtained.

As described above, the present inventors have found that a single crystal BSTO having a Ba-rich composition can
It has been confirmed that a very preferable ferroelectric thin film capacitor can be realized. Ba-rich composition means B
This means that the composition x of a = about 0.6-0.9. On the other hand, S
It has been confirmed that a single crystal BSTO having an r-rich composition can obtain a high dielectric property with an extremely high dielectric constant, and can realize a high dielectric thin film capacitor which is very preferable as a DRAM. The Sr-rich composition refers to an Sr composition of 0.6-0.
It means about 9 (Ba composition x = about 0.4-0.1). Therefore, by selecting the composition of Ba or Sr of the single crystal dielectric thin film grown epitaxially, it is possible to realize an FRAM or DRAM with a very high integration density. In other words, practical use of a gigabit memory is expected by using a single crystal dielectric thin film capacitor grown epitaxially.

[0008] The history of the development of semiconductor integrated circuits has focused on improving the integration density per chip and reducing the cost per chip. For example, the development of DRAM
In three years, the integration has been quadrupled, and the same trend is expected to continue in the future. The cell size of semiconductor integrated circuits has been further reduced due to the growing needs, and it can be said that the adoption of a thin film capacitor using a ferroelectric thin film layer is one of the conclusions for the reduction of the cell size. Looking back on the history of cell size reduction, 4Mb DRAM was a turning point. In the 4Mb DRAM, sufficient capacity cannot be ensured in a planar structure due to the relation of the capacitor area, and a three-dimensional capacitor such as a trench type in which a hole is dug and a capacitor is buried therein and a two-layer capacitor is stacked on a transistor, etc. The structure had to be adopted. However, the integration density is further improved, and 256Mb DRAM or 1Gb DRAM
However, even if these structures are used, an oxide film (SiO ₂
It has become extremely difficult to use a film as a capacitor insulating film, and the use of a high dielectric thin film layer or a ferroelectric thin film layer as a capacitor insulating film has emerged.

On the other hand, as the integration density per chip increases, the chip size tends to increase. The proposition of increasing the chip size and reducing the cost per chip inevitably requires a larger wafer size, and the diameter of the silicon wafer (silicon substrate) is 200 mm (8 inches). 30 from above
It is becoming 0 mm (12 inches), and further enlargement of the diameter is being studied. In addition, compound semiconductors mainly made of gallium arsenide (GaAs) having a diameter of 100 mm (4 inches) or more are available on the market, and further enlargement of the diameter is being studied.

In any case, in order to apply to a semiconductor memory having an ultra-high integration density of 1 gigabit or more, a structure in which a fine transistor and a capacitor capable of ensuring a constant capacitance value even in a small area are three-dimensionally stacked. It is essential. As described above, an epitaxial capacitor is promising as a capacitor that can ensure a constant capacitance value even in a small area. Known as a three-dimensional stacking method of a transistor and this epitaxial capacitor are a transistor formed on a silicon substrate and a transistor formed on an oxide substrate such as magnesium oxide (MgO) or strontium titanate (STO). This is a bonding structure with an epitaxial capacitor. For example, Japanese Patent Application Laid-Open No. 8-1392
No. 92 (see FIG. 7 of the publication),
Japanese Patent Application Publication No. 980 (see FIGS. 1 and 2 of the publication) proposes a device structure in which a silicon substrate 11 and an oxide substrate 110 such as an MgO or STO substrate are bonded together as shown in FIG. .

FIGS. 43 (a) and 43 (b) are cross-sectional views which are orthogonal to each other. That is, FIG.
FIG. 43 (b) is a cross-sectional view as viewed from the AA direction of (a), and FIG. 43 is a cross-sectional view as viewed from the BB direction of FIG. 43 (b).
(A). As shown in FIG. 43, a plurality of MOS transistors are arranged in a matrix on the surface of a p-well 12 formed on a silicon substrate 11. These plural MOS transistors are referred to as “STI (Shallow Trench Isolation: ShallowTrue).
An element isolation region 13 made of a buried oxide film called an “nch isolation (region)”. In the MOS transistor of FIG. 43, the gate oxide film 29 and the gate electrode 37 on the surface of the p well 12 and the p well 1
2 are formed from a source region 21 and a drain region 22 made of an n ⁺ region. Here, the gate electrode 3
Reference numeral 7 denotes a part of a word line.

A bit line 35 is formed on the drain region 22 via a bit line contact plug (not shown). The n ⁺ source region 21 is connected to an epitaxial capacitor (56,5) disposed above via a capacitor contact plug 31 made of polycrystalline silicon (doped polysilicon) doped with an impurity or a refractory metal.
5, 54, 53, 52).

The epitaxial capacitor comprises an upper barrier metal layer 56, an upper electrode layer 55 such as SRO, a dielectric thin film layer 54 such as BSTO, a lower electrode layer 53 such as SRO, and a lower barrier metal layer 52. In FIG. 43, the upper electrode layer 55 is shown below and the lower electrode layer 53 is shown above only because these layers are named based on the manufacturing process. That is, the lower barrier metal layer 52 and the lower electrode layer 5 are formed on an oxide substrate 110 such as MgO or STO.
3, a dielectric thin film layer 54, an upper electrode layer 55, and an upper barrier metal layer 56 are laminated in this order to form a capacitor portion;
Since the oxide substrate 110 is turned upside down and then bonded to the silicon substrate 11 on which the MOS transistor is formed, the order just happens to be called. This bonding is performed as shown in FIG.
This is realized by bringing the first bonding layer 49 on the silicon substrate 11 side and the second bonding layer 57 on the oxide substrate 110 side into contact with each other. In FIG. 43, reference numerals 32, 33, 3
4, 36, 37 and 38 are oxide films (SiO ₂ films), PSG
An insulating film such as a film, a BPSG film, a nitride film (Si ₃ N ₄ film), or a polyimide film.

[0014]

As described above, the semiconductor memory device using the oxide substrate 110 shown in FIG.
The ferroelectric Curie temperature was shifted to a higher temperature side by utilizing the stress caused by the mismatch between the lattice constant of 0 and the dielectric thin film layer 54, and the ferroelectric characteristics at room temperature were realized. In other words, BST is caused by the "epitaxial effect".
In order to artificially control the c-axis length of BSTO by using O as a strain lattice, the oxide substrate 110 was essential.

However, this means that the semiconductor memory device using the oxide substrate 110 exhibits the following problems.

(1) Silicon wafers (silicon substrates) having a diameter of 8 inches or more are easily available commercially, whereas oxide substrates such as MgO substrates and STO substrates have a diameter of 3 inches or more. Is difficult even at the research level. Substrate (wafer) with a diameter of 3 inches or less
It is difficult to mass-produce a semiconductor memory device based on the above. Therefore, a semiconductor memory device using the oxide substrate 110 has a high production cost per chip.

(2) Thermal expansion coefficient of silicon substrate is 2.5p
pm / ° C, whereas the MgO and STO substrates are 9
Since it has a thermal expansion coefficient of not less than ppm / ° C, for example, 500 ° C
If the oxide substrate is cooled to room temperature, a tensile stress of several tens of kg / mm ² or more is applied to the oxide substrate, and the substrate is cracked. Even if it does not break, very large warpage occurs. Since semiconductor storage devices in the gigabit era require ultra-fine processing at the deep sub-micron to nanometer level, if warpage occurs in the substrate,
Subsequent lithography steps become impossible.

Further, in addition to the disadvantage inherent in using such an oxide substrate 110, the semiconductor memory device shown in FIG. Layer 49) and the insulating part 34. On the other hand, the surface of the oxide substrate 110 facing the silicon substrate 11 is composed of a metal electrode portion (second bonding layer) 57 and an insulating portion 38. The conditions for connecting the metal electrode portions 49 and 57 and the conditions for connecting the insulating portions 34 and 38 are generally different. Therefore, these metal electrode portions 49 and 57 and insulating portion 3
4 and 38 under the same conditions, the two substrates 11 and 110
Are difficult to adhere uniformly to one another.

(4) The pattern of the electrode portion (source region) 21 of the transistor formed on the silicon substrate 11;
It is necessary to connect the patterns of the electrode portions (upper electrode layer 55, upper barrier metal layer 56) of the capacitor formed on the oxide substrate 110 in one-to-one correspondence, but the thermal expansion coefficients are different as described above. It is practically impossible to match patterns formed on a substrate at high temperatures with submicron accuracy over the entire surface of a wafer.

There is a problem caused by the structure.

In view of the above problems, it is an object of the present invention to provide a semiconductor memory device (semiconductor memory) having a large capacity of gigabit or more and a low product unit price.

Another object of the present invention is to facilitate mass production,
It is an object to provide a semiconductor memory device using a ferroelectric thin film layer or a high dielectric constant thin film layer.

Still another object of the present invention is to provide a novel structure of a semiconductor memory device which can be based on a semiconductor substrate whose diameter can be easily increased when a single crystal dielectric thin film capacitor is epitaxially grown. The purpose is to:

Still another object of the present invention is to provide a semiconductor memory device having a single crystal dielectric thin film capacitor which can be easily processed in ultra-fine processing at a deep submicron to nanometer level.

Still another object of the present invention is to provide a semiconductor memory device in which a good bonding interface can be obtained between bonding layers and an open defect does not occur.

Still another object of the present invention is to provide a semiconductor memory device in which there is no possibility of leak current or short circuit between adjacent memory cells.

Still another object of the present invention is to provide a method of manufacturing a semiconductor memory device which can easily increase the capacity of gigabit or more and has a low manufacturing cost.

Still another object of the present invention is to provide a manufacturing method for mass-producing a semiconductor memory device using a ferroelectric thin film layer or a high dielectric constant thin film layer.

Still another object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of epitaxially growing a single crystal dielectric thin film capacitor on a large-diameter substrate.

It is still another object of the present invention to provide a method of manufacturing a semiconductor memory device having a single crystal dielectric thin film capacitor which can be easily processed in a sub-quarter micron to nanometer level.

Still another object of the present invention is to provide a method of manufacturing a semiconductor memory device in which a good bonding interface is obtained between bonding layers and an open defect does not occur.

Still another object of the present invention is to provide a method of manufacturing a semiconductor memory device in which there is no possibility of leak current or short circuit between adjacent memory cells.

[0033]

Means for Solving the Problems In order to achieve the above-mentioned object, the present inventors have conducted various studies, simulations and experiments, and as a result of repeated studies, have obtained the following first to third inventions. Was.

That is, the first invention provides a first semiconductor substrate having a plurality of transistors arranged in a matrix, and a second semiconductor substrate having a plurality of perovskite-type epitaxial capacitors respectively corresponding to the plurality of transistors. And a connection portion for electrically connecting each main electrode region of the transistor and the epitaxial capacitor in a one-to-one correspondence. Here, the “first semiconductor substrate” and the “second semiconductor substrate” are referred to as a bulk semiconductor by the Czochralski method (CZ method), the floating zone method (FZ method), the magnetic field application Czochralski method (MCZ method), or the like. It means a semiconductor substrate obtained by a crystal growth method. It means a semiconductor substrate which is commercially available in the form of a so-called silicon wafer or gallium arsenide wafer. From the viewpoint of increasing the diameter, a silicon wafer is particularly preferable. That is, the semiconductor substrate according to the first aspect of the present invention may be a semiconductor substrate such as a silicon wafer that has a predetermined shape such as 8 inches Φ to 12 inches Φ at the start of the semiconductor memory device manufacturing process. It is intended to exclude a semiconductor which is amorphous or polycrystalline at the start of the process and which has been made into a single crystal by electron beam annealing, laser annealing, or another heat treatment, or a semiconductor formed by any method after the start of the process. CZ method, FZ
Wafers epitaxially grown on silicon wafers by the CVD method, MCZ method, etc., SOI substrates using these silicon wafers, etc. also fall under the “first semiconductor substrate” and “second semiconductor substrate” of the present invention. Of course.

The "main electrode region of the transistor" means one of a source region and a drain region of the transistor. Since the source region and the drain region of a transistor are usually formed symmetrically, it is only a matter of how to call them the source region or the drain region of the transistor. The "connection part for electrically connecting the main electrode region of the transistor and the epitaxial capacitor" of the first invention is a capacitor contact plug connected to the main electrode region of the transistor, and connected to the capacitor contact plug. This is a connection portion having at least a first bonding layer and a second bonding layer.

As the dielectric material of the perovskite structure epitaxial capacitor used in the first invention, a thermally stable BaTiO ₃ -based single crystal material which does not contain a low melting point metal such as Pb or Bi as a component is suitable. I have. That is, in the composition formula represented by ABO ₃ , A mainly consists of Ba, and a part thereof may be replaced with at least one element of Sr or Ca. As B, Ti, Sn, Zr, Hf and the like and their solid solution systems, furthermore, Mg _1/3 Ta _2/3 , Mg _1/3 Nb _2/3 , Z
Composite compounds such as n _1/3 Nb _2/3 and Zn _1/3 Ta _2/3 and solid solution systems thereof can be used.

Further, as a base electrode layer (lower electrode layer or upper electrode layer) of the perovskite type epitaxial capacitor used in the first invention, thermally stable single crystal strontium ruthenate or single crystal strontium molybdate is also used. A perovskite-type conductive oxide is most suitable, and further, noble metals such as platinum, gold, palladium, iridium, rhodium, rhenium, ruthenium, alloys thereof, and oxides thereof can be used. The lower electrode layer may be epitaxially grown after a barrier metal layer or the like is appropriately formed on the semiconductor substrate. The base electrode layer is a single crystal thin film, and the base electrode layer c
The axis is set to be perpendicular to the film surface.
It is preferable to select the composition so that the axial lattice constant is sufficiently smaller than that of the perovskite-type dielectric thin film layer. In this way, by utilizing the stress caused by the lattice constant mismatch between the base electrode layer and the dielectric thin film layer,
This is because the ferroelectric Curie temperature can be shifted to a higher temperature side to realize the ferroelectric characteristics at room temperature and the paraelectric characteristics having a high dielectric constant.

Therefore, by selecting the composition of the dielectric thin film layer, the ferroelectric thin film layer and the paraelectric thin film layer can be arbitrarily selected, so that both FRAM and DRAM can be realized. For example, the composition of Ba is 0.6-1.0, preferably 0.6.
By using a single crystal BSTO having a Ba-rich composition of about −0.9, the FRAM has an Sr composition of 0.6-0.
A DRAM can be realized by using a single crystal BSTO having an Sr-rich composition of about 9.

According to the first invention, the diameter is 200 mm
Since a silicon wafer (semiconductor substrate) of (8 inches) to 300 mm (12 inches) or more can be used, a semiconductor storage device (semiconductor memory) having a large capacity of gigabit or more and a low unit price can be realized.

According to a second aspect of the present invention, a transistor is formed on a first substrate, and the uppermost layer is planarized to form a substrate surface; Forming a first bonding layer;
Forming a multilayer structure for a capacitor comprising at least a first electrode layer, a dielectric thin film layer, and a second electrode layer on a second substrate by epitaxial growth; and forming a flat second bonding layer for the capacitor on the second substrate. Forming a step on the entire surface of the multilayer structure; abutting the first bonding layer and the second bonding layer to bond the first substrate and the second substrate to each other; A method of manufacturing a semiconductor memory device including at least a step of forming a capacitor for each cell by separating a multilayer structure for a capacitor and first and second bonding layers into a plurality of patterns later. Here, the “first substrate” and the “second substrate”
A substrate obtained by a bulk single crystal growth method by the CZ method, the FZ method, the MCZ method, or the like as defined in the first invention is preferable. In particular, the “second substrate” is preferably a substrate having high conductivity. From the viewpoint of increasing the diameter, the “first substrate” and the “second substrate” are preferably a semiconductor substrate, particularly a silicon substrate. Further, “a main electrode region of a transistor” means one of a source region and a drain region of a transistor.

In the second invention, the first bonding layer formed on the first substrate and the second bonding layer formed on the second substrate are both uniform over the entire surface of the wafer. Since the wafer is formed flat, it can be bonded uniformly over the entire surface of the wafer, and highly reliable bonding can be achieved. The main electrode region of the transistor and the capacitor of each cell are electrically connected one to one. The connection for electrical connection is formed by a capacitor contact plug connected to the main electrode region of the transistor, and a first bonding layer and a second bonding layer connected to the capacitor contact plug. What is necessary is just to comprise. Therefore, these bonding layers need to be made of metal or semiconductor with low resistivity. Alternatively, the first bonding layer is made of silicon, the second bonding layer is made of metal (or the first bonding layer is made of metal, and the second bonding layer is made of silicon), and then silicide is formed. Is also good. In any case, it is required at least that the first and second bonding layers after bonding are conductors.

Compared to the photolithography process including a series of steps such as exposure, development, and rinsing, the bonding process including the steps of holding, bonding, pressing, and heat-treating the two substrates is far more difficult. This is a process where alignment accuracy is difficult to obtain. The first flange (first bonding layer) connected to the main electrode region of the transistor and the second flange (second bonding layer) connected to the electrode layer of the capacitor for each cell are patterned in advance. Therefore, it is extremely difficult to mechanically bond the first substrate and the second substrate while paying attention to the fact that these flange patterns fit over the entire surface of the wafer with submicron to nanometer level accuracy. is there. In the second invention, after the first and second bonding layers are formed uniformly over the entire surface of the wafer, the first and second bonding layers are abutted, and the first and second substrates are bonded to each other. Since the multilayer structure for capacitors and the first and second bonding layers are separated by etching after bonding to each other to form capacitors for each cell, such submicron to nanometer level alignment accuracy is unnecessary. It is. In other words, after the first and second bonding layers are bonded, mask alignment may be performed by photolithography according to the pattern on the first substrate on which the transistor is formed, and patterning for capacitor isolation may be performed. The process is simplified. This is because the photolithography process has a higher degree of technical perfection and higher accuracy than the bonding process. In addition, since the relative positional relationship between the capacitor and the main electrode region of the transistor for each cell is determined after bonding to the first and second substrates, a slight misalignment can be covered in a subsequent photolithography process. Because.

The dielectric material of the perovskite structure epitaxial capacitor used in the second invention is the first dielectric material.
As described in the invention, a thermally stable BaTiO ₃ single crystal material which does not contain a low melting point metal such as Pb or Bi is suitable.

As a base electrode layer (lower electrode layer) of the perovskite structure epitaxial capacitor used in the second invention, a perovskite conductive material such as single crystal strontium ruthenate or single crystal strontium molybdate, which is also thermally stable. An oxide is optimal, and noble metals such as platinum, gold, palladium, iridium, rhodium, rhenium, ruthenium, alloys thereof, and oxides thereof can be used. The lower electrode layer may be epitaxially grown after a barrier metal layer or the like is appropriately formed on the substrate. The base electrode layer is a single crystal thin film, and the c-axis of the base electrode layer is perpendicular to the film surface. It is preferable to select the composition so as to be small. In this way, the ferroelectric Curie temperature is shifted to a higher temperature side by utilizing the stress caused by the lattice constant mismatch between the base electrode layer and the dielectric thin film layer, thereby realizing the ferroelectric characteristics at room temperature. Also, it is possible to realize paraelectric characteristics having a high dielectric constant. Therefore, by selecting the composition of the dielectric thin film layer, the ferroelectric thin film layer and the paraelectric thin film layer can be arbitrarily selected, so that both FRAM and DRAM can be realized.

In order to bond the first substrate and the second substrate at a temperature as low as possible, it is necessary to devise materials for the first and second bonding layers and a bonding method. For example, a system in which the material of the first bonding layer and the material of the second bonding layer are alloyed may be selected, and the reaction energy at the time of alloying may be used for bonding. Lowering the bonding temperature by selecting a system in which the first or second bonding layer is made of a different metal or semiconductor and forms an alloy layer between both bonding layers on an equilibrium diagram. Can be. In a system for forming an alloy layer, the free energy is lower when an alloy is formed, so that the alloying process promotes the bonding process. Further, by alloying, it is possible to increase the melting point and the mechanical strength as compared with the original metal. The system for forming an alloy may be a metal or a combination of a metal and a semiconductor for forming silicide such as nickel and silicon.

Further, Al—Ta, Al
-Cu, Al-Au, Al-Mg, Ti-Co, Ti-
Ni, Ti-Cu, Si-Mn, Si-Pd, Si-P
An amorphous metal (amorphous metal) such as t, Si-Ag or Si-Au may be used, and may be crystallized at the time of bonding, and the energy of crystallization may be used for bonding.
By selecting an amorphous metal or semiconductor for at least one of the first and second bonding layers, the bonding temperature can be lowered. This is because the crystallization process promotes the bonding process because the free energy is lower when the film is amorphous than when it is amorphous.

Further, as a device of the bonding method,
(B) bonding the bonded layer without forming it in the air after forming the bonded layer in a vacuum device; (b) physically cleaning the bonded surface by sputtering or the like in an inert gas;
It is desirable to employ a method of reducing the oxide on the surface by annealing in a reducing atmosphere such as hydrogen to chemically clean the metal surface by exposing the metal surface. When reducing with hydrogen or the like, it is necessary to use a metal layer or a semiconductor layer that can be reduced thermodynamically by examining the free energy of oxide formation.
After the step of cleaning the surface of (b) or (c), it is desirable to carry out the bonding step without exposing it to the atmosphere. In the second invention, after the first and second bonding layers are formed uniformly over the entire surface of the wafer, the first and second bonding layers are formed.
And the second substrate are bonded to each other, and then the capacitors for each cell are separated and
Since it is formed, the first and second substrates can be easily attached to each other without being exposed to the air in a vacuum device. This is because a slight misalignment can be covered in the subsequent photolithography process.

In the method for manufacturing a semiconductor memory device according to the second invention, the step of forming a transistor on the first substrate is first. Taking the case of a silicon substrate as an example, the process temperature of the step of forming a transistor is about 1000 ° C.
Which is the highest compared to other processes. Thereafter, a step of forming a multilayer structure for a capacitor and a step of abutting the first bonding layer and the second bonding layer to bond the first substrate and the second substrate to each other are performed. No extra heat energy is given to the multilayer structure for the capacitor, and the temperature of the whole process can be reduced.

According to the second aspect of the present invention, it is possible to use a substrate such as a silicon substrate having a large diameter, so that it is suitable for mass production and the manufacturing cost per chip is reduced.

According to a third aspect of the present invention, a transistor is formed on a first substrate, and the uppermost layer is planarized to form a substrate surface; Forming a first bonding layer;
Forming a flat second bonding layer over the entire surface of the second substrate; abutting the first bonding layer and the second bonding layer to form a first substrate and a second substrate; Bonding the first electrode layer and the dielectric thin film layer on the second substrate by epitaxial growth. Forming at least a part of a multilayer structure for a capacitor comprising at least a second electrode layer; and forming at least a part of the multilayer structure for a capacitor, a second substrate, and first and second bonding layers into a plurality of patterns. A method of manufacturing a semiconductor memory device including at least a step of separating the capacitors into capacitors for each cell. here,
The “first substrate” and the “second substrate” are preferably substrates obtained by a bulk single crystal growth method such as the CZ method, the FZ method, and the MCZ method as defined in the first invention.
In particular, the “second substrate” is preferably a substrate having high conductivity. From the viewpoint of increasing the diameter, the “first substrate” and the “second substrate” are preferably a semiconductor substrate, particularly a silicon substrate. Further, “a main electrode region of a transistor” means one of a source region and a drain region of a transistor. The “step of forming at least a part of the multilayer structure for a capacitor including the first electrode layer, the dielectric thin film layer, and the second electrode layer” may be, for example, a step of laminating only the first electrode layer. , The first electrode layer, the dielectric thin film layer and the second
This means that a process of laminating all of the electrode layers may be used. In any case, ultimately, this multilayer structure for a capacitor is composed of at least a first electrode layer, a dielectric thin film layer and a second electrode layer. Not all layers of these multilayer structures need to be separated in order to do so. If at least either the first electrode layer or the second electrode layer is separated for each cell, it can behave as an electrically independent capacitor. Therefore, the “step of separating at least a part of the multilayer structure for a capacitor, the second substrate, and the first and second bonding layers into a plurality of patterns to enable separation into capacitors for each cell” includes at least a first step. It should be understood as separating either the first electrode layer or the second electrode layer, and the second substrate and the first and second bonding layers. In the method for manufacturing a semiconductor memory device according to the third invention, the first
In a combination (time series) such that the first electrode layer is separated, and then the dielectric thin film layer and the second electrode layer are epitaxially grown.
Finally, a multilayer structure for a capacitor may be formed. That is, when a multilayer structure for a capacitor including at least a first electrode layer, a dielectric thin film layer, and a second electrode layer is formed on a second substrate by epitaxial growth, the epitaxial growth does not necessarily need to be a series of steps. Instead, it is also possible to configure it with two steps, and to interpose other processes between them. The upper electrode layer does not necessarily need to be formed by epitaxial growth.

Comparing the temperatures of the transistor formation, the formation of the capacitor multilayer structure, and the bonding process, the process temperature of the transistor formation is the highest. Taking the case of a silicon substrate as an example, the process temperature in the step of forming a transistor is about 1000 ° C. Therefore, as a sequence of steps, a method in which a transistor is formed on the first substrate shown in the second invention, a multilayer structure for a capacitor is formed on the second substrate, and the first and second substrates are bonded to each other. It is preferable that a transistor is formed on the first substrate of the third invention, the first substrate and the second substrate are bonded and polished, and then a multilayer structure for a capacitor is formed.

In the third invention, the first bonding layer formed on the first substrate and the second bonding layer formed on the second substrate are both uniform over the entire surface of the wafer. Since the wafer is formed flat, it can be bonded uniformly over the entire surface of the wafer, and highly reliable bonding can be achieved. A connection portion for electrically connecting the main electrode region of the transistor and the capacitor of each cell one-to-one is connected to the capacitor contact plug portion connected to the main electrode region of the transistor and the capacitor contact plug portion. It is composed of a first bonding layer and a second bonding layer. Therefore, these bonding layers need to be made of metal or semiconductor with low resistivity. Alternatively, the first bonding layer is made of silicon, the second bonding layer is made of metal (or the first bonding layer is made of metal, and the second bonding layer is made of silicon), and then silicide is formed. Is also good.

In the third invention, the first and second bonding layers are formed uniformly over the entire surface of the wafer, and then the first and second bonding layers are abutted to form the first and second bonding layers. The substrate and the substrate are adhered to each other, and then at least a part of the multilayer structure for a capacitor is formed. Since the capacitor is formed, positioning accuracy of a submicron to nanometer level is not required at the time of bonding. This is because, after bonding to the first and second substrates, the relative positional relationship between the capacitor and the main electrode region of the transistor for each cell is determined. In other words, after bonding, a multilayer structure for capacitors is formed, and mask matching is performed by a photolithography process according to the pattern on the first substrate on which the transistor is formed, and patterning for capacitor separation is performed. The time alignment process is simplified. A slight misalignment does not affect the subsequent photolithography process at all.

As the dielectric material of the perovskite structure epitaxial capacitor used in the third invention, the BaTiO ₃ single crystal material already described in the first invention is suitable. Further, as the base electrode layer (lower electrode layer) of the perovskite structure epitaxial capacitor used in the third invention, a thermally stable perovskite-type conductive oxide such as single-crystal strontium ruthenate or single-crystal strontium molybdate is optimal. And platinum,
Precious metals such as gold, palladium, iridium, rhodium, rhenium, ruthenium, and alloys and oxides thereof can be used. The lower electrode layer may be epitaxially grown after a barrier metal layer or the like is appropriately formed on the substrate. The base electrode layer is a single crystal thin film, and the c-axis of the base electrode layer is perpendicular to the film surface. It is preferable to select the composition so as to be small. In this way, the ferroelectric Curie temperature is shifted to a higher temperature side by utilizing the stress caused by the lattice constant mismatch between the base electrode layer and the dielectric thin film layer, thereby realizing the ferroelectric characteristics at room temperature. And
This is because paraelectric characteristics having a high dielectric constant can be realized. Therefore, by selecting the composition of the dielectric thin film layer, the ferroelectric thin film layer and the paraelectric thin film layer can be arbitrarily selected, so that both FRAM and DRAM can be realized.
In the above description, "the upper electrode layer does not necessarily need to be formed by epitaxial growth." This is because the lattice constant of the lower electrode layer in the a-axis and b-axis directions is sufficiently smaller than that of the dielectric thin film layer. That is, if a mismatch in lattice constant occurs between the lower electrode layer and the dielectric thin film layer, desired ferroelectric characteristics and high dielectric characteristics can be obtained.

In order to bond the first substrate and the second substrate at a temperature as low as possible, it is necessary to devise materials for the first and second bonding layers and methods of bonding.
For example, a system in which the material of the first bonding layer and the material of the second bonding layer are alloyed may be selected, and the reaction energy at the time of alloying may be used for bonding. 1st or 2nd
Is made of a different metal or semiconductor, and by selecting a system for forming an alloy layer between the two bonding layers on the equilibrium diagram, the bonding temperature can be lowered. In a system for forming an alloy layer, the free energy is lower when an alloy is formed, so that the alloying process promotes the bonding process. Further, by alloying, it is possible to increase the melting point and the mechanical strength as compared with the original metal. The system for forming an alloy may be a metal or a combination of a metal and a semiconductor for forming silicide such as nickel and silicon.

Further, an amorphous metal (amorphous metal) such as Al-Ta may be used as the bonding layer, and may be crystallized at the time of bonding to use the energy of crystallization for bonding. By selecting an amorphous metal or semiconductor for at least one of the first and second bonding layers, the bonding temperature can be reduced. This is because the crystallization process promotes the bonding process because the free energy is lower when the film is amorphous than when it is amorphous.

Further, the bonding method may be devised as follows: (1) After forming the bonding layer, the bonding is performed while keeping the clean surface without being exposed to the air; (2) Before bonding, the first or the second If the surface of the metal (or semiconductor) constituting the bonding layer is cleaned, the bonding temperature can be lowered. As a cleaning method, a physical method such as sputtering in an inert gas or a chemical method such as annealing in a reducing atmosphere such as hydrogen to reduce a surface oxide layer can be used. . When reducing with hydrogen or the like, it is necessary to use a metal layer or a semiconductor layer that can be reduced thermodynamically by examining the free energy of oxide formation. After the step of cleaning the surface, it is preferable to bond together without exposing it to the air. In the third invention, the first
When the substrate and the second substrate are bonded to each other, positioning accuracy at a submicron to nanometer level is not required, and therefore, it is easy to bond the first and second substrates together in a vacuum apparatus.

According to the third aspect of the present invention, it is possible to use a substrate such as a large-diameter silicon wafer.
It is suitable for mass production and the manufacturing cost per chip is reduced. The third invention of the present invention has many advantages almost in common with the second invention. In addition to these, it is also possible to form a three-dimensional capacitor cell using a U-shaped or V-shaped groove or the like. Since it is possible, the occupied area of the capacitor can be further reduced. In this case, for example, after bonding the first and second substrates, a U-shaped or V-shaped groove is formed, a first electrode layer is epitaxially grown in the groove, and then the first electrode layer is formed. And then performing a step of epitaxially growing the dielectric thin film layer and the second electrode layer.

[0059]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar parts are denoted by the same or similar reference numerals. However,
The drawings are schematic, the relationship between thickness and plane dimensions,
It should be noted that the ratio of the thickness of each layer is different from the actual one. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.

As described above, from the viewpoint of mass production of semiconductor memory devices, the first and second substrates to be bonded to each other are required to be semiconductor substrates. Before describing the semiconductor memory device according to the embodiment of the present invention, first, a structure using the first and second semiconductor substrates, which was preliminarily studied by the present inventors, will be described with reference to FIGS. State.

FIGS. 40 (a) and 40 (b) are cross-sectional views which are orthogonal to each other. That is, FIG.
FIG. 40 (b) is a cross-sectional view as viewed from the AA direction of (a), and FIG. 40 is a cross-sectional view as viewed from the BB direction of FIG. 40 (b).
(A). As shown in FIG. 40, a plurality of MOS transistors separated from each other by an element isolation region 13 made of a buried oxide film called an STI region are formed on a silicon substrate 11.
Are arranged in a matrix on the surface of a p-well 12 formed thereon. The MOS transistor in FIG.
Gate oxide film 29 and gate electrode 3 on the surface of well 12
7. Source region 21 composed of n ⁺ region in p well 12
And the drain region 22 and the like. Here, the gate electrode 37 forms a part of the word line.

A bit line 35 is formed on the drain region 22 via a bit line contact plug (not shown). A capacitor contact plug 31 made of polycrystalline silicon (doped polysilicon) doped with an impurity, a high melting point metal, or the like is connected to the n ⁺ source region 21. The capacitor contact plug 31 includes:
A first bonding layer 49 patterned in a rectangular flange shape is connected.

On the other hand, the epitaxial capacitors (56,
55, 54, 53, 52) are upper barrier metal layers 56, S
Upper electrode layer 55 such as RO, dielectric thin film layer 5 such as BSTO
4. Lower electrode layer 53 such as SRO, lower barrier metal layer 52
It is composed of A second bonding layer 57 having a flange shape corresponding to the first bonding layer 49 is connected to the upper barrier metal layer 56. As a result, the capacitor contact plug 31, the first bonding layer 49, and the second
N ⁺ source region 21 and epitaxial capacitors (56, 55, 54, 53, 52)
And are electrically connected.

The semiconductor memory device shown in FIG. 40 has a flange (first bonding layer) 49 on the silicon substrate 11 side and a flange (second bonding layer) 57 on the silicon substrate 51 side.
Are brought into contact with each other to realize a direct bonding (SDB) substrate between the silicon substrate 11 and the silicon substrate 51. In FIG. 40, reference numerals 32, 33, 34, 36, and 37 indicate insulating films. The first bonding layer 49 is arranged one for each memory cell, and is patterned into a rectangle separated by an insulating film 48. Similarly, the second bonding layer 57, the upper barrier metal layer 56, and the upper electrode layer 55 are also arranged one by one in each memory cell, and have a rectangular pattern separated by the capacitor isolation insulating film 58. That is, the second bonding layer 57 is formed as a flange corresponding to the first bonding layer 49, and the two flanges 49 and 57 are abutted to realize electrical connection.

The semiconductor memory device shown in FIG. 40 was manufactured through the steps shown in FIGS. 38 and 39.

First, as shown in FIG. 38, a first silicon (100) substrate 11
^A transistor including a ⁺ source region 21, an n ⁺ drain region 22, a gate oxide film 29, and a word line 37, an element isolation insulating film 13, a bit line 35, and a capacitor contact plug 31 are formed, and then chemically and mechanically polished ( CM
P) and the like. Next, after an Al film is formed on the entire surface as a first bonding layer 49 on the entire surface, patterning is performed for each contact plug, and an insulating film 48 is buried by a plasma CVD method or the like using TEOS gas as a raw material. It was flattened by a method or the like.

Next, as shown in FIG. 39, a 10 nm-thick (Ti, Al) N film as a lower barrier metal layer 52 and a 20 nm-thick SrRuO film as a lower electrode layer 53 are formed on a second silicon (100) substrate 51. _3. a 20 nm thick BSTO thin film having a Ba mole fraction of 70% as the dielectric thin film layer 54;
A 20 nm thick SrRuO ₃ film as the upper electrode layer 55,
Further, a 10 nm-thick (T
i, Al) N at RF or DC at a substrate temperature of 600 ° C.
Epitaxial growth was carried out continuously without being exposed to the atmosphere by sputtering. Next, the second bonding layer 5 is formed on the surface.
After forming an Al film on the entire surface as No. 7, a groove was formed so as to be separated into electrode layers of respective capacitors corresponding to the respective memory cells. Then, TEO is inserted into the trench for separating the capacitor.
After the capacitor isolation insulating film 58 was buried by a plasma CVD method or the like using S gas as a raw material, it was planarized again by a CMP method or the like.

Next, as shown in FIG. 40, the electrode layer (first bonding layer) 49 formed on the first silicon substrate 11 is formed.
And an electrode layer formed on the second silicon substrate 51 (second electrode layer).
The bonding layer 57 was aligned, and pressed and joined at 400 ° C. for 30 minutes.

According to the manufacturing process shown in FIGS. 38 to 40, since the two semiconductor substrates 11 and 51 are used, it is easy to increase the diameter and is suitable for mass production. However, as a result of inspecting the memory cell created by such a process, a large number of misalignments between the upper and lower electrode layers 49 and 57 occur. A leak current path is generated at the interface between the insulating layers 48 and 58 due to poor adhesion between the insulating layers 48 and 58 around the electrode layers 49 and 57, and a number of short-circuits with the electrode layers of adjacent memory cells occur. And many other problems arose.

Therefore, the problems of the semiconductor memory device shown in FIG. 40 were examined, and various considerations, simulations, and experiments were performed. Then, as a result of repeated trial and error and examination, the semiconductor memory device according to the embodiment as described below has been attained.

(First Embodiment) FIG. 1 is a sectional view of a semiconductor memory device according to a first embodiment of the present invention.
Here, FIG. 1A and FIG. 1B are cross-sectional views that are orthogonal to each other. That is, AA in FIG.
1B is a cross-sectional view as viewed from the direction, and FIG. 1A is a cross-sectional view as viewed from the BB direction in FIG. 1B. Also,
FIG. 2 is a corresponding plan view.

The semiconductor memory device according to the first embodiment of the present invention is an FRAM having an epitaxial capacitor using a BSTO thin film having a Ba mole fraction of 70% as a ferroelectric thin film layer. This semiconductor storage device (FRA
M) includes a first semiconductor substrate 11 in which a plurality of transistors are arranged in a matrix as shown in FIG. It includes at least a semiconductor substrate 51 and a connection part (31, 47, 59) for electrically connecting the main electrode region 21 of each transistor and the epitaxial capacitor 9 in one-to-one correspondence.

Then, as shown in FIG.
In the semiconductor memory device according to the embodiment, a plurality of MOS transistors separated from each other by an element isolation region 13 made of a buried oxide film called an STI region are formed on a silicon substrate 1.
1 are arranged in a matrix. This multiple M
The OS transistor is an nMOSFET formed on a surface of a p-well 12 formed on a silicon substrate 11. This nMOSFET has a source region 21 and a drain region 22 composed of an n ⁺ region in a p-well 12 as main electrode regions. Furthermore, this nMOSF
The ET has a gate electrode 37 on the gate oxide film 29 on the surface of the p-well 12 as a control electrode. Here, the gate electrode 37 forms a part of the word line. As shown in FIG. 2, there are a plurality of word lines 37, which extend in the vertical direction.

Also, as shown in FIG.
A bit line contact plug 39 made of polycrystalline silicon (doped polysilicon) doped with an impurity, a refractory metal or a silicide of a refractory metal is disposed thereon, and is connected to the bit line 35. The bit line 35 extends in a horizontal direction orthogonal to the word line 37. Although only one bit line 35 is shown in FIG. 2 for simplification, it goes without saying that an XY matrix is composed of a plurality of bit lines and a plurality of word lines.

As shown in FIG. 1, a capacitor contact plug 31 made of doped polysilicon, a refractory metal, a silicide of a refractory metal, or the like is provided in the n ⁺ source region 21.
Is connected. A first bonding layer 47 having the same plane pattern as that of the rectangular capacitor section 9 shown in FIG. 2 is connected to the capacitor contact plug 31.

On the other hand, the epitaxial capacitor (capacitor portion) 9 includes an upper barrier metal layer 56, an upper electrode layer 55 such as SRO, a dielectric thin film layer 54 such as BSTO having a mole fraction of Ba of 70%, and a lower electrode layer such as SRO. 53 and a lower barrier metal layer 52. Second silicon substrate 5
Reference numeral 1 denotes a silicon substrate having a high impurity density of about 2 × 10 ^{18 to} 1 × 10 ²⁰ cm ⁻³ . The lower barrier metal layer 5 is formed via the second silicon substrate 51 having a high impurity density.
2 is connected to a plate electrode 62 such as a Ti / TiN / Al layer. Further, a passivation insulating film 65 such as an oxide film (SiO ₂ film), a PSG film, a BPSG film, a nitride film (Si ₃ N ₄ film), or a polyimide film is formed on the plate electrode 62. Then, a second bonding layer 59 having the same plane pattern as that of the rectangular capacitor section 9 shown in FIG. 2 is connected to the upper barrier metal layer 56. As a result, the capacitor contact plug 3
1. The first bonding layer 47 and the second bonding layer 59 electrically connect the n ⁺ source region 21 and the epitaxial capacitor (capacitor portion) 9. In FIG. 1, reference numerals 32, 33, 34, 36, and 37 denote insulating films such as an oxide film (SiO ₂ film), a PSG film, a BPSG film, or a nitride film (Si ₃ N ₄ film).

Next, a method of manufacturing the semiconductor memory device according to the first embodiment of the present invention will be described with reference to the following schematic cross-sectional views in the order of steps (FIGS. 3 to 11). FIGS. 3A to 11B are cross-sectional views orthogonal to each other in FIGS. That is, the cross-sectional view as viewed from the AA direction in FIG. (A) is FIG. (B), and the cross-sectional view as viewed from the BB direction in FIG. (B) is (a).

(A) First, as shown in FIG. 3, an n ⁺ source region 21, an n ⁺ drain region 22, and a gate oxide film 29 are formed on a first silicon (100) substrate 11 by using a known process. , A transistor including the word line 37,
The inter-element isolation insulating film 13, the bit line 37, and the capacitor contact plug 31 are formed, and the uppermost layer is flattened by a method such as chemical mechanical polishing (CMP) to form a substrate surface.

(B) Next, a flat Al film is formed as a first bonding layer 47 on the entire surface of the substrate. At this time, the flat first bonding layer 47 is connected to the n ⁺ source region 21 serving as the main electrode region of the transistor of the present invention by the capacitor contact plug 31.

(C) Next, as shown in FIG. 4, on the second silicon (100) substrate 51, a (Ti, Al) N film having a thickness of 10 nm is formed as a lower barrier metal layer 52, and a lower electrode layer (first layer) is formed. 20 nm thick SrRuO ₃ ,
The dielectric thin film layer 54 has a thickness of 2 with a mole fraction of Ba of 70%.
0 nm BSTO thin film, upper electrode layer (second electrode layer) 5
5, a 20 nm thick SrRuO ₃ film, and a 10 nm thick (Ti, Al) N film as the upper barrier metal layer 56.
Is formed. This multilayer structure for capacitors can be used at RF
It suffices that the epitaxial growth be carried out continuously without being exposed to the atmosphere by a sputtering method.

(D) Next, as shown in FIG. 4, as the second bonding layer 59, a flat Al film is formed on the entire surface of the multilayer structure for capacitors.

(E) Next, as shown in FIG. 5, the oxide layers formed on the surfaces of the first bonding layer 47 and the second bonding layer 59 are separated by a pressure of 4 × 10 ⁻⁶ Pa or less. A in ultra high vacuum
A new surface of Al is obtained by removing by sputtering of r gas. When the new surface of Al is exposed, the first bonding layer 47 and the second bonding layer 59 are butted to each other without being exposed to the air, and are pressed at 400 ° C. for 30 minutes. The silicon substrate 51 is bonded.

(F) Next, as shown in FIG. 6, the bonded second silicon substrate 51 is polished from the back surface by CMP or the like to leave the capacitor layer and the silicon substrate at about 0.2 μm.

(G) Thereafter, alignment is performed with reference to the transistor pattern formed on the first silicon substrate. That is, a photolithography technique is used to form a photoresist separation mask pattern. Using this separation mask pattern as an etching mask, a capacitor for each memory cell is patterned by a separation groove 91 as shown in FIG. The etching mask may be a multilayer film such as a photoresist and an oxide film,
Other mask materials may be used. FIG. 8 is a corresponding plan view. A rectangular pattern serving as a pattern of the capacitor portion is formed in an island shape corresponding to each memory cell. The alignment may be performed using the alignment mark used when forming the transistor on the first silicon substrate, or may be adjusted by focusing on the actual transistor pattern. A new alignment mark may be formed after bonding. In order to form the separation groove 91, reactive ion etching (RIE) or the like may be used. As an etching condition at this time, it is preferable to use the oxide layer 33 as an etching stop layer.

(H) Further, as shown in FIG. 9, after an insulating film (capacitor isolation insulating film) 61 is buried by a plasma CVD method or the like using TEOS gas as a raw material, as shown in FIG. Become

(I) Next, as shown in FIG. 11, a Ti / TiN / Al layer was formed as the plate electrode layer 62, and FIG.
Oxide film (SiO ₂ film), PSG film, BPS
A passivation insulating film 65 such as a G film, a nitride film (Si ₃ N ₄ film), or a polyimide film is covered.

By such a process, a memory cell comprising an epitaxial capacitor and a transistor using a ferroelectric thin film layer having a perovskite structure can be manufactured with high yield, and a favorable and highly reliable operation as an FRAM has been confirmed. Was done.

In the method for manufacturing a semiconductor memory device according to the first embodiment of the present invention, the first and second silicon substrates 11 and 51 are bonded to each other, and then, in a photolithography step, each cell is manufactured. Separate capacitor
Since it is formed, there is essentially no problem of misalignment between the upper and lower first bonding layers 47 and the second bonding layer 59.
Further, the first bonding layer 4 is formed on a flat surface formed on the entire surface.
7 and the second bonding layer 59 are bonded, so that a good bonding interface is obtained, and no open failure occurs. Furthermore, since a new insulating film (capacitor separating insulating film) 61 is buried in the separation groove 91 around the junction between the first bonding layer 47 and the second bonding layer 59 by a plasma CVD method or the like, There is no possibility that a leakage current path is generated. Therefore, there is no possibility of a leak current or a short circuit between the first and second bonding layers 47 and 59 of the adjacent memory cells.

In order to expose the nascent surface of Al in the ultra-high vacuum in the step (e) and to join the first silicon substrate 11 and the second silicon substrate 51 without exposing them to the air as they are, An apparatus as shown in FIG. 41 may be used. In FIG. 41, the film forming chamber 1 and the pressure bonding chamber 3 are connected to each other via a gate valve not shown. Further, the film forming chamber 1 and the pressure bonding chamber 3 are connected to an ultra-high vacuum vacuum pump such as a cryopump or a turbo pump (not shown) so that the chamber can be evacuated to an ultra-high vacuum having a pressure of 4 × 10 ⁻⁶ Pa or less. Has become. A cassette 5 capable of holding a plurality of silicon substrates, a stage 5 having a heater on which a first silicon substrate 11 and a second silicon substrate 51 are mounted and which can be heated to a predetermined temperature, and a first A press 4 and the like for pressing the silicon substrate 11 and the second silicon substrate 51 together with a predetermined pressure are provided. A vacuum preparation chamber is connected to the film formation chamber 1 via another gate valve not shown, so that the first silicon substrate 11 and the second silicon substrate 51 can be transferred from the vacuum preparation chamber by an air lock. ing. In the film forming chamber 1, the first bonded layer 47 and the second
An Al target is prepared so that Al as the bonding layer 59 can be deposited by sputtering. Further, the wafer holder on which the first silicon substrate 11 and the second silicon substrate 51 are mounted can be switched between a ground (ground) level and a high voltage level. Therefore, the polarity is switched immediately after the first bonding layer 47 and the second bonding layer 59 are deposited by sputtering, and the first bonding layer 47 and the second bonding layer 59 are generated on the surfaces of the first bonding layer 47 and the second bonding layer 59. The oxidized layer can be removed by sputtering of Ar gas in an ultra-high vacuum at a pressure of 4 × 10 ⁻⁶ Pa or less, and a new Al surface can be obtained. Of course, the first bonding layer 47
(Chamber) for depositing the second bonding layer 59 and the second bonding layer 59
And a room (chamber) for removing an oxide layer generated on the surface of the first bonding layer 47 and the second bonding layer 59 by sputtering, respectively, so that they can be transported in a vacuum. Is also good. In any case, when a new surface of Al is exposed by sputtering, the gate valve is opened, and the first silicon substrate 11 and the second silicon substrate 51 are vacuum-transferred to the crimping chamber 3. Specifically, first, a plurality of first silicon substrates 11 are vacuum-transferred to the crimping chamber 3, temporarily held in a cassette in the crimping chamber 3, and then the second silicon substrate 51 is vacuum-transferred to the crimping chamber 3. The procedure to do is good. In the crimping chamber 3, the first silicon substrate 11 and the second silicon substrate 51 are mounted on the stage 5, and press-bonded with a press 4 at a predetermined pressure at 400 ° C. for 30 minutes to perform bonding (direct bonding). In the method for manufacturing a semiconductor memory device according to the first embodiment of the present invention, the first and second
Are bonded to each other, and then the capacitors for each cell are separated and formed in a photolithography process. Therefore, after the first and second silicon substrates are bonded, the capacitor for each cell and the main electrode of the transistor are formed. The relative positional relationship with the area is determined. Therefore, a slight misalignment between the first and second silicon substrates is allowed. In other words, a semiconductor memory device having a positioning accuracy that is high enough to match the outer peripheral positions of the first and second silicon substrates, and having a gigabit-class fine pattern, has a submicron to nanometer size relative to the transistor pattern. It is not necessary to mechanically bond the first silicon substrate and the second silicon substrate while paying attention to the level of accuracy. For this reason, positioning and bonding can be performed with a simple apparatus configuration as shown in FIG. 41, and since a complicated apparatus does not enter the vacuum chamber, the degassing component with respect to vacuum is reduced, and the pressure is 4 × 1.
An ultra-high vacuum of 0 ⁻⁶ Pa or less can be easily achieved. Therefore, more reliable bonding between the first bonding layer 47 and the second bonding layer 59 can be realized, and as a result, the performance and reliability of the semiconductor memory device can be improved.

FIG. 12 is a schematic cross-sectional view of an SOI / FRAM memory cell according to a modification of the first embodiment of the present invention. S according to a modification of the first embodiment of the present invention.
The OI-FRAM is an SOI-FRAM having an epitaxial capacitor using a Ba-rich BSTO thin film layer (ferroelectric thin film layer). This semiconductor memory device (F
As shown in FIG. 12, a plurality of transistors are arranged in a matrix on an SOI substrate (10, 14, 15). The SOI substrates (10, 14, 15) include a first silicon substrate 10 serving as a support substrate, a buried insulating film 14 on the first silicon substrate 10, and an SOI film 15 on the buried insulating film 14. It is configured. S
The OI substrates (10, 14, 15) are formed by direct bonding (SDB).
Method, a SIMOX method, an epitaxial growth method, or the like. The SOI-FRAM memory cell according to the modification of the first embodiment of the present invention shown in FIG. 12 has a first silicon substrate 10 on which a plurality of transistors are arranged in a matrix and a plurality of A second silicon substrate 51 having a plurality of perovskite-type epitaxial capacitors 9 described above, and connection portions (31, 47) electrically connecting the respective main electrode regions 21 of the transistors and the epitaxial capacitors 9 in one-to-one correspondence. , 59). As described above, the “first silicon substrate” and the “second silicon substrate” of the present invention are obtained by the CZ method, the FZ method,
The method is not limited to only silicon substrates such as the CZ method, the MCZ method, etc., but also includes epitaxial wafers epitaxially grown on silicon wafers by the CZ method, the FZ method, the MCZ method, etc., and SOI substrates using these silicon wafers. It is a structural example for showing that it corresponds to the "first silicon substrate" and the "second silicon substrate" of the invention.

As shown in FIG. 12, in the SOI / FRAM memory cell according to the modification of the first embodiment of the present invention, a plurality of MOS transistors are formed by the STI region 13 reaching the buried insulating film 14. Are separated from each other. The plurality of MOS transistors are nMOSFETs formed on the surface of the p-type SOI film 15 on the buried insulating film 14. This nMOSFET is
The p-type SOI film 15 has, as main electrode regions, a source region 21 and a drain region 22 composed of an n ⁺ region. Further, this nMOSFET serves as a control electrode with p
A gate electrode 37 is provided on the gate oxide film 29 on the surface of the type SOI film 15. Here, the gate electrode 37 is
It forms part of a word line. A bit line contact plug (not shown) is disposed on the drain region 22 (see FIG. 2), and is connected to the bit line 35. The bit line 35 extends in a direction orthogonal to the word line 37.

As shown in FIG. 12, n ⁺ source region 21
Is connected to a capacitor contact plug 31. On the other hand, epitaxial capacitors (capacitor part)
9 is an upper barrier metal layer 56, an upper electrode layer 5 such as SRO
5, a dielectric thin film layer 54 of BSTO or the like having a mole fraction of Ba of 70%, a lower electrode layer 53 of SRO or the like, and a lower barrier metal layer 5
And 2. The second silicon substrate 51
The silicon substrate has a high impurity density of about 2 × 10 ^{18 to} 1 × 10 ²⁰ cm ⁻³ . The lower barrier metal layer 52 is formed via the second silicon substrate 51 having a high impurity density.
It is connected to a plate electrode 62 such as a Ti / TiN / Al layer. Further, a passivation insulating film 65 is formed on the plate electrode 62. The second bonding layer 59 is connected to the partial barrier metal layer 56. As a result, the capacitor contact plug 31, the first bonding layer 47 and the second bonding layer 59
N ⁺ source region 21 and epitaxial capacitor (capacitor portion) 9 are electrically connected. In FIG. 12, reference numerals 32, 33, 34, 36, and 37 denote oxide films (S
An insulating film such as an iO ₂ film), a PSG film, a BPSG film, or a nitride film (Si ₃ N ₄ film).

(Second Embodiment) FIGS. 13 and 14
2A and 2B are a cross-sectional view and a plan view of a semiconductor memory device according to a second embodiment of the present invention. The semiconductor memory device according to the second embodiment of the present invention is characterized in that BS having a mole fraction of Ba of 70% is used.
This is an FRAM having an epitaxial capacitor using a TO thin film as a ferroelectric thin film layer. FIG. 13A and FIG. 13B are cross-sectional views that are orthogonal to each other. That is, FIG. 13B is a cross-sectional view as viewed from the AA direction in FIG. 13A, and FIG. 13A is a cross-sectional view as viewed from the BB direction in FIG. 13B. FIG. 14 is a corresponding plan view.

This semiconductor memory device (FRAM) has the structure shown in FIG.
As shown in FIG. 3, a first semiconductor substrate 11 having a plurality of transistors arranged in a matrix, a second semiconductor substrate 64 having a plurality of perovskite-type epitaxial capacitors 9 corresponding to each of the plurality of transistors, At least connection portions (31, 47, 63, 64) for electrically connecting the respective main electrode regions 21 of the transistors and the epitaxial capacitors 9 in one-to-one correspondence are included.

As shown in FIG. 13, in the semiconductor memory device according to the second embodiment of the present invention, a plurality of MOS transistors separated from each other by an STI region (element isolation region) 13 They are arranged in a matrix above. The plurality of MOS transistors are nMOSFETs formed on the surface of a p-well 12 formed on a silicon substrate 11. This nMOSFET
Has a source region 21 and a drain region 22 composed of an n ⁺ region as a main electrode region in a p-well 12. Further, this nMOSFET serves as a control electrode with p
A gate electrode 37 is provided on the gate oxide film 29 on the surface of the well 12. Here, the gate electrode 37 forms a part of the word line. The word line 37 is
As shown in the figure, there are a plurality of them, which extend in the vertical direction.

Further, as shown in FIG.
A bit line contact plug 3 made of doped polysilicon, refractory metal or silicide of refractory metal is formed on
9 are arranged and connected to the bit line 35. The bit line 35 extends in a horizontal direction orthogonal to the word line 37. Although only one bit line 35 is shown in FIG. 14 for simplicity, it goes without saying that an XY matrix is composed of a plurality of bit lines and a plurality of word lines.

Further, as shown in FIG. 13, a capacitor contact plug 31 made of doped polysilicon, high melting point metal, silicide of high melting point metal or the like is connected to n ⁺ source region 21. A first bonding layer 47 having the same plane pattern as the rectangular capacitor section 9 shown in FIG. 14 is connected to the capacitor contact plug 31.

On the other hand, the epitaxial capacitor (capacitor portion) 9 includes a lower barrier metal layer 52, a lower electrode layer 53 such as SRO, a dielectric thin film layer 54 such as BSTO having a mole fraction of Ba of 70%, and an upper electrode layer such as SRO. 55 and an upper barrier metal layer 56. A plate electrode 62 such as a Ti / TiN / Al layer is connected to the upper barrier metal layer 56, and an oxide film (S
iO ₂ film), PSG film, BPSG film, nitride film (Si ₃ N)
₄ ) or a passivation insulating film 65 such as a polyimide film. Second silicon substrate 64
Is a silicon substrate having a high impurity density of about 2 × 10 ^{18 to} 1 × 10 ²⁰ cm ⁻³ . The lower barrier metal layer 52 is provided via the second silicon substrate 64 having a high impurity density.
Are connected to the second bonding layer 63. That is,
A multilayer structure including a lower barrier metal layer 52, a lower electrode layer 53, a dielectric thin film layer such as BSTO, an upper electrode layer 55, and an upper barrier metal layer 56;
4. The first and second bonding layers 47 and 63 are formed as shown in FIG.
Are formed separately in the same plane pattern as the rectangular capacitor section 9 shown in FIG. Then, the capacitor contact plug 31, the first bonding layer 47, the second bonding layer 63
And the second silicon substrate 64, the n ⁺ source region 2
1 and the epitaxial capacitor (capacitor section) 9 are electrically connected. In FIG.
2, 33, 34, 36, and 37 are oxide films (SiO ₂ films);
PSG film, BPSG film, or nitride film (Si ₃ N
₄ ).

Next, a method of manufacturing the semiconductor memory device according to the second embodiment of the present invention will be described with reference to the following schematic sectional views (FIGS. 3 and 15 to 22). In the following steps (a) and (b), the first bonding layer 47 is formed as A
Except that the Cu film is used instead of the 1 film, the method is basically the same as the method of manufacturing the semiconductor memory device according to the above-described first embodiment. The description will be made with reference to FIG. Note that FIG.
22A to 22B are cross-sectional views orthogonal to each other. That is, the cross-sectional view as viewed from the AA direction in FIG.
(A) is a cross-sectional view as viewed from the BB direction.

(A) First, as shown in FIG. 3, the n ⁺ source region 21 and the n ⁺ drain region 2 are formed on the first silicon (100) substrate 11 by using a known process.
2. A transistor including a gate oxide film 29 and a word line 37, an element isolation insulating film 13, a bit line 37, and a capacitor contact plug 31 are formed, and the uppermost layer is formed by a method such as chemical mechanical polishing (CMP). To obtain a substrate surface.

(B) Next, a flat Cu film is formed as a first bonding layer 47 on the entire surface of the substrate. At this time, the flat first bonding layer 47 is connected to the n ⁺ source region 21 serving as the main electrode region of the transistor of the present invention by the capacitor contact plug 31.

(C) Next, as shown in FIG. 15, a flat Cu film is formed as the second bonding layer 63 on the entire surface of the second silicon (100) substrate 64.

(D) Next, as shown in FIG. 16, the Cu film as the first bonding layer 47 and the second bonding layer 63 is
A reduction treatment in hydrogen at 400 ° C. is performed to reduce the Cu oxide layer on the surface.
Press for 30 minutes to join. By performing a reduction treatment on the surface of the Cu film, the first bonding layer 4 is not exposed to the air as it is.
In order to join the second bonding layer 63 to the second bonding layer 63, FIG.
An apparatus as shown in FIG.

(E) Next, as shown in FIG. 17, the bonded second silicon substrate 64 is thinned to a predetermined thickness. For example, the CMP from the back surface of the second silicon substrate 64
The second silicon substrate 64 is polished by 0.2 μm.
The thickness is reduced to about m.

(F) Next, as shown in FIG. 18, 10 nm thick (Ti, Al) N as the lower barrier metal layer 52 and 20 nm thick S as the lower electrode layer (first electrode layer) 53.
rRuO ₃ , the molar fraction of Ba being 7 as the dielectric thin film layer 54
0% and 20 nm thick BSTO thin film, upper electrode layer (second
A SrRuO ₃ film having a thickness of 20 nm as an electrode layer 55;
Further, a 10 nm-thick (T
i, Al) N at RF or DC at a substrate temperature of 600 ° C.
Continuous epitaxial growth is performed by sputtering without exposing to the atmosphere to form a multilayer structure for a capacitor.

(G) Next, as shown in FIG. 19, alignment is performed on the basis of the transistor pattern on the first silicon substrate 11, and a photoresist separation mask pattern is formed by photolithography. Using the separation mask pattern as an etching mask,
A separation groove 93 is formed. The etching mask may be a multilayer film such as a photoresist and an oxide film, or another mask material may be used. The isolation trench 93 separates the capacitor multilayer structures 52, 53, 54, 55, 56, the second silicon substrate 64, and the first and second bonding layers 47, 63 into a plurality of patterns. Each capacitor is formed. The alignment in the photolithography technique may be performed using an alignment mark used for forming a transistor on the first silicon substrate, or may be adjusted by focusing on an actual transistor pattern. A new alignment mark may be formed after bonding. In order to form the separation groove 93, reactive ion etching (RIE) or the like may be used. As an etching condition at this time, it is preferable to use the oxide layer 33 as an etching stop layer.

(H) Further, as shown in FIG.
The separation groove 93 is formed by a plasma CVD method using a gas as a raw material.
After the capacitor isolation insulating film 61 is buried, the surface is planarized again by the CMP method or the like as shown in FIG. afterwards,
As shown in FIG. 22, Ti / T
An iN / Al layer was formed, and as shown in FIG. 13, an oxide film (SiO ₂ film), a PSG film, a BPSG film, and a nitride film (Si
₃ N ₄ film) or a passivation insulating film 65 such as a polyimide film.

According to such a process, a memory cell including a capacitor and a transistor using a ferroelectric thin film layer can be manufactured with high yield, and a favorable and highly reliable operation as an FRAM has been confirmed.

In the method for manufacturing a semiconductor memory device according to the second embodiment of the present invention, the first and second silicon substrates 11 and 64 are bonded to each other, and then, in a photolithography step, each cell is formed. Separate capacitor
Since it is formed, there is essentially no problem of misalignment between the upper and lower first bonding layers 47 and the second bonding layer 63. Further, the first bonding layer 47 is formed on the flat surface formed on the entire surface.
Since the second bonding layer 63 is bonded to the second bonding layer 63, a good bonding interface is obtained, and no open failure occurs.
Further, the first bonding layer 47 and the second bonding layer 63
Since the insulating film (capacitor separating insulating film) 61 is newly buried in the separating groove 93 formed around the junction of
There is no possibility that a leakage current path is generated. Therefore, there is no possibility of a leak current or short circuit between the first and second bonding layers 47 and 63 of the adjacent memory cells.

FIG. 42 shows that the reduction process in hydrogen in the step (d) is performed to reduce the Cu oxide layer on the surface,
This shows an apparatus for joining the first silicon substrate 11 and the second silicon substrate 64 without exposing them to the air. In FIG. 42, the film formation chamber 1, the reduction chamber 2, and the reduction chamber 2 and the pressure bonding chamber 3 are connected to each other via a gate valve (not shown). Further, a film forming chamber 1 and a reduction chamber 2
The crimping chamber 3 is connected to an ultra-high vacuum vacuum pump such as a cryopump or a turbo pump (not shown).
It can be evacuated to an ultra-high vacuum of × 10 ^-6 Pa or less. The reduction chamber 2 is provided with a hydrogen gas inlet 7 for reduction processing, and can be controlled to a predetermined flow rate by a flow controller or the like. Further, a heater 6 is provided in the reduction chamber 2, and the first temperature is set to a predetermined temperature such as 400 ° C.
And the second silicon substrate 64 can be heated. Heating may be performed by infrared lamp heating or resistance heating, but infrared lamp heating can provide cleaner heating. A cassette 5 capable of holding a plurality of silicon substrates, a stage 5 having a heater on which the first silicon substrate 11 and the second silicon substrate 64 are mounted and which can be heated to a predetermined temperature, and a first A press 4 is provided for pressing the silicon substrate 11 and the second silicon substrate 64 together at a predetermined pressure. A vacuum preparation chamber is connected to the film formation chamber 1 via another gate valve not shown, and the first silicon substrate 11 and the second silicon substrate 64 can be transferred from the vacuum preparation chamber by an air lock. ing. The film forming chamber 1 includes a first bonding layer 4
7 and a Cu film as the second bonding layer 64 are formed by CVD,
It is configured so that it can be deposited by vacuum evaporation or sputtering. You may make it conveyable in a vacuum. After depositing the Cu film, the gate valve is opened, and the first silicon substrate 11 and the second silicon substrate 51 are transferred to the reduction chamber 2 by vacuum. In the reduction chamber 2, the Cu film serving as the first bonding layer 47 or the second bonding layer 63 is subjected to a reduction treatment in hydrogen at 400 ° C. for a predetermined time (for example, 10 to 30 minutes). When the reduction process is completed, the gate valve is opened, and the first silicon substrate 11 and the second silicon substrate 51 are opened.
Is transferred to the crimping chamber 3 by vacuum. Specifically, first, a plurality of first silicon substrates 11 are vacuum-transferred while sequentially processing the film formation chamber 1, the reduction chamber 2, and the compression chamber 3, and once held in a cassette in the compression chamber 3, A procedure may be employed in which the second silicon substrate 64 is vacuum-transferred while sequentially processing the film formation chamber 1, the reduction chamber 2, and the compression chamber 3 in the same manner. First, the second silicon substrate 64 is vacuum-transferred while sequentially processing the film formation chamber 1, the reduction chamber 2, and the compression chamber 3, and once held in a cassette in the compression chamber 3, and then the first silicon substrate 11 May be transferred by vacuum. In the crimping chamber 3, the first silicon substrate 11 and the second silicon substrate 64 are mounted on the stage 5,
Then, pressure bonding is performed at a predetermined pressure at 400 ° C. for 30 minutes to perform bonding (direct bonding). In the method for manufacturing a semiconductor memory device according to the second embodiment of the present invention, the first and second
Are bonded to each other, and then the capacitors for each cell are separated and formed in a photolithography process. Therefore, after the first and second silicon substrates are bonded, the capacitor for each cell and the main electrode of the transistor are formed. The relative positional relationship with the area is determined. Therefore, a slight misalignment between the first and second silicon substrates is allowed. That is, it is sufficient that the positioning accuracy is such that the outer peripheral positions of the first and second silicon substrates are aligned. For this reason, as shown in FIG. 42, since a complicated apparatus does not enter the vacuum chamber, the degassing component with respect to the vacuum is reduced, and an ultra-high vacuum with a pressure of 4 × 10 ⁻⁶ Pa or less can be easily achieved. . Therefore, the more reliable first bonding layer 4
7 and the second bonding layer 63 can be joined, and as a result, high performance and high reliability of the semiconductor memory device are achieved.

(Third Embodiment) A semiconductor memory device according to a third embodiment of the present invention is substantially the same as that of the second embodiment, except that a planar structure perovskite type epitaxial capacitor is used. In addition, the point that a three-dimensional structure perovskite type epitaxial capacitor was created
This is different from the semiconductor memory device according to the second embodiment.
Further, in the third embodiment, the B mole fraction of 70%
DR using a BSTO thin film (paraelectric thin film) having a mole fraction of Ba of 30% instead of the STO thin film (ferroelectric thin film)
AM, which is different from the FRAM according to the second embodiment.

FIGS. 23 and 24 are a sectional view and a plan view of a semiconductor memory device according to the third embodiment of the present invention. FIG. 23A and FIG. 23B are cross-sectional views that are orthogonal to each other. That is, A in FIG.
FIG. 23B is a cross-sectional view taken from the −A direction, and FIG.
FIG. 23A is a cross-sectional view taken along the line BB in FIG. FIG. 24 is a corresponding plan view.

This semiconductor memory device (DRAM) has the structure shown in FIG.
As shown in FIG. 3, a first silicon substrate 11 on which a plurality of transistors are arranged in a matrix, a second silicon substrate 64 having a plurality of perovskite-type epitaxial capacitors 9 corresponding to the plurality of transistors, Each main electrode region 21 of the transistor
And at least connection portions (31, 47, 63, 64) for electrically connecting the epitaxial capacitors 9 in one-to-one correspondence.

As shown in FIG. 23, in the semiconductor memory device according to the third embodiment of the present invention, a plurality of MOS transistors separated from each other by an STI region (element isolation region) 13 They are arranged in a matrix above. The plurality of MOS transistors are nMOSFETs formed on the surface of a p-well 12 formed on a silicon substrate 11. This nMOSFET
Has a source region 21 and a drain region 22 composed of an n ⁺ region as a main electrode region in a p-well 12. Further, this nMOSFET serves as a control electrode with p
A gate electrode 37 is provided on the gate oxide film 29 on the surface of the well 12. Here, the gate electrode 37 forms a part of the word line. The word line 37 is
As shown in the figure, there are a plurality of them, which extend in the vertical direction.

Further, as shown in FIG.
A bit line contact plug 3 made of doped polysilicon, refractory metal or silicide of refractory metal is formed on
9 are arranged and connected to the bit line 35. The bit line 35 extends in a horizontal direction orthogonal to the word line 37. Although only one bit line 35 is shown in FIG. 24 for simplification, it goes without saying that an XY matrix is composed of a plurality of bit lines and a plurality of word lines.

Further, as shown in FIG. 23, a capacitor contact plug 31 made of doped polysilicon, a refractory metal or a silicide of a refractory metal is connected to the n ⁺ source region 21. The first bonding layer 47 having the same plane pattern as the rectangular capacitor section 9 shown in FIG. 24 is connected to the capacitor contact plug 31.

On the other hand, the epitaxial capacitor (capacitor portion) 9 has a three-dimensional structure formed in the U groove.
That is, the lower barrier metal layer 52 formed along the bottom and side walls of the U groove, the lower electrode layer 53 such as SRO, the dielectric thin film layer 54 such as BSTO having a Ba mole fraction of 70% and the U groove are buried. Electrode layer 5 such as SRO formed as described above
5 and a flat upper barrier metal layer 56. The upper barrier metal layer 56 includes Ti / TiN / A
A plate electrode 62 such as an L layer is connected, and an oxide film (SiO ₂ film), a PSG film, a BPS
A passivation insulating film 65 such as a G film, a nitride film (Si ₃ N ₄ film), or a polyimide film is formed.
The second silicon substrate 64 is a silicon substrate having a high impurity density of about 2 × 10 ^{18 to} 1 × 10 ²⁰ cm ⁻³ . The lower barrier metal layer 52 is connected to a second bonding layer 63 via a second silicon substrate 64 having a high impurity density. Lower barrier metal layer 52, lower electrode layer 5
3, a dielectric thin film layer 54 such as BSTO, an upper electrode layer 55,
, A second silicon substrate 64, a first and second bonding layer 47,
Reference numeral 63 is formed so as to substantially fit in the region of the island-shaped planar pattern of the rectangular capacitor portion 9 shown in FIG. Then, the capacitor contact plug 31,
The first bonding layer 47, the second bonding layer 63, and the second
The n ⁺ source region 21 and the epitaxial capacitor (capacitor part) 9 are electrically connected by the silicon substrate 64 of FIG. In FIG. 23, reference numerals 32, 33, 3
4, 36, 37 are oxide films (SiO ₂ films), PSG films, B
It is an insulating film such as a PSG film or a nitride film (Si ₃ N ₄ film).

The single crystal BSTO having the Sr-rich composition has a very high dielectric constant of, for example, a dielectric constant of 800 or more at a film thickness of 20 nm. Thus, the single crystal BST having the Sr-rich composition
By using O, in addition to having a very high dielectric constant, since the capacitor has a three-dimensional shape, a predetermined capacitance value is ensured even if the cell area is extremely small. Therefore, a DRAM of 4 Gb to 256 Gb and a terabit DRAM can be realized.

Note that the upper electrode layer 55 and the upper barrier metal layer 56 need not always be formed by epitaxial growth. This is because the lattice constants of the lower electrode layer 53 in the a-axis and b-axis directions are sufficiently smaller than those of the dielectric thin film layer 54, and a mismatch in lattice constant occurs between the lower electrode layer 53 and the dielectric thin film layer 54. This is because it is possible to obtain a very high dielectric constant of 800 or more.

Next, a method of manufacturing a semiconductor memory device according to the third embodiment of the present invention will be described with reference to schematic cross-sectional views (FIGS. 3, 15, 16 and 25 to 37). . In the method for manufacturing a semiconductor memory device according to the third embodiment of the present invention, a transistor and a first bonding layer 47 are formed on a first silicon substrate 11 and a second bonding layer 47 is formed on a second silicon substrate 64. The steps from forming the layer 63 to joining the first bonding layer 47 and the second bonding layer 63 by abutting each other are the same as those in the method of manufacturing the semiconductor memory device according to the second embodiment. This will be described with reference to FIG. 3, FIG. 15 and FIG. In FIGS. 25 to 37, (a) and (b) of each drawing are cross-sectional views which are orthogonal to each other. That is, the cross-sectional view as viewed from the AA direction in FIG. (A) is FIG. (B), and the cross-sectional view as viewed from the BB direction in FIG. (B) is (a). Hereinafter, a description will be given using a schematic cross section of these steps.

(A) First, as shown in FIG. 3, the n ⁺ source region 21 and the n ⁺ drain region 2 are formed on the first silicon (100) substrate 11 by using a known process.
2. A transistor including a gate oxide film 29 and a word line 37, an element isolation insulating film 13, a bit line 37, and a capacitor contact plug 31 are formed, and the uppermost layer is formed by a method such as chemical mechanical polishing (CMP). To obtain a substrate surface.

(B) Next, a flat Cu film is formed as a first bonding layer 47 on the entire surface of the substrate. At this time, the flat first bonding layer 47 is connected to the n ⁺ source region 21 serving as the main electrode region of the transistor of the present invention by the capacitor contact plug 31.

(C) Next, as shown in FIG. 15, a flat Cu film is formed as the second bonding layer 63 on the entire surface of the second silicon (100) substrate 64.

(D) Next, as shown in FIG. 16, the Cu film as the first bonding layer 47 and the second bonding layer 63 is
A reduction treatment in hydrogen at 400 ° C. is performed to reduce the Cu oxide layer on the surface.
Press for 30 minutes to join.

(E) Next, as shown in FIG. 25, the bonded second silicon substrate 64 is thinned to a predetermined thickness. For example, the CMP from the back surface of the second silicon substrate 64
The second silicon substrate 64 is polished by 0.5 μm or the like.
The thickness is reduced to about m.

(F) Next, as shown in FIG. 26, a mask pattern of a photoresist is formed using a photolithography technique. That is, the alignment is performed based on the pattern of the transistor on the first silicon substrate 11,
Create an etching mask. Using this etching mask, a capacitor trench 92 for forming a three-dimensional capacitor is formed. The etching mask may be a multilayer film such as a photoresist and an oxide film. However, for etching the silicon substrate, it is preferable to etch the silicon substrate using the oxide film only mask pattern. To this end, an oxide film is formed by low-temperature CVD or CVD using TEOS, the oxide film is first patterned into a predetermined shape by a photoresist mask pattern, and then the photoresist mask pattern is removed. A single mask pattern may be used. Nitride film other than oxide film (Si ₃
Another mask material such as an N ₄ film may be used. The alignment is performed by the first silicon substrate 11 and patterning is performed. (G) Next, as shown in FIG.
10 nm thick (Ti, Al) N, lower electrode layer 5
SrRuO ₃ having a film thickness of 20 nm as substrate ₃ and a substrate temperature of 60
Epitaxial growth is performed at 0 ° C. by a DC sputtering method. Next, as shown in FIG. 28, the oxide film 66 and the like are buried in the capacitor trench 92 by a plasma CVD method or the like, and then, as shown in FIG. To perform flattening.

(H) Next, as shown in FIG. 30, a separation groove 93 is formed using photolithography and RIE. Etching masks are photoresist, oxide film,
Alternatively, a multilayer film such as a photoresist and an oxide film may be used. Separation groove 93 is formed inside the protrusion sandwiched between capacitor trenches 92. It is preferable to use the oxide layer 33 as an etching stop layer during the RIE for forming the separation groove 93. Further, as shown in FIG. 31, the capacitor isolation insulating film 61 is buried in the isolation groove 93 by a plasma CVD method or the like using TEOS gas as a raw material, and then flattened again by a CMP method or the like as shown in FIG.

(I) Next, as shown in FIG.
Only 6 is removed by selective etching such as RIE to expose the SRO lower electrode layer 53. Next, as shown in FIG. 34, the dielectric thin film layer 14 has a molar fraction of Ba of 30%.
To form a BSTO thin film 54 having a thickness of 20 nm. Further, as shown in FIG. 35, the upper electrode layer 55 has a thickness of 20 nm.
The SrRuO ₃ film is continuously grown epitaxially on the SRO electrode layer at a substrate temperature of 600 ° C. without being exposed to the air by RF or DC sputtering. However, BST is applied on the capacitor isolation insulating film 61 outside the trench.
Both O and SRO grow as polycrystals. At this time, when the width of the capacitor trench 92 is small, the trench can be filled with the SRO of the upper electrode layer. Next, FIG.
Is flattened by a CMP method or the like, and (Ti, Al) N having a thickness of 10 nm is formed as an upper barrier metal layer 56 at room temperature as shown in FIG.

(N) Finally, as shown in FIG. 23, an oxide film (SiO ₂ film) and a PS
A passivation insulating film 65 such as a G film, a BPSG film, a nitride film (Si ₃ N ₄ film), or a polyimide film is covered.

Through these steps, a memory cell including a capacitor and a transistor using a paraelectric thin film layer having a large dielectric constant can be manufactured with a high yield.
The operation as a RAM was confirmed. In the method for manufacturing a semiconductor memory device according to the third embodiment of the present invention, the first and second silicon substrates 11 and 64 are bonded to each other, and then a capacitor trench 92 is formed by a photolithography process. , This capacitor trench 9
2 is used to separate and form a capacitor for each cell, so that upper and lower first bonding layers 47 and second bonding layers 6
There is essentially no problem of misalignment of 3. Further, since the first bonding layer 47 and the second bonding layer 63 are bonded on the flat surface formed on the entire surface, a good bonding interface is obtained, and no open failure occurs. Furthermore, the first
Since the insulating film (capacitor separating insulating film) 61 is newly buried in the separation groove 93 formed around the joint between the bonding layer 47 and the second bonding layer 63, a leakage current path is generated. There is no fear. Therefore, each of the first and second bonding layers 4 of the adjacent memory cells
There is no danger of leakage current or short circuit between 7, 63.

(Fourth Embodiment) The manufacturing process of a semiconductor memory device according to a fourth embodiment of the present invention is almost the same as that of the first embodiment, but the first and second bonding steps are performed. Layer 4
This is an example in which Ti is used for the second bonding layer instead of using Al for both Nos. 7 and 59, and bonding is promoted by an alloying reaction between Al and Ti.

In the bonding step, a first bonding layer, Al, was formed by sputtering, and a second bonding layer, Ti, was formed by sputtering, and both were cleaned without being exposed to the air. The first bonded layer and the second bonded layer are abutted while maintaining the surface,
Press for 0 minutes to join. In this case, an apparatus as shown in FIG. 41 may be used. That is, as shown in FIG. 41, in the film forming chamber 1, Al as the first bonding layer is formed by sputtering, and Ti as the second bonding layer is formed by sputtering. By opening the gate valve between the pressure chamber 3 and the first silicon substrate 11 and the second silicon substrate 51 from the film forming chamber 1 to the pressure chamber 3 by vacuum,
The first silicon substrate 11 and the second silicon substrate 51 can be joined without being exposed to the air.

As a result, an alloy mainly composed of a TiAl phase is formed as a bonding layer. The melting point of TiAl phase is 1
A temperature of 460 ° C. is higher than 660 ° C. of Al, the strength is much higher, and a thermally and mechanically stable bonded layer can be formed.

(Fifth Embodiment) A method of manufacturing a semiconductor memory device according to a fifth embodiment of the present invention is substantially the same as that of the first embodiment, but includes a first and a second bonding. Layer Al
This is an example in which the bonding is promoted by an amorphous crystallization reaction using an amorphous Al-Ta alloy instead of using.

In the bonding step, the first bonded layer and the second bonded layer were formed by oxidizing an oxide layer formed on the surface by sputtering of Ar gas in an ultra-high vacuum at a pressure of 4 × 10 ⁻⁶ Pa or less. It is removed to expose the cleaned surface of the Al—Ti alloy, and the first bonded layer and the second
Are bonded to each other by pressing at 300 ° C. for 30 minutes. In this case, an apparatus as shown in FIG. 41 may be used. That is, as shown in FIG. 41, the first bonding layer and the second bonding layer are formed in the film forming chamber 1 at a pressure of 4 × 10 ⁻⁶ Pa.
The oxide layer formed on the surface by the sputtering of Ar gas in the following ultra-high vacuum is removed to obtain a cleaned surface of the Al-Ti alloy, and the gate valve between the film forming chamber 1 and the pressure bonding chamber 3 is opened. Then, if the first silicon substrate 11 and the second silicon substrate 51 are vacuum-transferred from the film forming chamber 1 to the pressure bonding chamber 3, the first silicon substrate 11 and the second silicon substrate 51 are not exposed to the atmosphere. Can be joined.

As a result, a crystallized alloy layer mainly composed of Al and Ti ₃ Al phase is formed as a bonding layer.
The bonding temperature is set to 100 ℃
It was possible to lower the temperature and to form a bonded layer that was much stronger in strength than single-phase Al.

As the amorphous material, in addition to the Al—Ta alloy, Al
-Cu, Al-Au, Al-Mg, Ti-Co, Ti-
Ni, Ti-Cu, Si-Mn, Si-Pd, Si-P
t, Si-Ag, Si-Au, or the like can be used.

[0138]

As described above, according to the present invention, it is possible to manufacture a memory cell in which a perovskite type epitaxial capacitor and a transistor are integrated at a high density, and an ultra-highly integrated FRAM or DRA of gigabit or more is manufactured.
M can be realized.

In particular, since a silicon wafer (semiconductor substrate) having a diameter of 200 mm (8 inches) to 300 mm (12 inches) or more can be used, a semiconductor memory device having a large capacity of gigabit or more and a low product unit price (Semiconductor memory) can be provided.

Further, according to the method of manufacturing a semiconductor memory device of the present invention, since the problem of misalignment between the first and second substrates is not inherent, the bonding step is simplified.
The bonding operation is completed in a short time, and the production yield of the semiconductor memory device manufacturing method of the present invention is high.

Further, according to the method of manufacturing a semiconductor memory device of the present invention, since there is no problem of misalignment in the bonding step, the bonding operation in a vacuum is facilitated. As a result, bonding can be performed in a vacuum at an extremely low pressure without being exposed to the air, so that a good bonding interface can be obtained.

According to the method for manufacturing a semiconductor memory device of the present invention, the first bonding layer 47 and the second bonding layer 5
9, a good bonding interface is obtained, and no open failure occurs. Further, since there is no possibility that a leak current path is generated in the capacitor isolation insulating film, there is no risk of leak current between memory cells or short circuit, and a high-performance and high-reliability FRAM or DRAM can be realized. Has an extremely high industrial value.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of an FRAM memory cell according to a first embodiment of the present invention.

FIG. 2 is a plan view of the FRAM memory cell according to the first embodiment of the present invention.

FIG. 3 is a sectional view of the FRAM memory cell according to the first embodiment of the present invention in the order of steps;

FIG. 4 is a sectional view of the FRAM memory cell according to the first embodiment of the present invention in the order of steps;

FIG. 5 is a sectional view in order of the process of the FRAM memory cell according to the first embodiment of the present invention.

FIG. 6 is a sectional view in order of the process of the FRAM memory cell according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the FRAM memory cell according to the first embodiment of the present invention in the order of steps;

FIG. 8 is a top view corresponding to FIG. 7 of the FRAM memory cell according to the first embodiment of the present invention.

FIG. 9 is a process sectional view of the FRAM memory cell according to the first embodiment of the present invention.

FIG. 10 is a process sectional view of the FRAM memory cell according to the first embodiment of the present invention.

FIG. 11 is a process sectional view of the FRAM memory cell according to the first embodiment of the present invention.

FIG. 12 is a diagram illustrating a modified example of the S according to the modification of the first embodiment of the present invention.
FIG. 3 is a schematic sectional view of an OI / FRAM memory cell.

FIG. 13 is a schematic sectional view of an FRAM memory cell according to a second embodiment of the present invention.

FIG. 14 is a plan view of an FRAM memory cell according to a second embodiment of the present invention.

FIG. 15 is a sectional view of the FRAM memory cell according to the second embodiment of the present invention in the order of steps;

FIG. 16 is a sectional view in order of the steps of the FRAM memory cell according to the second embodiment of the present invention.

FIG. 17 is a sectional view in order of the process of the FRAM memory cell according to the second embodiment of the present invention.

FIG. 18 is a sectional view of the FRAM memory cell according to the second embodiment of the present invention in the order of steps;

FIG. 19 is a sectional view in order of process of the FRAM memory cell according to the second embodiment of the present invention.

FIG. 20 is a sectional view in order of the process of the FRAM memory cell according to the second embodiment of the present invention.

FIG. 21 is a sectional view in order of a process of an FRAM memory cell according to a second embodiment of the present invention.

FIG. 22 is a sectional view in order of the process of the FRAM memory cell according to the second embodiment of the present invention.

FIG. 23 is a schematic sectional view of a DRAM memory cell according to a third embodiment of the present invention.

FIG. 24 is a plan view of a DRAM memory cell according to a third embodiment of the present invention.

FIG. 25 is a step-by-step cross-sectional view of the DRAM memory cell according to the third embodiment of the present invention.

FIG. 26 is a sectional view illustrating a DRAM memory cell according to a third embodiment of the present invention in the order of steps;

FIG. 27 is a step-by-step cross-sectional view of the DRAM memory cell according to the third embodiment of the present invention.

FIG. 28 is a cross-sectional view illustrating a DRAM memory cell according to a third embodiment of the present invention in the order of steps;

FIG. 29 is a sectional view in order of process of the DRAM memory cell according to the third embodiment of the present invention.

FIG. 30 is a sectional view in order of process of the DRAM memory cell according to the third embodiment of the present invention.

FIG. 31 is a cross-sectional view illustrating a DRAM memory cell according to a third embodiment of the present invention in the order of steps;

FIG. 32 is a cross-sectional view illustrating a DRAM memory cell according to a third embodiment of the present invention in the order of steps;

FIG. 33 is a step-by-step cross-sectional view of the DRAM memory cell according to the third embodiment of the present invention.

FIG. 34 is a cross-sectional view illustrating a DRAM memory cell according to a third embodiment of the present invention in the order of steps;

FIG. 35 is a cross-sectional view in the order of steps of the DRAM memory cell according to the third embodiment of the present invention.

FIG. 36 is a cross-sectional view illustrating a DRAM memory cell according to a third embodiment of the present invention in the order of steps;

FIG. 37 is a step-by-step cross-sectional view of the DRAM memory cell according to the third embodiment of the present invention;

FIG. 38: FRA studied by the present inventors first
FIG. 7 is a sectional view in order of the process of the M cell.

FIG. 39. FRA examined by the present inventors first in a preliminary manner.
FIG. 7 is a sectional view in order of the process of the M cell.

FIG. 40: FRA studied by the present inventors first
FIG. 7 is a sectional view in order of the process of the M cell.

FIG. 41 is a diagram showing an apparatus for joining two silicon substrates without being exposed to the air after film formation or surface treatment.

FIG. 42 is a view showing an apparatus for bonding two silicon substrates by reducing the surface of the silicon substrate with hydrogen so as not to be exposed to the air.

FIG. 43 is a sectional view showing a conventional FRAM cell.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Film-forming chamber 2 Reduction chamber 3 Compression chamber 4 Press 5 Stage 6 Heater 7 Gas inlet 9 Capacitor part 10, 11, 51, 64 Silicon substrate 12 P well 13 STI area 14 Embedded insulating film 15 P-type SOI film 21 Source area Reference Signs List 22 drain region 29 gate oxide film 31 capacitor contact plug 32, 33, 34, 36, 37, 38, 48 insulating film 35 bit line 39 bit line contact plug 47, 49 first bonding layer 52 lower barrier metal layer 53 lower Electrode layer 54 Dielectric thin film layer 55 Upper electrode layer 56 Upper barrier metal layer 57, 59, 63 Second bonding layer 58, 61 Capacitor isolation insulating film 62 Plate electrode layer 65 Passivation insulating film 66 Flattening embedded material 91, 93 Separation groove 92 Capacitor trench 110 Oxide base Plate (MgO, STO, etc.)

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (3)

[Claims] A first semiconductor substrate having a plurality of transistors arranged in a matrix; a second semiconductor substrate having a plurality of perovskite-type epitaxial capacitors corresponding to each of the plurality of transistors; A semiconductor memory device characterized by including at least a connecting portion for electrically connecting the main electrode region and the epitaxial capacitor in a one-to-one correspondence. 2. A transistor is formed on a first substrate,
Flattening the uppermost layer to form a substrate surface, forming a flat first bonding layer connected to the main electrode region of the transistor over the entire surface of the substrate, and epitaxially growing the second substrate. Forming a multilayer structure for a capacitor comprising at least a first electrode layer, a dielectric thin film layer, and a second electrode layer thereon; and forming a flat second bonding layer over the entire surface of the multilayer structure for a capacitor. Performing the steps of: abutting the first bonding layer and the second bonding layer, and bonding the first substrate and the second substrate to each other; A method for manufacturing a semiconductor memory device, comprising: at least a step of forming a capacitor for each cell by separating a second bonding layer into a plurality of patterns. 3. A transistor is formed on a first substrate,
Flattening the uppermost layer to form a substrate surface; forming a flat first bonding layer connected to the main electrode region of the transistor over the entire surface of the substrate; A step of forming a flat second bonding layer on the entire surface; and bonding the first substrate and the second substrate to each other by abutting the first bonding layer and the second bonding layer. A step of thinning the second substrate to a predetermined thickness after the bonding step; a first electrode layer, a dielectric thin film layer, and a second electrode on the second substrate by epitaxial growth. Forming at least a part of a multilayer structure for a capacitor comprising a plurality of layers; separating at least a part of the multilayer structure for a capacitor, a second substrate, and first and second bonding layers into a plurality of patterns. Can be separated into capacitors for each cell Method of manufacturing a semiconductor memory device characterized by comprising at least a step of.