JP2010232400A - Semiconductor substrate, method of manufacturing semiconductor substrate, and semiconductor package - Google Patents

Semiconductor substrate, method of manufacturing semiconductor substrate, and semiconductor package Download PDF

Info

Publication number
JP2010232400A
JP2010232400A JP2009077897A JP2009077897A JP2010232400A JP 2010232400 A JP2010232400 A JP 2010232400A JP 2009077897 A JP2009077897 A JP 2009077897A JP 2009077897 A JP2009077897 A JP 2009077897A JP 2010232400 A JP2010232400 A JP 2010232400A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
wiring layer
opening
insulating layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009077897A
Other languages
Japanese (ja)
Inventor
Takeshi Kita
武司 北
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to JP2009077897A priority Critical patent/JP2010232400A/en
Publication of JP2010232400A publication Critical patent/JP2010232400A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate having a through electrode with high reliability, and to provide a method of manufacturing the semiconductor substrate. <P>SOLUTION: A first wiring layer (3) is formed via a first insulating layer (2); and a second wiring layer (5) is formed at an inner periphery of the through hole (4). The through hole (4) comprises: a first opening (4a); and a second opening (4b) having smaller opening area than the first opening (4a), and has a third wiring layer (103a) formed at the second opening (4b), the third wiring layer (103a) being formed before the first opening (4a) is formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体基板の貫通孔に形成した半導体基板と半導体基板の製造方法および半導体パッケージに関するものである。   The present invention relates to a semiconductor substrate formed in a through hole of a semiconductor substrate, a method for manufacturing the semiconductor substrate, and a semiconductor package.

貫通電極を有するこの種の半導体基板を内蔵した半導体パッケージの一例を図１２に示す。
この半導体パッケージでは、半導体基板１にドライエッチング加工などで貫通孔２１を形成し、貫通孔２１の側壁にＣＶＤ法などにより絶縁膜を堆積する。この絶縁膜の上にシード層を形成し、めっき法などにより導電性材料を充填させることによって半導体基板を貫通する電極（貫通電極と呼ぶ）が形成されている。 An example of a semiconductor package incorporating this type of semiconductor substrate having a through electrode is shown in FIG.
In this semiconductor package, a through hole 21 is formed in the semiconductor substrate 1 by dry etching or the like, and an insulating film is deposited on the side wall of the through hole 21 by a CVD method or the like. An electrode penetrating the semiconductor substrate (called a penetrating electrode) is formed by forming a seed layer on the insulating film and filling a conductive material by plating or the like.

貫通孔２１の形成後、或いは形成前に半導体基板１の上面に配線層５Ａを形成して、半導体基板１に実装された、或いは半導体基板１自体に作り込まれた回路素子２２と前記貫通電極とを電気的に接続している。   After or before the formation of the through-hole 21, the wiring layer 5A is formed on the upper surface of the semiconductor substrate 1, and the circuit element 22 mounted on the semiconductor substrate 1 or built in the semiconductor substrate 1 itself and the through-electrode And are electrically connected.

また、この貫通電極を有するこの種の半導体基板１は、半導体基板１の下面に配線層３Ａを形成した後、樹脂基板等の基板１７にフリップチップ接続し、アンダーフィル材１８でその接続部を保護した後、基板全体を樹脂１９で覆い、基板１７に半田ボール等の導電部材２０を搭載することにより半導体パッケージが作製され、導電部材２０を介してプリント基板等の外部回路と電気的に接続されている。   Also, in this type of semiconductor substrate 1 having this through electrode, after forming the wiring layer 3A on the lower surface of the semiconductor substrate 1, it is flip-chip connected to a substrate 17 such as a resin substrate, and the connection portion is connected by an underfill material 18. After the protection, the entire substrate is covered with a resin 19, and a semiconductor package is manufactured by mounting a conductive member 20 such as a solder ball on the substrate 17, and is electrically connected to an external circuit such as a printed circuit board via the conductive member 20. Has been.

半導体基板１に回路素子が作り込まれている場合、半導体基板１の上面に絶縁層が形成されている場合が多い。半導体基板１の前記上面と下面の間に導通経路を形成するためには、半導体基板１に貫通孔２１を形成後、前記絶縁層に開口部を形成して前記配線層３Ａを露出させる必要がある。   When circuit elements are formed in the semiconductor substrate 1, an insulating layer is often formed on the upper surface of the semiconductor substrate 1. In order to form a conduction path between the upper surface and the lower surface of the semiconductor substrate 1, it is necessary to form the through hole 21 in the semiconductor substrate 1 and then form an opening in the insulating layer to expose the wiring layer 3A. is there.

特許文献１には、図１３（ａ）〜（ｄ）に示す第１の方法が記載されている。
図１３（ａ）では、半導体基板１に貫通孔形成用のレジスト１０を形成して、半導体基板１に貫通孔２３を形成する。 Patent Document 1 describes a first method shown in FIGS. 13 (a) to 13 (d).
In FIG. 13A, a through hole forming resist 10 is formed in the semiconductor substrate 1, and the through hole 23 is formed in the semiconductor substrate 1.

図１３（ｂ）では、半導体基板１に形成されている第１絶縁層２を、レジスト１０をマスクとしてエッチングして開口部２４を形成して、半導体基板１に形成されている第１配線層３を貫通孔２３に露出させる。   In FIG. 13B, the first insulating layer 2 formed on the semiconductor substrate 1 is etched using the resist 10 as a mask to form the opening 24, and the first wiring layer formed on the semiconductor substrate 1. 3 is exposed in the through hole 23.

図１３（ｃ）では、レジスト１０を除去し、ＣＶＤ法などにより半導体基板１の表面と貫通孔２３の側壁および開口部２４に第２絶縁層７を形成する。
図１３（ｄ）では、貫通孔２３の底部のみ第２絶縁層７を除去したあと、スパッタ等によるシード層形成やメッキ法により第２配線層５を形成して貫通電極を形成している。１５は充填された絶縁体である。 In FIG. 13C, the resist 10 is removed, and the second insulating layer 7 is formed on the surface of the semiconductor substrate 1, the side wall of the through hole 23, and the opening 24 by the CVD method or the like.
In FIG. 13D, after the second insulating layer 7 is removed only at the bottom of the through hole 23, the second wiring layer 5 is formed by the seed layer formation by sputtering or the plating method to form the through electrode. Reference numeral 15 denotes a filled insulator.

また、特許文献２には図１４（ａ）〜（ｈ）に示す第２の方法が記載されている。
図１４（ａ）では、半導体基板１に貫通孔形成用のレジスト１０を形成し、さらに、等方性エッチングによって貫通孔上部にすり鉢形状２５を形成する。 Patent Document 2 describes a second method shown in FIGS. 14 (a) to 14 (h).
In FIG. 14A, a through hole forming resist 10 is formed on the semiconductor substrate 1, and a mortar shape 25 is formed above the through hole by isotropic etching.

図１４（ｂ）では、レジスト１０をマスクにし、異方性エッチングによって貫通孔２６を形成する。
図１４（ｃ）では、レジスト１０を除去する。 In FIG. 14B, the through hole 26 is formed by anisotropic etching using the resist 10 as a mask.
In FIG. 14C, the resist 10 is removed.

図１４（ｄ）では、貫通孔２６の底部の第１絶縁層２に開口部を形成するために、レジスト２７を貫通孔２６の全体に塗布する。
図１４（ｅ）では、露光現像することによってパターニングする。 In FIG. 14D, a resist 27 is applied to the entire through hole 26 in order to form an opening in the first insulating layer 2 at the bottom of the through hole 26.
In FIG. 14E, patterning is performed by exposure and development.

図１４（ｆ）では、レジスト２７をマスクにして第１絶縁層２に開口部２８を形成する。
図１４（ｇ）では、レジスト２７を除去する。 In FIG. 14F, the opening 28 is formed in the first insulating layer 2 using the resist 27 as a mask.
In FIG. 14G, the resist 27 is removed.

図１４（ｈ）では、スパッタ等によるシード層形成やメッキ法により第１配線層３に達する第２配線層５を形成し、貫通電極を形成している。
特開２００６−１２８１７１号公報 特開２００７−５３１４９号公報 In FIG. 14 (h), the second wiring layer 5 reaching the first wiring layer 3 is formed by seed layer formation by sputtering or the like, or plating, and the through electrode is formed.
JP 2006-128171 A JP 2007-53149 A

しかしながら、第１の方法では、第１絶縁層２に開口部２４を形成する際に下地の第１配線層３をエッチングしてしまうため、第１配線層３から飛び出した金属粒子が第１絶縁層２の開口部２４の側壁に付着し、第１配線層３と半導体基板１とが導通してしまい、結果として、形成した貫通電極の信頼性が低くなる。   However, in the first method, when the opening 24 is formed in the first insulating layer 2, the underlying first wiring layer 3 is etched, so that the metal particles popping out from the first wiring layer 3 are in the first insulating layer. The first wiring layer 3 and the semiconductor substrate 1 are electrically connected to the side wall of the opening 24 of the layer 2, and as a result, the reliability of the formed through electrode is lowered.

また、第２の方法では、図１４（ｅ）〜（ｆ）において、半導体基板１に形成した貫通孔２６の底面の一部に第１絶縁層２の開口部２８を形成するため、図１４（ｇ）に示すように貫通孔２６と開口部２８との接続部分に段部２９が形成されており、第１絶縁層２の開口部２８の側壁に金属粒子が付着しても半導体基板１との導通経路が形成されない。   Further, in the second method, the opening 28 of the first insulating layer 2 is formed in a part of the bottom surface of the through hole 26 formed in the semiconductor substrate 1 in FIGS. As shown in (g), a stepped portion 29 is formed at the connection portion between the through hole 26 and the opening 28, and the semiconductor substrate 1 even if metal particles adhere to the side wall of the opening 28 of the first insulating layer 2. No conduction path is formed.

しかし、図１４（ｈ）において第１絶縁層２の上に第２配線層５が形成されるため、それらの熱膨張係数の違いから、リフロー等の後工程で熱ストレスがかかった際に膜の密着力が低くなり貫通電極の信頼性が低くなる。また、レジスト形成とレジスト除去工程が２回必要なため処理工程数が多くなり、貫通電極の作製リードタイムが長くなる。さらに、アスペクト比が高い貫通電極を作製する場合、図１４（ｅ）に示すように、開口部にすり鉢形状を形成させても、貫通孔２６の底部まで光が入りにくいため露光が不十分になり、また貫通孔２６が深いため孔底部まで現像液が入り込まず現像も困難であるため、第１絶縁層２に開口部２８を形成する際のレジスト形成が困難になるという課題を有している。   However, since the second wiring layer 5 is formed on the first insulating layer 2 in FIG. 14 (h), a film is formed when thermal stress is applied in a subsequent process such as reflow due to the difference in thermal expansion coefficient thereof. As a result, the through-electrode reliability is lowered. Further, since the resist formation and resist removal steps are required twice, the number of processing steps is increased, and the lead time for manufacturing the through electrode is increased. Further, when a through electrode having a high aspect ratio is manufactured, as shown in FIG. 14E, even if a mortar shape is formed in the opening, light does not easily enter the bottom of the through hole 26, so that exposure is insufficient. In addition, since the through hole 26 is deep and the developer does not enter the bottom of the hole and development is difficult, it is difficult to form a resist when forming the opening 28 in the first insulating layer 2. Yes.

本発明は、高信頼性の貫通電極を有する半導体基板と半導体パッケージおよび半導体基板の製造方法を提供することを目的とする。   An object of the present invention is to provide a semiconductor substrate having a highly reliable through electrode, a semiconductor package, and a method for manufacturing the semiconductor substrate.

本発明の請求項１記載の半導体基板は、半導体基板の一方の面に第１絶縁層を介して第１配線層が形成され、前記半導体基板を貫通する貫通孔の内周に第２配線層を形成した貫通電極を有する半導体基板であって、前記貫通孔は、 前記半導体基板の他方の面から前記第１絶縁層に向かって形成された第１の開口部と、前記第１の開口部よりも開口面積が小さく前記第１の開口部の底部から前記第１絶縁層を貫通して前記第１の配線層に達する第２の開口部とで形成され、前記第２の開口部に第３配線層を設け、前記半導体基板の他方の面に達している前記第２配線層が、第３配線層を経て前記第１の配線層に電気接続されていることを特徴とする。   According to a first aspect of the present invention, there is provided the semiconductor substrate, wherein the first wiring layer is formed on one surface of the semiconductor substrate via the first insulating layer, and the second wiring layer is formed on the inner periphery of the through hole penetrating the semiconductor substrate. The through-hole includes a first opening formed from the other surface of the semiconductor substrate toward the first insulating layer, and the first opening. A second opening that has a smaller opening area than the bottom of the first opening and penetrates the first insulating layer and reaches the first wiring layer, and the second opening has a second opening. Three wiring layers are provided, and the second wiring layer reaching the other surface of the semiconductor substrate is electrically connected to the first wiring layer through the third wiring layer.

本発明の請求項２記載の半導体基板は、請求項１において、前記貫通孔の前記第１の開口部の周面にわたって第２絶縁層が形成され、前記第２配線層と前記半導体基板の間に前記第２絶縁層が介在していることを特徴とする。   According to a second aspect of the present invention, there is provided the semiconductor substrate according to the first aspect, wherein a second insulating layer is formed over a peripheral surface of the first opening of the through hole, and the second wiring layer and the semiconductor substrate are formed. And the second insulating layer is interposed.

本発明の請求項３記載の半導体基板は、半導体基板の一方の面に第１絶縁層が形成され、前記半導体基板を貫通する貫通孔の内周に第２配線層を形成した貫通電極を有する半導体基板であって、前記貫通孔は、 前記半導体基板の他方の面から前記第１絶縁層に向かって形成された第１の開口部と、前記第１の開口部よりも開口面積が小さく前記第１の開口部の底部から前記第１絶縁層を貫通する第２の開口部と、前記第２の開口部に形成されて一端が前記第１絶縁層から突出した第３配線層とを有しており、前記半導体基板の他方の面に達している前記第２配線層が、第３配線層に電気接続されていることを特徴とする。   According to a third aspect of the present invention, there is provided a semiconductor substrate having a through electrode in which a first insulating layer is formed on one surface of the semiconductor substrate, and a second wiring layer is formed on an inner periphery of a through hole penetrating the semiconductor substrate. In the semiconductor substrate, the through hole has a first opening formed from the other surface of the semiconductor substrate toward the first insulating layer, and an opening area smaller than the first opening. A second opening penetrating the first insulating layer from the bottom of the first opening; and a third wiring layer formed in the second opening and having one end protruding from the first insulating layer. The second wiring layer reaching the other surface of the semiconductor substrate is electrically connected to the third wiring layer.

本発明の請求項４記載の半導体基板は、請求項３において、前記第２の開口部に導電材料を充填して前記第２配線層が形成され、前記第２の開口部に充填された前記第２配線層の上に外部回路と電気的に接続するための導電部材を備えたことを特徴とする。   The semiconductor substrate according to a fourth aspect of the present invention is the semiconductor substrate according to the third aspect, wherein the second wiring layer is formed by filling the second opening with a conductive material and filling the second opening. A conductive member for electrically connecting to an external circuit is provided on the second wiring layer.

本発明の請求項５記載の半導体基板は、請求項１または請求項３において、前記第２配線層は、Ｔｉ、Ｗ、Ｃｕ、Ｃｒ、Ａｕ、Ａｌ、Ａｇ、Ｎｉ等の金属材料やＴｉＮ等の金属化合物、またはそれらを含有した導電性材料、ポリシリコン等のＳｉ系材料であり、前記第２配線層は単層または２層以上の多層膜であることを特徴とする。   The semiconductor substrate according to claim 5 of the present invention is the semiconductor substrate according to claim 1 or 3, wherein the second wiring layer is made of a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, Ni, TiN, or the like. These metal compounds, or conductive materials containing them, and Si-based materials such as polysilicon, are characterized in that the second wiring layer is a single layer or a multilayer film of two or more layers.

本発明の請求項６記載の半導体基板は、請求項２において、前記第２絶縁層は、ＳｉＮ、ＳｉＯ２、ＢＰＳＧ、熱酸化膜等のＳｉ化合物やＡｌ２Ｏ３等の金属化合物、またはポリイミド樹脂等の有機化合物であり、また前記第２絶縁層は単層または２層以上の多層膜であることを特徴とする。 The semiconductor substrate according to claim 6 of the present invention is the semiconductor substrate according to claim 2, wherein the second insulating layer is made of Si compound such as SiN, SiO 2 , BPSG, thermal oxide film, metal compound such as Al 2 O 3 , or polyimide. It is an organic compound such as a resin, and the second insulating layer is a single layer or a multilayer film of two or more layers.

本発明の請求項７記載の半導体基板は、請求項１において、前記第２配線層上にその表面の一部を露出するように形成された保護膜と、前記第２配線層上に外部回路と電気的に接続するための導電部材とを備えることを特徴とする。   According to a seventh aspect of the present invention, there is provided a semiconductor substrate according to the first aspect, wherein the protective film is formed on the second wiring layer so as to expose a part of the surface thereof, and the external circuit is formed on the second wiring layer. And a conductive member for electrical connection.

本発明の請求項８記載の半導体基板は、請求項１において、前記貫通孔の内部に形成された空隙部の一部、または全体に絶縁材料が充填されていることを特徴とする。
本発明の請求項９記載の半導体基板は、請求項１または請求項３において、前記第１の開口部の半導体基板１の他方の面１ｂの孔径は、前記第１の開口部の底部の孔径より大きいことを特徴とする。 A semiconductor substrate according to an eighth aspect of the present invention is characterized in that, in the first aspect, an insulating material is filled in a part or the whole of the void formed inside the through hole.
A semiconductor substrate according to a ninth aspect of the present invention is the semiconductor substrate according to the first or third aspect, wherein the hole diameter of the other surface 1b of the semiconductor substrate 1 of the first opening is the hole diameter of the bottom of the first opening. It is characterized by being larger.

本発明の請求項１０記載の半導体基板は、請求項１または請求項３において、前記半導体基板が、シリコン、シリカゲルマニウム等のシリコン系半導体、あるいはガリウムヒ素、ガリウムナイトライド、インジウムリン等の化合物半導体であることを特徴とする。   A semiconductor substrate according to a tenth aspect of the present invention is the semiconductor substrate according to the first or third aspect, wherein the semiconductor substrate is a silicon-based semiconductor such as silicon or silica gel, or a compound semiconductor such as gallium arsenide, gallium nitride, or indium phosphide. It is characterized by being.

本発明の請求項１１記載の半導体基板は、請求項１または請求項３において、前記第３配線層は、Ｔｉ、Ｗ、Ｃｕ、Ｃｒ、Ａｕ、Ａｌ、Ａｇ、Ｎｉ等の金属材料やＴｉＮ等の金属化合物、ポリシリコン等のＳｉ系材料、あるいは上記材料の混合物であり、また前記第３配線層は単層又は２層以上の多層膜であることを特徴とする。   The semiconductor substrate according to an eleventh aspect of the present invention is the semiconductor substrate according to the first or third aspect, wherein the third wiring layer is made of a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, Ni, TiN, or the like. A metal compound, a Si-based material such as polysilicon, or a mixture of the above materials, and the third wiring layer is a single layer or a multilayer film of two or more layers.

本発明の請求項１２記載の半導体基板は、請求項１または請求項３において、前記第３配線層と前記第１配線層は同一材料で構成されていることを特徴とする。
本発明の請求項１３記載の半導体基板は、請求項１または請求項３において、前記第１絶縁層は、ＳｉＮ、ＳｉＯ２、ＢＰＳＧ、熱酸化膜等のＳｉ化合物やＡｌ２Ｏ３等の金属化合物であり、また前記絶縁層は単層または２層以上の多層膜であることを特徴とする。 According to a twelfth aspect of the present invention, in the semiconductor substrate according to the first or third aspect, the third wiring layer and the first wiring layer are made of the same material.
A semiconductor substrate according to a thirteenth aspect of the present invention is the semiconductor substrate according to the first or third aspect, wherein the first insulating layer is made of a Si compound such as SiN, SiO 2 , BPSG, or a thermal oxide film, or a metal such as Al 2 O 3. Further, the insulating layer is a single layer or a multilayer film of two or more layers.

本発明の請求項１４記載の半導体パッケージは、請求項１から請求項１３の何れかに記載の半導体基板を内蔵したことを特徴とする。
本発明の請求項１５記載の半導体基板の製造方法は、半導体基板の一方の面に第１絶縁層を形成する工程と、第１絶縁層に形成されたレジストをマスクとして第１絶縁層をエッチングして第１絶縁層を貫通する第２の開口部を形成する工程と、前記第２の開口部に第３配線層を形成する工程と、前記第１絶縁層の上に前記第３配線層に導通する第１配線層を形成する工程と、前記半導体基板の他方の面に形成されたレジストをマスクとして前記半導体基板をエッチングして前記半導体基板の他方の面から前記第３配線層が露出するように第２の開口部よりも開口面積が大きい第１の開口部を形成する工程と、前記半導体基板の他方の面と前記第１の開口部の内側に第２絶縁層を形成する工程と、前記第１の開口部の底部に形成された前記第２絶縁層を除去して前記第３配線層を露出させる工程と、前記第１の開口部の内側に前記第３配線層に導通すると共に前記半導体基板の他方の面に達する第２配線層を形成する工程とを有することを特徴とする。 A semiconductor package according to a fourteenth aspect of the present invention includes the semiconductor substrate according to any one of the first to thirteenth aspects.
According to a fifteenth aspect of the present invention, there is provided a semiconductor substrate manufacturing method comprising: forming a first insulating layer on one surface of the semiconductor substrate; and etching the first insulating layer using a resist formed on the first insulating layer as a mask. Forming a second opening penetrating the first insulating layer, forming a third wiring layer in the second opening, and forming the third wiring layer on the first insulating layer. Forming a first wiring layer electrically connected to the semiconductor substrate, and etching the semiconductor substrate using a resist formed on the other surface of the semiconductor substrate as a mask to expose the third wiring layer from the other surface of the semiconductor substrate. Forming a first opening having a larger opening area than the second opening, and forming a second insulating layer on the other surface of the semiconductor substrate and on the inner side of the first opening. And the second formed at the bottom of the first opening. Removing the edge layer to expose the third wiring layer; and forming a second wiring layer that is electrically connected to the third wiring layer and reaches the other surface of the semiconductor substrate inside the first opening. And a step of performing.

本発明の請求項１６記載の半導体基板の製造方法は、請求項１５において、前記第２の開口部を形成する工程はドライエッチング工法やウェットエッチング工法により形成することを特徴とする。   According to a sixteenth aspect of the present invention, in the semiconductor substrate manufacturing method according to the fifteenth aspect, the step of forming the second opening is formed by a dry etching method or a wet etching method.

本発明の請求項１７記載の半導体基板の製造方法は、請求項１５において、前記第３配線層を形成する工程はＣＶＤ法やスパッタリング法、蒸着法等により形成することを特徴とする。   According to a seventeenth aspect of the present invention, in the semiconductor substrate manufacturing method according to the fifteenth aspect, the step of forming the third wiring layer is formed by a CVD method, a sputtering method, a vapor deposition method, or the like.

本発明の請求項１８記載の半導体基板の製造方法は、請求項１５において、前記第３配線層と前記第１配線層を同時に形成することを特徴とする。   According to an eighteenth aspect of the present invention, in the semiconductor substrate manufacturing method according to the fifteenth aspect, the third wiring layer and the first wiring layer are formed simultaneously.

この半導体基板の製造方法によると、第１の開口部の形成前に、第１絶縁層に第３配線層を形成することにより、第３配線層の変形や破損、或いは完全除去を防止でき、さらに半導体基板と第１配線層の間の絶縁性を向上させ、その後に形成される貫通電極およびそれを設けた半導体や半導体パッケージの信頼性を向上させることができる。   According to this method of manufacturing a semiconductor substrate, by forming the third wiring layer in the first insulating layer before forming the first opening, deformation, breakage, or complete removal of the third wiring layer can be prevented, Furthermore, the insulation between the semiconductor substrate and the first wiring layer can be improved, and the reliability of the through electrode formed thereafter and the semiconductor or semiconductor package provided with the through electrode can be improved.

この半導体基板によると、第１の開口部の径より小さい面積の第３配線層を形成することにより、半導体基板と第１配線層間の絶縁性を向上させ、その後に形成される貫通電極およびそれを設けた半導体や半導体パッケージの信頼性を向上させることができるという効果を有する。   According to this semiconductor substrate, by forming the third wiring layer having an area smaller than the diameter of the first opening, the insulation between the semiconductor substrate and the first wiring layer is improved, and the through electrode formed thereafter and It is possible to improve the reliability of a semiconductor or a semiconductor package provided with.

以下、本発明の各実施の形態を図１〜図１１に基づいて説明する。
（実施の形態１）
図１，図２，図３は本発明の実施の形態１を示す。 Hereinafter, each embodiment of the present invention will be described with reference to FIGS.
(Embodiment 1)
1, FIG. 2 and FIG. 3 show Embodiment 1 of the present invention.

図１は貫通電極を有する半導体基板を示している。
半導体基板１の一方の面１ａに第１絶縁層２を介して第１配線層３が形成され、半導体基板１を貫通する貫通孔４の内周に第２配線層５を形成した貫通電極を有する半導体パッケージであって、半導体基板１の厚さ方向にドライエッチングによって形成された貫通孔４は開口径が５μｍから２００μｍ程度で、孔深さは１０μｍから４００μｍ程度の大きさである。 FIG. 1 shows a semiconductor substrate having through electrodes.
A through electrode in which a first wiring layer 3 is formed on one surface 1a of the semiconductor substrate 1 with a first insulating layer 2 interposed therebetween and a second wiring layer 5 is formed on the inner periphery of a through hole 4 that penetrates the semiconductor substrate 1 is provided. The through hole 4 formed by dry etching in the thickness direction of the semiconductor substrate 1 has an opening diameter of about 5 μm to 200 μm and a hole depth of about 10 μm to 400 μm.

貫通孔４は、半導体基板１に形成された第１の開口部としての大径部４ａと、大径部４ａの底部から第１絶縁層２を貫通して第１配線層３に達する第２の開口部としての小径部４ｂを有している。小径部４ｂには導電性材料が充填されて第３配線層１０３ａが形成形成されており、半導体基板１の他方の面１ｂに達している第２配線層５が、第３配線層１０３ａを経て第１の配線層３に電気接続されている。   The through hole 4 has a large diameter portion 4a as a first opening formed in the semiconductor substrate 1, and a second hole that reaches the first wiring layer 3 through the first insulating layer 2 from the bottom of the large diameter portion 4a. The small-diameter portion 4b is provided as an opening. The small diameter portion 4b is filled with a conductive material to form and form a third wiring layer 103a, and the second wiring layer 5 reaching the other surface 1b of the semiconductor substrate 1 passes through the third wiring layer 103a. The first wiring layer 3 is electrically connected.

７は第２絶縁層である。８は保護膜、９は半導体パッケージの回路素子を外部回路との接続に使用される導電部材である。なお、半導体基板１の内部または表面上には回路素子が構築されている。   Reference numeral 7 denotes a second insulating layer. Reference numeral 8 denotes a protective film, and 9 denotes a conductive member used for connecting the circuit element of the semiconductor package to an external circuit. A circuit element is constructed inside or on the surface of the semiconductor substrate 1.

この貫通電極は、図２と図３に示す貫通電極形成プロセスによって作成されている。
まず、図２（ａ）では、半導体基板１に第１絶縁層２を成膜する。第１絶縁層２がＳｉＯ２の場合、プラズマＣＶＤ等で形成される。第１絶縁層２の材料はその他、ＳｉＮ、ＢＰＳＧ、熱酸化膜等のＳｉ化合物やＡｌ２Ｏ３等の金属化合物であってもよい。また、その絶縁層は単層または２層以上の多層膜であっても構わない。そして第１絶縁層２にフォトレジスト１０１を塗布し、フォトリソグラフィ工法により開口部１０２を形成する。フォトレジストはスピンコーティングにより形成する。 The through electrode is formed by the through electrode forming process shown in FIGS.
First, in FIG. 2A, the first insulating layer 2 is formed on the semiconductor substrate 1. When the first insulating layer 2 is SiO 2 , it is formed by plasma CVD or the like. In addition, the material of the first insulating layer 2 may be a Si compound such as SiN, BPSG, or a thermal oxide film, or a metal compound such as Al 2 O 3 . The insulating layer may be a single layer or a multilayer film of two or more layers. Then, a photoresist 101 is applied to the first insulating layer 2 and an opening 102 is formed by a photolithography method. The photoresist is formed by spin coating.

図２（ｂ）では、第１絶縁層２をエッチングし、小径部４ｂを形成する。小径部４ｂの開口径は大径部４ａの開口径より小さく４〜１８０μｍ程度であり、第１配線層３との接続抵抗が小さければ、小径部４ｂの開口径はなるべく小さい方が望ましい。   In FIG. 2B, the first insulating layer 2 is etched to form the small diameter portion 4b. The opening diameter of the small diameter portion 4b is smaller than the opening diameter of the large diameter portion 4a and is about 4 to 180 μm. If the connection resistance with the first wiring layer 3 is small, the opening diameter of the small diameter portion 4b is preferably as small as possible.

第１絶縁層２の材質がＳｉＯ２の場合、エッチングガスとしては、ＣＨＦ３ガスやＣＦ４ガス、Ｃ４Ｆ８ガス、Ａｒガス等の混合ガスを使用した。一般的に、酸化膜をエッチングする場合、フッ素や塩素ラジカルとの反応性がＳｉ等に比べてかなり小さいので、圧力を１〜１５Ｐａと高真空条件にしてイオン性の強いプラズマを生成させさらに基板バイアスを５０〜４００Ｗ程度印加することにより、ＣＦ系イオンを半導体基板１に引き込むことが可能にし、イオンアシストエッチングをする。しかし、イオンアシストエッチングでは、第１絶縁層２の下側に形成された材料との選択比があまり高くできないため、結果的に半導体基板１も一部エッチングしてしまう。よって、後工程で小径部４ｂに導電性材料を充填して形成される第３配線層１０３ａは、その一部が半導体基板１にめり込んだ構造になる。 When material of the first insulating layer 2 is SiO 2, as an etching gas, CHF3 gas or CF4 gas, C4F8 gas was a mixed gas such as Ar gas. In general, when etching an oxide film, the reactivity with fluorine and chlorine radicals is considerably smaller than that of Si or the like. By applying a bias of about 50 to 400 W, CF ions can be drawn into the semiconductor substrate 1 and ion-assisted etching is performed. However, in ion-assisted etching, the selectivity with respect to the material formed below the first insulating layer 2 cannot be so high, and as a result, the semiconductor substrate 1 is also partially etched. Therefore, the third wiring layer 103 a formed by filling the small diameter portion 4 b with a conductive material in a later process has a structure in which a part thereof is recessed into the semiconductor substrate 1.

従来例では、半導体基板１に大径部４ａを形成したあと小径部４ｂを形成し、半導体基板１の表裏の導通経路を形成するが、この実施例では先に小径部４ｂを形成する。従来の方法では、小径部４ｂを形成する際に上記のようにイオンアシストエッチングをするため、第１絶縁層２をエッチングした後、第１配線層３との選択比が確保できず、第１配線層３もかなりエッチングされることになる。第１配線層３がエッチングされると第１配線層表面から金属粒子が飛び出し、小径部４ｂの側壁に付着してしまい、結果として第１配線層と半導体基板１が導通してしまう。しかし、この実施の形態のように、大径部４ａの形成前に大径部４ａの開口径より小さい開口径を持つ小径部４ｂ、その貫通孔に第３配線層１０３ａを形成することにより、半導体基板１をＳＦ６ガス等でエッチングする条件で第３配線層１０３ａ（従来例では第１配線層）をエッチングしても第３配線層１０３ａがほとんどエッチングされないため第３配線層１０３ａから飛び出す金属粒子量を抑制することができ、また、半導体基板１との絶縁距離が確保できるため、半導体基板１と第３配線層１０３ａとの絶縁性を向上することができる。例えば、従来例のように第１貫通孔の底部面積と第３配線層１０３ａの面積が同じ（小径部４ｂと第１貫通孔の開口径が同じ）場合、或いは、第３配線層１０３ａの面積が第１貫通孔の底部面積より大きい場合は、半導体基板１と第３配線層１０３ａとの絶縁距離がほとんどないため、容易に電流リークが発生すると思われる。よって、第３配線層１０３ａの面積は第１貫通孔の底部の面積より小さいことが望ましい。   In the conventional example, after forming the large diameter portion 4a on the semiconductor substrate 1, the small diameter portion 4b is formed to form the conduction paths on the front and back of the semiconductor substrate 1. In this embodiment, the small diameter portion 4b is formed first. In the conventional method, since the ion-assisted etching is performed as described above when forming the small-diameter portion 4b, after the first insulating layer 2 is etched, the selection ratio with the first wiring layer 3 cannot be secured, and the first The wiring layer 3 is also etched considerably. When the first wiring layer 3 is etched, metal particles pop out from the surface of the first wiring layer and adhere to the side wall of the small diameter portion 4b. As a result, the first wiring layer and the semiconductor substrate 1 become conductive. However, as in this embodiment, by forming the third wiring layer 103a in the through hole, the small diameter portion 4b having an opening diameter smaller than the opening diameter of the large diameter portion 4a before the formation of the large diameter portion 4a, Even if the third wiring layer 103a (first wiring layer in the conventional example) is etched under the condition of etching the semiconductor substrate 1 with SF6 gas or the like, the third wiring layer 103a is hardly etched, so that the metal particles jump out of the third wiring layer 103a. Since the amount can be suppressed and the insulation distance from the semiconductor substrate 1 can be secured, the insulation between the semiconductor substrate 1 and the third wiring layer 103a can be improved. For example, when the bottom area of the first through hole and the area of the third wiring layer 103a are the same as in the conventional example (the small diameter portion 4b and the opening diameter of the first through hole are the same), or the area of the third wiring layer 103a Is larger than the bottom area of the first through hole, there is almost no insulation distance between the semiconductor substrate 1 and the third wiring layer 103a, so that current leakage is likely to occur easily. Therefore, the area of the third wiring layer 103a is preferably smaller than the area of the bottom of the first through hole.

図２（ｃ）では、アッシングや有機溶剤によってフォトレジスト１０１を除去する。
第１絶縁層に小径部４ｂを形成する加工方法として、ドライエッチング法のほかに、フッ酸等を用いたウェットエッチング法でもよい。エッチング加工用のマスクとしてフォトレジストを使用する説明をしたが、マスク材料としてＳｉＯ２やＳｉＮ等のハードマスクやＡｌやＮｉ等のメタルマスクでもよい。小径部４ｂの水平断面形状は、図１（ｂ）のように真円や、図１（ｃ）のように四角形等の多角形、または楕円でもよい。 In FIG. 2C, the photoresist 101 is removed by ashing or an organic solvent.
As a processing method for forming the small-diameter portion 4b in the first insulating layer, a wet etching method using hydrofluoric acid or the like may be used in addition to the dry etching method. Although description has been given of using a photoresist as a mask for etching processing, a hard mask such as SiO 2 or SiN or a metal mask such as Al or Ni may be used as a mask material. The horizontal cross-sectional shape of the small diameter portion 4b may be a perfect circle as shown in FIG. 1B, a polygon such as a rectangle as shown in FIG. 1C, or an ellipse.

また、一般的には、半導体基板１の一方の面１ａには、既にトランジスタやＣＭＯＳ回路等のデバイスが組み込まれている。その場合、後工程で、第１絶縁層２に小径部４ｂを形成し、Ｃｕ等の配線部を形成することになるので、小径部４ｂの形成のためにはマスクパターンを変更するだけでよく、工程の追加にはならない（従来第２の方法では、小径部４ｂ形成のためにレジスト形成工程が必要であり製造リードタイムが長くなってしまう）。   In general, a device such as a transistor or a CMOS circuit is already incorporated in one surface 1 a of the semiconductor substrate 1. In that case, since the small-diameter portion 4b is formed in the first insulating layer 2 and the wiring portion such as Cu is formed in the subsequent process, it is only necessary to change the mask pattern in order to form the small-diameter portion 4b. No additional process is required (the second conventional method requires a resist formation process for forming the small diameter portion 4b, resulting in a long manufacturing lead time).

図２（ｄ）では、小径部４ｂに導電性材料を充填するために第１絶縁層２の上に導電性材料１０３を成膜する。導電性材料として、Ｔｉ、Ｗ、Ｃｕ、Ｃｒ、Ａｕ、Ａｌ、Ａｇ、Ｎｉ等の金属材料やＴｉＮ等の金属化合物、ポリシリコン等のＳｉ系材料、あるいは上記材料の混合物であってもよい。また、成膜構造として、単層だけでなく２層以上の多層膜でも構わない。   In FIG. 2D, a conductive material 103 is formed on the first insulating layer 2 in order to fill the small diameter portion 4b with the conductive material. The conductive material may be a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, Ni, a metal compound such as TiN, a Si-based material such as polysilicon, or a mixture of the above materials. Further, the film formation structure may be not only a single layer but also a multilayer film of two or more layers.

図２（ｅ）では、ＣＭＰ工法やドライエッチング工法、ウェットエッチング工法により第１絶縁層２が露出するまで導電性材料１０３を除去し、第３配線層１０３ａを形成する。   In FIG. 2E, the conductive material 103 is removed until the first insulating layer 2 is exposed by a CMP method, a dry etching method, or a wet etching method, and a third wiring layer 103a is formed.

図２（ｆ）では、第１配線層３を形成するために、第１絶縁層２に小径部４ｂに充填したものと同じ導電性材料１０３を成膜する。導電性材料として、Ｔｉ、Ｗ、Ｃｕ、Ｃｒ、Ａｕ、Ａｌ、Ａｇ、Ｎｉ等の金属材料やＴｉＮ等の金属化合物、ポリシリコン等のＳｉ系材料、あるいは上記材料の混合物であってもよい。また、成膜構造として、単層だけでなく２層以上の多層膜でも構わない。   In FIG. 2 (f), in order to form the first wiring layer 3, the same conductive material 103 as that filled in the small diameter portion 4 b is formed on the first insulating layer 2. The conductive material may be a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, Ni, a metal compound such as TiN, a Si-based material such as polysilicon, or a mixture of the above materials. Further, the film formation structure may be not only a single layer but also a multilayer film of two or more layers.

図２（ｇ）では、導電性材料１０３の膜の上にフォトレジスト１０４を塗布し、フォトリソグラフィ工法によりパターニングする。フォトレジストはスピンコーティングにより形成する。その後、ドライエッチング工法等でエッチングして図２（ｈ）に示すように第１配線層３を得る。   In FIG. 2G, a photoresist 104 is applied on the film of the conductive material 103 and patterned by a photolithography method. The photoresist is formed by spin coating. Thereafter, etching is performed by a dry etching method or the like to obtain the first wiring layer 3 as shown in FIG.

図２（ｉ）では、フォトレジスト１０４をアッシングや有機溶剤によって除去する。
なお、第１配線層３を形成する加工方法として、ドライエッチング法のほかに、酢酸や硝酸等の酸性薬液やＮａＯＨ等のアルカリ性薬液、Ｈ２Ｏ２等を用いたウェットエッチング法でもよい。エッチング加工用のマスクとしてフォトレジストを使用する説明をしたが、マスク材料としてＳｉＯ２やＳｉＮ等のハードマスクやＡｌやＮｉ等のメタルマスクでもよい。 In FIG. 2I, the photoresist 104 is removed by ashing or an organic solvent.
The processing method for forming the first wiring layer 3 may be a wet etching method using an acidic chemical solution such as acetic acid or nitric acid, an alkaline chemical solution such as NaOH, H 2 O 2 or the like in addition to the dry etching method. Although description has been given of using a photoresist as a mask for etching processing, a hard mask such as SiO 2 or SiN or a metal mask such as Al or Ni may be used as a mask material.

図３（ａ）では、半導体基板１の他方の面１ｂにスピンコーティングによりフォトレジスト１０５を塗布し、フォトリソグラフィ工法により開口部１０６を形成する。一般的に、半導体基板に回路素子を作製してから貫通孔を形成し貫通電極を形成する場合（ビアラストと呼ばれる）、回路素子を形成されている方の半導体基板表面（この実施例では一方の面１ａ）にあるアライメントマークや貫通孔位置を認識した上で、半導体基板裏面（この実施例では他方の面１ｂ）のマスク合わせを行う両面露光法が使われている。従来の方法では、半導体基板に貫通孔を形成後、第１絶縁層２を開口するため、貫通孔とＡｌパッド等の第１配線との位置合わせ精度が求められる。しかし、この実施例のように、先に第１絶縁層２に第３配線層１０３ａを形成するため、貫通孔は第３配線層１０３ａの上に形成すればよい。つまり、第３配線層１０３ａが小さければ貫通孔位置合わせ精度が低くても貫通電極が形成できる。   In FIG. 3A, a photoresist 105 is applied to the other surface 1b of the semiconductor substrate 1 by spin coating, and an opening 106 is formed by photolithography. In general, when a through hole is formed after forming a circuit element on a semiconductor substrate (called via last), the surface of the semiconductor substrate on which the circuit element is formed (in this embodiment, one of the surfaces) A double-sided exposure method is used in which the alignment of the alignment mark and the through-hole position on the surface 1a) is recognized and the mask alignment of the back surface of the semiconductor substrate (the other surface 1b in this embodiment) is performed. In the conventional method, since the first insulating layer 2 is opened after the through hole is formed in the semiconductor substrate, the alignment accuracy between the through hole and the first wiring such as the Al pad is required. However, as in this embodiment, since the third wiring layer 103a is first formed in the first insulating layer 2, the through hole may be formed on the third wiring layer 103a. That is, if the third wiring layer 103a is small, the through electrode can be formed even if the through hole alignment accuracy is low.

図３（ｂ）では、フォトレジスト１０６をマスクにして半導体基板１をドライエッチングすることにより、大径部４ａを形成する。エッチングガスとしてはＳＦ６ガス（５０〜５００ｓｃｃｍ）に同程度以下のＯ２ガスを混合することによりＳＦ６への分圧を低下させ、半導体基板エッチングに作用するＦラジカルの発生を抑制することによって、イオン性の高いプラズマを生成した。さらに、圧力を１〜２０Ｐａと高真空条件にし、基板バイアスを２０〜２００Ｗ程度印加することにより、そのイオンを半導体基板１に引き込むことが可能になるため、異方性ドライエッチができる。エッチングは第３配線層１０３ａが露出されるまで行う。Ｆ系ガスを使用している場合、第３配線層１０３ａにＡｌ膜等を使用しているとほとんどエッチングされず、第３配線層１０３ａが薄膜化しない。さらに、第３配線層１０３ａの材料にＷ等を使用するなど、ドライエッチングが困難な材料を選択することで、第３配線層１０３ａの薄膜化を防止できる。 In FIG. 3B, the large diameter portion 4a is formed by dry etching the semiconductor substrate 1 using the photoresist 106 as a mask. As an etching gas, SF6 gas (50 to 500 sccm) is mixed with O 2 gas of the same degree or less to reduce the partial pressure to SF6, thereby suppressing generation of F radicals acting on semiconductor substrate etching. A high quality plasma was generated. Furthermore, anisotropic dry etching can be performed because the ions can be drawn into the semiconductor substrate 1 by applying a substrate bias of about 20 to 200 W under a high vacuum condition of 1 to 20 Pa. Etching is performed until the third wiring layer 103a is exposed. When an F-based gas is used, if an Al film or the like is used for the third wiring layer 103a, it is hardly etched and the third wiring layer 103a is not thinned. Furthermore, by selecting a material that is difficult to dry-etch, such as using W or the like as the material of the third wiring layer 103a, the third wiring layer 103a can be prevented from being thinned.

また、図４に示したように、半導体基板１の他方の面１ｂでの貫通孔径Ｄ４１は半導体基板の一方の面１ａでの貫通孔径Ｄ４２（＝大径部４ａ）の底部の孔径より大きいことが望ましい。理由は後工程で絶縁膜や金属膜等の成膜を実施する際に、貫通孔側壁や底部まで十分に成膜させることを可能にするためである。例えば、貫通孔４の側壁部が逆テーパ形状や垂直形状をしている場合、スパッタリング法により金属膜を成膜しようとしても貫通孔開口部が障害物となり、貫通孔底部や貫通孔側壁の底部近傍に金属粒子が飛んでいかないため成膜ができない。   Further, as shown in FIG. 4, the through hole diameter D41 on the other surface 1b of the semiconductor substrate 1 is larger than the hole diameter at the bottom of the through hole diameter D42 (= large diameter portion 4a) on the one surface 1a of the semiconductor substrate. Is desirable. The reason is that when forming an insulating film, a metal film, or the like in a subsequent process, it is possible to sufficiently form the film up to the side wall and bottom of the through hole. For example, when the side wall portion of the through hole 4 has a reverse taper shape or a vertical shape, the through hole opening portion becomes an obstacle even if a metal film is formed by sputtering, and the bottom portion of the through hole or the through hole side wall Film formation is impossible because metal particles do not fly nearby.

その後、アッシングや有機溶剤によってフォトレジスト１０５を除去することによって図３（ｃ）の状態になる。
図３（ｄ）では、ＣＶＤ法により第２絶縁層７を大径部４ａの内壁や底部、半導体基板の他方の面１ｂに形成する。絶縁膜材料としてはＳｉＮ、ＳｉＯ２、ＢＰＳＧ、熱酸化膜等のＳｉ酸化物やＡｌ２Ｏ３等の金属酸化物、またはポリイミド樹脂等のカーボン系ポリマーなどでもよい。また、第２絶縁層７は単層または２層以上の多層膜でも構わない。絶縁膜形成方法として、スパッタや熱酸化、ゾルゲル法により形成してもよい。 Thereafter, the photoresist 105 is removed by ashing or an organic solvent, so that the state shown in FIG.
In FIG. 3D, the second insulating layer 7 is formed on the inner wall and bottom of the large diameter portion 4a and the other surface 1b of the semiconductor substrate by the CVD method. As the insulating film material, Si oxide such as SiN, SiO 2 , BPSG, and thermal oxide film, metal oxide such as Al 2 O 3 , or carbon-based polymer such as polyimide resin may be used. The second insulating layer 7 may be a single layer or a multilayer film of two or more layers. As an insulating film forming method, it may be formed by sputtering, thermal oxidation, or sol-gel method.

図３（ｅ）では、大径部４ａの底部の第２絶縁層７をドライエッチング法により除去する。この場合も大径部４ａの形成時と同様、異方性ドライエッチングを用いるため、大径部４ａの側壁部に形成された第２絶縁層７は、ほとんどエッチングされないため残る。   In FIG. 3E, the second insulating layer 7 at the bottom of the large diameter portion 4a is removed by a dry etching method. Also in this case, since the anisotropic dry etching is used as in the formation of the large diameter portion 4a, the second insulating layer 7 formed on the side wall portion of the large diameter portion 4a remains because it is hardly etched.

また、図３（ｄ）において、一般的なＣＶＤ法を用いて第２絶縁層７を形成する場合、半導体基板１の他方の面１ｂの絶縁層膜厚は大径部４ａの底部での膜厚よりもかなり厚くなる。よって、大径部４ａの底部がエッチングされた時には半導体基板１の他方の面１ｂの第２絶縁層７は残っていることになる。   3D, when the second insulating layer 7 is formed using a general CVD method, the insulating layer thickness of the other surface 1b of the semiconductor substrate 1 is a film at the bottom of the large diameter portion 4a. It becomes considerably thicker than the thickness. Therefore, when the bottom of the large diameter portion 4a is etched, the second insulating layer 7 on the other surface 1b of the semiconductor substrate 1 remains.

図３（ｆ）では、スパッタ法やメッキ法により大径部４ａの底部と、半導体基板１の他方の面１ｂから大径部４ａの内周にかけて配線層を形成し、この配線層をパターニングして第２配線層５を形成する。   In FIG. 3F, a wiring layer is formed from the bottom of the large diameter portion 4a and the other surface 1b of the semiconductor substrate 1 to the inner periphery of the large diameter portion 4a by sputtering or plating, and this wiring layer is patterned. Thus, the second wiring layer 5 is formed.

図３（ｇ）では、大径部４ａの内周に形成されている第２配線層５の内側に絶縁体１５を充填させる。その第２配線層５を保護するための保護層８を第２配線層５の上に形成する。その後、その保護層８もパターニングして第２配線層５の一部を露出させ、その部分に外部回路と電気的に接続するための半田ボール等の導電部材９を形成する。   In FIG. 3G, the insulator 15 is filled inside the second wiring layer 5 formed on the inner periphery of the large diameter portion 4a. A protective layer 8 for protecting the second wiring layer 5 is formed on the second wiring layer 5. Thereafter, the protective layer 8 is also patterned to expose a part of the second wiring layer 5, and a conductive member 9 such as a solder ball for electrically connecting to an external circuit is formed in that part.

なお、図３（ｆ）での第２配線層５の形成方法は、スパッタ法やめっき法の他に印刷法やインクジェットによる塗布等でもよい。さらに、第２配線層５材料はＴｉ、Ｗ、Ｃｕ、Ｃｒ、Ａｕ、Ａｌ、Ａｇ、Ｎｉ等の金属材料やＴｉＮ等の金属化合物、ポリシリコン等のＳｉ系材料、又はそれらを含有した導電性材料でもよい。また、前記第２配線層５は単層又は２層以上の多層膜でも構わない。さらに錫、錫を含む合金やインジウム、インジウムを含む合金からなる低融点金属でもよい。   In addition, the formation method of the 2nd wiring layer 5 in FIG.3 (f) may be the printing method, the application | coating by an inkjet other than the sputtering method and the plating method. Further, the second wiring layer 5 material is a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, Ni, a metal compound such as TiN, a Si-based material such as polysilicon, or a conductive material containing them. It may be a material. The second wiring layer 5 may be a single layer or a multilayer film of two or more layers. Further, a low melting point metal made of tin, an alloy containing tin, indium, or an alloy containing indium may be used.

銅等のシード層と第２絶縁層７との間には、チタンやチタンタングステン、チタンナイトライド、タンタルナイトライドからなる拡散防止膜（図示せず）が形成されていてもよいし、形成されていなくてもよい。   A diffusion prevention film (not shown) made of titanium, titanium tungsten, titanium nitride, or tantalum nitride may be formed or formed between the seed layer such as copper and the second insulating layer 7. It does not have to be.

この構成によれば半導体基板１に形成された貫通孔４において、貫通孔４の形成前に、第１絶縁層に第３配線層１０３ａを形成することにより、第３配線層１０３ａの変形や破損、或いは完全除去を防止でき、さらに半導体基板１と第１配線層３の間の絶縁性を向上させ、その後に形成される貫通電極およびそれを設けた半導体や半導体パッケージの信頼性を向上させることができる。   According to this configuration, in the through hole 4 formed in the semiconductor substrate 1, the third wiring layer 103a is formed in the first insulating layer before the through hole 4 is formed, so that the third wiring layer 103a is deformed or damaged. Alternatively, complete removal can be prevented, and further, the insulation between the semiconductor substrate 1 and the first wiring layer 3 can be improved, and the reliability of the through electrode formed thereafter and the semiconductor or semiconductor package provided with the through electrode can be improved. Can do.

なお、この実施の形態１において、大径部４ａの内側に絶縁体１５を完全に充填したが、一部のみ充填しても構わないし無くてもよい。さらに、この実施の形態では、絶縁体１５と保護層８は別々だが、同一材料を用いて、絶縁体充填と保護層形成を同時に実施しても構わない。   In the first embodiment, the insulator 15 is completely filled inside the large diameter portion 4a. However, only a part of the insulator 15 may or may not be filled. Further, in this embodiment, the insulator 15 and the protective layer 8 are separate, but the same material may be used to simultaneously fill the insulator and form the protective layer.

また、図２（ｅ）のように、小径部４ｂを導電性材料により完全に充填し、第３配線層１０３ａを形成しているが、一部のみ充填しても構わない。
（実施の形態２）
図５と図６は本発明の実施の形態２の半導体基板を示している。 Further, as shown in FIG. 2E, the small diameter portion 4b is completely filled with the conductive material to form the third wiring layer 103a. However, only a part may be filled.
(Embodiment 2)
5 and 6 show a semiconductor substrate according to the second embodiment of the present invention.

実施の形態１の半導体基板では小径部４ｂは単一であったが、この実施の形態２では複数の小径部４ｂが半導体基板１に形成されている。その他は実施の形態１と同じである。
図５（ａ）に示すように、半導体基板１の厚さ方向にドライエッチングによって形成された大径部４ａは開口径が５μｍから２００μｍ程度で孔深さは１０μｍから４００μｍ程度の大きさであり、第１絶縁層２に大径部４ａの面積より小さな面積の開口径を有する小径部４ｂ，４ｂを形成し、第３配線層１０３ａが形成されている。小径部４ｂ，４ｂの水平断面は図５（ｂ）のように円弧でなくても、図５（ｃ）のように四角形等の多角形でもいい。 In the semiconductor substrate of the first embodiment, the small diameter portion 4 b is single, but in the second embodiment, a plurality of small diameter portions 4 b are formed in the semiconductor substrate 1. The rest is the same as in the first embodiment.
As shown in FIG. 5A, the large diameter portion 4a formed by dry etching in the thickness direction of the semiconductor substrate 1 has an opening diameter of about 5 μm to 200 μm and a hole depth of about 10 μm to 400 μm. Small diameter portions 4b and 4b having an opening diameter smaller than that of the large diameter portion 4a are formed in the first insulating layer 2, and a third wiring layer 103a is formed. The horizontal sections of the small diameter portions 4b and 4b may not be arcs as shown in FIG. 5B, but may be polygons such as quadrangles as shown in FIG.

実施の形態１の場合、第３配線層１０３ａが１ヵ所しか形成されないため、例えば、大径部４ａの形成後にパーティクル等が底部に堆積してしまうと、第３配線層１０３ａと第２配線層の密着性が低下し、配線抵抗が大きくなり、最悪膜剥がれが発生してしまう等、貫通電極としての信頼性が低くなることが予想される。そこで、複数の小径部４ｂを形成して図５（ａ）のように第３配線層１０３ａを複数形成することにより、仮に１か所の第３配線層１０３ａにおいて上記のような不具合が発生しても、他の導電端子により導通経路を確保することができる。さらに、複数開口部を形成することにより、貫通孔底部の凸凹構造を形成できるため、第２配線層５と第３配線層１０３ａとの密着力が向上すると思われる。   In the first embodiment, since only one third wiring layer 103a is formed, for example, if particles or the like are deposited on the bottom after the formation of the large diameter portion 4a, the third wiring layer 103a and the second wiring layer are formed. It is expected that the reliability of the through electrode will be lowered, such as the adhesiveness of the electrode is lowered, the wiring resistance is increased, and the worst film peeling occurs. Thus, by forming a plurality of small diameter portions 4b and forming a plurality of third wiring layers 103a as shown in FIG. 5A, the above-described problem occurs in one third wiring layer 103a. However, a conduction path can be secured by another conductive terminal. Furthermore, since the uneven structure at the bottom of the through hole can be formed by forming a plurality of openings, it is considered that the adhesion between the second wiring layer 5 and the third wiring layer 103a is improved.

なお、図５（ａ）では単一の第１配線層３について２つの第３配線層１０３ａを形成したが、図６に示すようにそれぞれの第３配線層１０３ａに対して独立した第１配線層３が接続されていてもよい。   In FIG. 5A, two third wiring layers 103a are formed for a single first wiring layer 3. However, as shown in FIG. 6, first wirings independent of each third wiring layer 103a are formed. Layer 3 may be connected.

この構成によれば半導体基板に形成された貫通孔において、貫通孔形成前に、第１絶縁層に第３配線層１０３ａを形成することにより、第３配線層１０３ａ（従来例では第１配線層）の変形や破損、或いは完全除去を防止でき、さらに半導体基板と第１配線層間の絶縁性を向上させ、その後に形成される貫通電極およびそれを設けた半導体や半導体パッケージの信頼性を向上させることができる。   According to this configuration, in the through hole formed in the semiconductor substrate, the third wiring layer 103a is formed in the first insulating layer before the through hole is formed, so that the third wiring layer 103a (the first wiring layer in the conventional example) is formed. ) Can be prevented from being deformed, damaged, or completely removed, and the insulation between the semiconductor substrate and the first wiring layer can be improved, and the through electrode formed thereafter and the reliability of the semiconductor or semiconductor package provided therewith can be improved. be able to.

（実施の形態３）
図７と図８はそれぞれ本発明の実施の形態３の半導体基板を示している。
実施の形態１との違いは、図７の場合には第１配線層３を形成しないことと、第３配線層１０３ａが第１絶縁層２の端面より突出した形にある。それ以外は実施の形態１と同じである。 (Embodiment 3)
7 and 8 show a semiconductor substrate according to the third embodiment of the present invention.
The difference from the first embodiment is that the first wiring layer 3 is not formed in the case of FIG. 7 and that the third wiring layer 103 a protrudes from the end face of the first insulating layer 2. The rest is the same as in the first embodiment.

更に、図８の場合には、第１配線層３を形成せずに、第３配線層１０３ａが第１絶縁層２の端面より突出した形状であるとともに、大径部４ａの内側に絶縁体１５を充填するのではなくて第２配線層５となる導電材料を充填して、この大径部４ａの内側に充填された第２配線層５の上に、半導体パッケージの回路素子を外部回路との接続に使用される導電部材９が設けられている。   Further, in the case of FIG. 8, without forming the first wiring layer 3, the third wiring layer 103a has a shape protruding from the end face of the first insulating layer 2, and an insulator is provided inside the large-diameter portion 4a. 15 is filled with a conductive material to be the second wiring layer 5, and the circuit element of the semiconductor package is placed on the second wiring layer 5 filled inside the large diameter portion 4a. The conductive member 9 used for connection with the is provided.

この図７と図８のように構成した半導体基板では、第３配線層１０３ａが外部回路等と直接接続することになる。図８の場合には、大径部４ａの内側に充填された第２配線層５の上に導電部材９を設けているため、貫通孔ピッチを短縮することができるようになる。   In the semiconductor substrate configured as shown in FIGS. 7 and 8, the third wiring layer 103a is directly connected to an external circuit or the like. In the case of FIG. 8, since the conductive member 9 is provided on the second wiring layer 5 filled inside the large diameter portion 4a, the through hole pitch can be shortened.

第１絶縁層２の端面より突出した形状の第３配線層１０３ａの具体的な形成方法は、ＣＭＰ等により、図２（ｅ）のように第３配線層１０３ａを第１絶縁層２内部に形成した後、ＣＨＦ３やＣＦ４ガスを用いたドライエッチング工法を適用し、第１絶縁層２のみを除去することにより形成できる。また、先に第３配線層１０３ａを形成したあと、第１絶縁層２を第３配線層１０３ａの周りに形成してもよい。具体的には、半導体基板１の上に導電膜層を形成し、その後パターニングにより第３配線層１０３ａを形成し、その後、全面に第１絶縁層２を形成し、その後、全面エッチングして第３配線層１０３ａを露出させる。   A specific method of forming the third wiring layer 103a having a shape protruding from the end face of the first insulating layer 2 is as follows. The third wiring layer 103a is placed inside the first insulating layer 2 as shown in FIG. After the formation, a dry etching method using CHF3 or CF4 gas is applied and only the first insulating layer 2 is removed. Alternatively, the first insulating layer 2 may be formed around the third wiring layer 103a after the third wiring layer 103a is formed first. Specifically, a conductive film layer is formed on the semiconductor substrate 1, and then the third wiring layer 103a is formed by patterning. Thereafter, the first insulating layer 2 is formed on the entire surface, and then the entire surface is etched to form the first wiring layer 103a. The three wiring layers 103a are exposed.

この構成によれば、大径部４ａの形成前に、第１絶縁層２に第３配線層１０３ａを形成することにより、第３配線層１０３ａ（従来例では第１配線層）の変形や破損、或いは完全除去を防止でき、さらに半導体基板と第１配線層間の絶縁性を向上させ、その後に形成される貫通電極およびそれを設けた半導体や半導体パッケージの信頼性を向上させることができる。   According to this configuration, by forming the third wiring layer 103a in the first insulating layer 2 before the formation of the large diameter portion 4a, the third wiring layer 103a (first wiring layer in the conventional example) is deformed or damaged. Alternatively, complete removal can be prevented, the insulation between the semiconductor substrate and the first wiring layer can be improved, and the reliability of the through electrode formed thereafter and the semiconductor or semiconductor package provided therewith can be improved.

（実施の形態４）
図９は本発明の実施の形態４を示す。
これは図８に示した半導体基板を２層に積層したものであって、実施の形態１との違いは、大径部４ａの内部もメッキ等の導電材料により埋め込み、孔全体で第２配線層を形成しており、その貫通孔の直上に導電部材９が形成され、さらに半導体基板１を半導体基板１の上に積層した形にある。それ以外は実施の形態１と同じである。 (Embodiment 4)
FIG. 9 shows a fourth embodiment of the present invention.
This is a laminate of the semiconductor substrate shown in FIG. 8 in two layers. The difference from the first embodiment is that the inside of the large-diameter portion 4a is also filled with a conductive material such as plating, and the second wiring is formed over the entire hole. The conductive member 9 is formed immediately above the through hole, and the semiconductor substrate 1 is laminated on the semiconductor substrate 1. The rest is the same as in the first embodiment.

この実施の形態４では半導体基板１，１を２層に積層する場合を示しているが、３層以上積層する場合もある。導電部材９は半田ボールや半田バンプ等で形成され、形状はこの実施の形態では直方体になっているが、柱状や球状であってもよい。しかし、複数の半導体基板の積層時に、あるいは積層基板を他の回路基板（図１１の基板１７を参照）へ実装する時に貫通電極に衝撃が加わり、大径部４ａの内部に形成された第２配線層５を介して第３配線層１０３ａに物理的ダメージが加わることによって、貫通電極の信頼性が低下するという新たな課題が想定されるが、この構成によれば半導体基板に形成された貫通孔において、第１絶縁層に貫通孔底部の面積より小さな開口径を有する小径部４ｂの中に第３配線層１０３ａを形成し、第１絶縁層２のエッチング時に発生する第１配線層３の薄膜化を防ぐことにより積層時の衝撃に対する耐久性が高くなるため、第３配線層１０３ａ（従来例では第２配線層）の変形や破損を防止でき、その後に形成される貫通電極およびそれを設けた半導体パッケージの信頼性を向上させることができる。   In the fourth embodiment, the semiconductor substrates 1 and 1 are stacked in two layers. However, in some cases, three or more layers are stacked. The conductive member 9 is formed of a solder ball, a solder bump, or the like, and has a rectangular parallelepiped shape in this embodiment, but may be a columnar shape or a spherical shape. However, when the plurality of semiconductor substrates are stacked or when the stacked substrate is mounted on another circuit substrate (see the substrate 17 in FIG. 11), an impact is applied to the through electrode, and the second formed in the large diameter portion 4a. A new problem that the reliability of the through electrode is lowered due to physical damage to the third wiring layer 103a through the wiring layer 5 is assumed. According to this configuration, the through hole formed in the semiconductor substrate is assumed. In the hole, the third wiring layer 103a is formed in the first insulating layer in the small diameter portion 4b having an opening diameter smaller than the area of the bottom of the through hole, and the first wiring layer 3 generated when the first insulating layer 2 is etched. By preventing the thinning, durability against impact during stacking is increased, so that deformation and breakage of the third wiring layer 103a (second wiring layer in the conventional example) can be prevented. Provided It is possible to improve the reliability of the conductor package.

（実施の形態５）
図１０は本発明の実施の形態５を示す。
実施の形態１との違いは、第１配線層３が存在せず、第３配線層１０３ａが小径部４ｂの中だけでなく第１絶縁層２上にも形成され、第１配線層３も兼ねていることである。この実施の形態５の第３配線層１０３ａの形成方法としては、ＣＶＤ法やスパッタリング工法、蒸着法などにより小径部４ｂの中と第１絶縁層２上に同時に導電性材料を成膜する。導電性材料として、Ｔｉ、Ｗ、Ｃｕ、Ｃｒ、Ａｕ、Ａｌ、Ａｇ、Ｎｉ等の金属材料やＴｉＮ等の金属化合物、ポリシリコン等のＳｉ系材料、あるいは上記材料の混合物であってもよい。また、その構造は単層だけでなく２層以上の多層膜でも構わない。次に、配線回路を形成するために、フォトレジストを塗布し、フォトリソグラフィ工法によりパターニングする。フォトレジストはスピンコーティングにより形成した。その後、ドライエッチング工法等で、配線回路を形成し、フォトレジストをアッシングや有機溶剤によって除去する。 (Embodiment 5)
FIG. 10 shows a fifth embodiment of the present invention.
The difference from the first embodiment is that the first wiring layer 3 does not exist, the third wiring layer 103a is formed not only in the small diameter portion 4b but also on the first insulating layer 2, and the first wiring layer 3 is also formed. It is also serving. As a method of forming the third wiring layer 103a of the fifth embodiment, a conductive material is simultaneously formed in the small diameter portion 4b and on the first insulating layer 2 by a CVD method, a sputtering method, a vapor deposition method, or the like. The conductive material may be a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, Ni, a metal compound such as TiN, a Si-based material such as polysilicon, or a mixture of the above materials. The structure may be not only a single layer but also a multilayer film of two or more layers. Next, in order to form a wiring circuit, a photoresist is applied and patterned by a photolithography method. The photoresist was formed by spin coating. Thereafter, a wiring circuit is formed by a dry etching method or the like, and the photoresist is removed by ashing or an organic solvent.

配線回路を形成する方法として、ドライエッチング法のほかに、酢酸や硝酸等の酸性薬液やＮａＯＨ等のアルカリ性薬液、Ｈ２Ｏ２等を用いたウェットエッチング法でもよい。エッチング加工用のマスクとしてフォトレジストを使用する説明をしたが、マスク材料としてＳｉＯ２やＳｉＮ等のハードマスクやＡｌやＮｉ等のメタルマスクでもよい。 As a method for forming the wiring circuit, in addition to the dry etching method, an acidic chemical solution such as acetic acid or nitric acid, an alkaline chemical solution such as NaOH, H 2 O 2, or the like may be used. Although description has been given of using a photoresist as a mask for etching processing, a hard mask such as SiO 2 or SiN or a metal mask such as Al or Ni may be used as a mask material.

また、この実施の形態では、小径部４ｂに充填されている導電性材料１０３の一部に窪み１０３ｂが形成されているが、完全に充填されていてもよい。しかし、第３配線層１０３ａをスパッタリング等で成膜する場合、小径部４ｂと第１絶縁層２上に同時に成膜するためその成膜される面積が広くなり、後工程でかかる熱ストレス等によって、導電性材料１０３と第１絶縁層２の材料の熱膨張係数が異なるため、導電性材料１０３と第１絶縁層２との密着力が減少し、最悪、膜剥がれが発生するという新たな課題が想定される。その場合は、ドライエッチング法等で、小径部４ｂの側壁部に凸凹部を形成するか、第１絶縁層２としてエッチングレートの異なる複数の絶縁層を積層させておくことにより、上と同様に小径部４ｂの側壁部に凸凹部を形成して膜密着力を向上させるとよい。また、第３配線層１０３ａと第１配線層３を同時に形成することにより、第３配線層１０３ａと第１配線層３との膜密着性の問題がなくなる。また、第３配線層１０３ａを形成する工程や第１配線層３を形成する工程の一部が省略できるため、製造リードタイムを短縮することができる。   In this embodiment, the depression 103b is formed in a part of the conductive material 103 filled in the small diameter portion 4b. However, the depression 103b may be completely filled. However, when the third wiring layer 103a is formed by sputtering or the like, since the film is formed on the small diameter portion 4b and the first insulating layer 2 at the same time, the area of the film is increased, which is caused by thermal stress applied in a later process. Since the thermal expansion coefficients of the conductive material 103 and the first insulating layer 2 are different from each other, the adhesion between the conductive material 103 and the first insulating layer 2 is reduced, and the new problem that the film peeling occurs in the worst case. Is assumed. In that case, a dry etching method or the like is used to form a convex / concave portion on the side wall portion of the small diameter portion 4b or to laminate a plurality of insulating layers having different etching rates as the first insulating layer 2 in the same manner as above. It is preferable to improve the film adhesion by forming convex and concave portions on the side wall portion of the small diameter portion 4b. Further, by forming the third wiring layer 103a and the first wiring layer 3 at the same time, the problem of film adhesion between the third wiring layer 103a and the first wiring layer 3 is eliminated. Further, part of the step of forming the third wiring layer 103a and the step of forming the first wiring layer 3 can be omitted, so that the manufacturing lead time can be shortened.

この構成によれば半導体基板に形成された第１貫通孔において、第１絶縁層に貫通孔底部の面積より小さな開口径を有する小径部４ｂの中に第３配線層１０３ａを備え、第３配線層１０３ａが第１配線層の機能を同時に果たすことにより、第３配線層１０３ａと第１配線層との密着性の問題がなくなるため、その後に形成される貫通電極およびそれを設けた半導体パッケージの信頼性を向上させることができる。さらに、第３配線層１０３ａを形成する工程や第１配線層を形成する工程の一部が省略できるため、製造リードタイムを短縮することができる。   According to this configuration, in the first through hole formed in the semiconductor substrate, the third wiring layer 103a is provided in the first insulating layer in the small diameter portion 4b having an opening diameter smaller than the area of the bottom of the through hole. Since the layer 103a performs the function of the first wiring layer at the same time, the problem of adhesion between the third wiring layer 103a and the first wiring layer is eliminated. Therefore, the through electrode formed thereafter and the semiconductor package provided with the through electrode Reliability can be improved. Furthermore, part of the step of forming the third wiring layer 103a and the step of forming the first wiring layer can be omitted, so that the manufacturing lead time can be shortened.

（実施の形態６）
図１１は本発明の実施の形態６における半導体パッケージの貫通電極部分の断面図である。 (Embodiment 6)
FIG. 11 is a cross-sectional view of the through electrode portion of the semiconductor package according to the sixth embodiment of the present invention.

実施の形態１との違いは、実施の形態１は半導体基板自身の構造についての実施例だが、実施の形態６はその半導体基板を樹脂成型した半導体パッケージの実施例である。
図１１に示すように、半導体基板１の厚さ方向にドライエッチングによって形成された貫通孔１は開口径が５μｍから２００μｍ程度で孔深さは１０μｍから４００μｍ程度の大きさであり、第１絶縁層に大径部４ａの底部の面積より小さな開口径を有する小径部４ｂの中に第３配線層１０３ａを形成し、その半導体基板がダイボンド材等で２層に積層されている。 The difference from the first embodiment is that the first embodiment is an example of the structure of the semiconductor substrate itself, but the sixth embodiment is an example of a semiconductor package in which the semiconductor substrate is resin-molded.
As shown in FIG. 11, the through hole 1 formed by dry etching in the thickness direction of the semiconductor substrate 1 has an opening diameter of about 5 μm to 200 μm and a hole depth of about 10 μm to 400 μm. A third wiring layer 103a is formed in a small-diameter portion 4b having an opening diameter smaller than the area of the bottom of the large-diameter portion 4a, and the semiconductor substrate is laminated in two layers with a die bond material or the like.

そのあと、基板１７にフリップチップ接合し、アンダーフィル材１８で接続部を保護した後、基板全体を樹脂１９で覆い、最後に半田ボール等の導電部材２０を搭載することにより半導体パッケージが形成される。   After that, after flip-chip bonding to the substrate 17 and protecting the connecting portion with the underfill material 18, the entire substrate is covered with a resin 19, and finally a conductive member 20 such as a solder ball is mounted to form a semiconductor package. The

この実施の形態６では２層の半導体基板１，１を積層する場合を示しているが、単層の場合もあるし、３層以上積層する場合もある。また、１つの半導体パッケージ内に積層された基板が１対形成されているが、２対以上形成されていてもよい。しかし、樹脂モールド形成時や本半導体パッケージを別のプリント基板等にリフロー等で接続する場合、パッケージ全体が高温にさらされ、貫通電極部分に多くの熱エネルギーがかかることが予想されるが、この構成によれば半導体基板に形成された貫通孔４において、第１絶縁層に貫通孔底部の面積より小さな面積の開口径を有する第３配線層１０３ａを形成することにより、第３配線層１０３ａ（従来例では第１配線層）の強度を向上させることができるため、半導体パッケージの信頼性を向上させることができる。   In the sixth embodiment, a case where two layers of semiconductor substrates 1 and 1 are stacked is shown, but there may be a single layer or three or more layers. In addition, one pair of substrates stacked in one semiconductor package is formed, but two or more pairs may be formed. However, when resin molds are formed or when this semiconductor package is connected to another printed circuit board or the like by reflow or the like, it is expected that the entire package will be exposed to high temperatures and a large amount of thermal energy will be applied to the through electrode part. According to the configuration, in the through hole 4 formed in the semiconductor substrate, the third wiring layer 103a (having an opening diameter smaller than the area of the bottom of the through hole is formed in the first insulating layer, whereby the third wiring layer 103a ( In the conventional example, since the strength of the first wiring layer) can be improved, the reliability of the semiconductor package can be improved.

なお、実施の形態１〜６で用いた半導体基板１の材質はシリコン、シリカゲルマニウム等のシリコン系半導体、あるいはガリウムヒ素 ガリウムナイトライド、インジウムリン等の化合物半導体である。   The material of the semiconductor substrate 1 used in the first to sixth embodiments is a silicon-based semiconductor such as silicon or silica gel, or a compound semiconductor such as gallium arsenide gallium nitride or indium phosphide.

本発明は、貫通電極を用いたデバイスの小型化、多段チップ積層技術の用途などに寄与する。   The present invention contributes to the miniaturization of devices using through electrodes, the use of multistage chip stacking technology, and the like.

本発明の実施の形態１における半導体基板の断面図と第３の配線層の水平断面図、第３の配線層の別の例の水平断面図Sectional view of semiconductor substrate, horizontal sectional view of third wiring layer, and horizontal sectional view of another example of third wiring layer in Embodiment 1 of the present invention 本発明の実施の形態１における半導体の貫通電極部分の形成工程図Process for forming a through electrode portion of a semiconductor in the first embodiment of the present invention 同実施の形態１における半導体の貫通電極部分の形成工程図Process for forming through electrode portion of semiconductor in the first embodiment 同実施の形態の貫通孔の寸法を説明する断面図Sectional drawing explaining the dimension of the through-hole of the embodiment 本発明の実施の形態２における半導体の貫通電極部分の断面図Sectional drawing of the penetration electrode part of the semiconductor in Embodiment 2 of this invention 同実施の形態の第１配線層の別の例を示す断面図Sectional drawing which shows another example of the 1st wiring layer of the embodiment 本発明の実施の形態３における半導体の貫通電極部分の断面図Sectional drawing of the penetration electrode part of the semiconductor in Embodiment 3 of this invention 同実施の形態の第２配線層の別の例の断面図Sectional drawing of another example of the 2nd wiring layer of the same embodiment 本発明の実施の形態４における半導体の貫通電極部分の断面図Sectional drawing of the penetration electrode part of the semiconductor in Embodiment 4 of this invention 本発明の実施の形態５における半導体の貫通電極部分の断面図Sectional drawing of the penetration electrode part of the semiconductor in Embodiment 5 of this invention 本発明の実施の形態６における半導体パッケージの貫通電極部分の断面図Sectional drawing of the penetration electrode part of the semiconductor package in Embodiment 6 of this invention 貫通電極を有する半導体基板をパッケージした半導体パッケージの断面図Cross-sectional view of a semiconductor package in which a semiconductor substrate having a through electrode is packaged 特許文献１の貫通電極形成の工程図Process drawing of forming through electrode of Patent Document 1 特許文献２の貫通電極形成の工程図Process drawing of forming through electrode of Patent Document 2

１ 半導体基板
１ａ 半導体基板１の一方の面
１ｂ 半導体基板１の他方の面
２ 第１絶縁層
３ 第１配線層
４ 貫通孔
４ａ 大径部（第１の開口部）
４ｂ 小径部（＝小径部４ｂ）
５ 第２配線層
７ 第２絶縁層
８ 保護膜
９ 導電部材
１５ 絶縁体
１８ アンダーフィル材
１９ 樹脂
２０ 導電部材
１０１ フォトレジスト
１０３ 導電性材料
１０３ａ 第３配線層
１０４ フォトレジスト
１０５ フォトレジスト
１０６ 開口部 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a One surface of the semiconductor substrate 1 1b The other surface of the semiconductor substrate 1 2 1st insulating layer 3 1st wiring layer 4 Through-hole 4a Large diameter part (1st opening part)
4b Small diameter part (= Small diameter part 4b)
5 Second Wiring Layer 7 Second Insulating Layer 8 Protective Film 9 Conductive Member 15 Insulator 18 Underfill Material 19 Resin 20 Conductive Member 101 Photoresist 103 Conductive Material 103a Third Wiring Layer 104 Photoresist 105 Photoresist 106 Opening

Claims (18)

半導体基板の一方の面に第１絶縁層を介して第１配線層が形成され、前記半導体基板を貫通する貫通孔の内周に第２配線層を形成した貫通電極を有する半導体基板であって、
前記貫通孔は、 前記半導体基板の他方の面から前記第１絶縁層に向かって形成された第１の開口部と、
前記第１の開口部よりも開口面積が小さく前記第１の開口部の底部から前記第１絶縁層を貫通して前記第１の配線層に達する第２の開口部とで形成され、
前記第２の開口部に第３配線層を設け、前記半導体基板の他方の面に達している前記第２配線層が、第３配線層を経て前記第１の配線層に電気接続されている
半導体基板。 A semiconductor substrate having a through electrode in which a first wiring layer is formed on one surface of a semiconductor substrate via a first insulating layer, and a second wiring layer is formed on the inner periphery of a through hole penetrating the semiconductor substrate. ,
The through hole includes a first opening formed from the other surface of the semiconductor substrate toward the first insulating layer;
A second opening having a smaller opening area than the first opening and reaching the first wiring layer from the bottom of the first opening through the first insulating layer;
A third wiring layer is provided in the second opening, and the second wiring layer reaching the other surface of the semiconductor substrate is electrically connected to the first wiring layer through the third wiring layer. Semiconductor substrate. 前記貫通孔の前記第１の開口部の周面にわたって第２絶縁層が形成され、
前記第２配線層と前記半導体基板の間に前記第２絶縁層が介在している
請求項１記載の半導体基板。 A second insulating layer is formed over a peripheral surface of the first opening of the through hole;
The semiconductor substrate according to claim 1, wherein the second insulating layer is interposed between the second wiring layer and the semiconductor substrate. 半導体基板の一方の面に第１絶縁層が形成され、前記半導体基板を貫通する貫通孔の内周に第２配線層を形成した貫通電極を有する半導体基板であって、
前記貫通孔は、前記半導体基板の他方の面から前記第１絶縁層に向かって形成された第１の開口部と、
前記第１の開口部よりも開口面積が小さく前記第１の開口部の底部から前記第１絶縁層を貫通する第２の開口部と、
前記第２の開口部に形成されて一端が前記第１絶縁層から突出した第３配線層とを有しており、前記半導体基板の他方の面に達している前記第２配線層が、第３配線層に電気接続されている
半導体基板。 A semiconductor substrate having a through electrode in which a first insulating layer is formed on one surface of the semiconductor substrate and a second wiring layer is formed on an inner periphery of a through hole penetrating the semiconductor substrate;
The through hole includes a first opening formed from the other surface of the semiconductor substrate toward the first insulating layer;
A second opening having a smaller opening area than the first opening and penetrating the first insulating layer from the bottom of the first opening;
A second wiring layer formed on the second opening and having one end protruding from the first insulating layer and reaching the other surface of the semiconductor substrate; A semiconductor substrate electrically connected to three wiring layers. 前記第２の開口部に導電材料を充填して前記第２配線層が形成され、前記第２の開口部に充填された前記第２配線層の上に外部回路と電気的に接続するための導電部材を備えた
請求項３記載の半導体基板。 The second wiring layer is formed by filling the second opening with a conductive material, and electrically connected to an external circuit on the second wiring layer filled in the second opening. The semiconductor substrate of Claim 3 provided with the electrically-conductive member. 前記第２配線層は、Ｔｉ、Ｗ、Ｃｕ、Ｃｒ、Ａｕ、Ａｌ、Ａｇ、Ｎｉ等の金属材料やＴｉＮ等の金属化合物、またはそれらを含有した導電性材料、ポリシリコン等のＳｉ系材料であり、前記第２配線層は単層または２層以上の多層膜である
請求項１または請求項３記載の半導体基板。 The second wiring layer is made of a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, Ni, a metal compound such as TiN, a conductive material containing them, or a Si-based material such as polysilicon. 4. The semiconductor substrate according to claim 1, wherein the second wiring layer is a single layer or a multilayer film of two or more layers. 前記第２絶縁層は、ＳｉＮ、ＳｉＯ２、ＢＰＳＧ、熱酸化膜等のＳｉ化合物やＡｌ２Ｏ３等の金属化合物、またはポリイミド樹脂等の有機化合物であり、また前記第２絶縁層は単層または２層以上の多層膜である
請求項２記載の半導体基板。 The second insulating layer is a Si compound such as SiN, SiO 2 , BPSG, or a thermal oxide film, a metal compound such as Al 2 O 3 , or an organic compound such as a polyimide resin, and the second insulating layer is a single layer. 3. The semiconductor substrate according to claim 2, wherein the semiconductor substrate is a multilayer film having two or more layers. 前記第２配線層上にその表面の一部を露出するように形成された保護膜と、
前記第２配線層上に外部回路と電気的に接続するための導電部材とを備える
請求項１記載の半導体基板。 A protective film formed on the second wiring layer so as to expose a part of the surface thereof;
The semiconductor substrate according to claim 1, further comprising a conductive member electrically connected to an external circuit on the second wiring layer. 前記貫通孔の内部に形成された空隙部の一部、または全体に絶縁材料が充填されている
請求項１記載の半導体基板。 The semiconductor substrate according to claim 1, wherein an insulating material is filled in a part or the whole of the gap formed inside the through hole. 前記第１の開口部の半導体基板１の他方の面１ｂの孔径は、前記第１の開口部の底部の孔径より大きい
請求項１または請求項３記載の半導体基板。 4. The semiconductor substrate according to claim 1, wherein a hole diameter of the other surface 1 b of the semiconductor substrate 1 of the first opening is larger than a hole diameter of the bottom of the first opening. 前記半導体基板が、シリコン、シリカゲルマニウム等のシリコン系半導体、あるいはガリウムヒ素、ガリウムナイトライド、インジウムリン等の化合物半導体である
請求項１または請求項３記載の半導体基板。 The semiconductor substrate according to claim 1 or 3, wherein the semiconductor substrate is a silicon-based semiconductor such as silicon or silica gel, or a compound semiconductor such as gallium arsenide, gallium nitride, or indium phosphide. 前記第３配線層は、Ｔｉ、Ｗ、Ｃｕ、Ｃｒ、Ａｕ、Ａｌ、Ａｇ、Ｎｉ等の金属材料やＴｉＮ等の金属化合物、ポリシリコン等のＳｉ系材料、あるいは上記材料の混合物であり、また前記第３配線層は単層又は２層以上の多層膜である
請求項１または請求項３記載の半導体基板。 The third wiring layer is a metal material such as Ti, W, Cu, Cr, Au, Al, Ag, Ni, a metal compound such as TiN, a Si-based material such as polysilicon, or a mixture of the above materials. 4. The semiconductor substrate according to claim 1, wherein the third wiring layer is a single layer or a multilayer film of two or more layers. 前記第３配線層と前記第１配線層は同一材料で構成されている
請求項１または請求項３記載の半導体基板。 4. The semiconductor substrate according to claim 1, wherein the third wiring layer and the first wiring layer are made of the same material. 前記第１絶縁層は、ＳｉＮ、ＳｉＯ２、ＢＰＳＧ、熱酸化膜等のＳｉ化合物やＡｌ２Ｏ３等の金属化合物であり、また前記絶縁層は単層または２層以上の多層膜である
請求項１または請求項３記載の半導体基板。 The first insulating layer is a Si compound such as SiN, SiO 2 , BPSG, or a thermal oxide film, or a metal compound such as Al 2 O 3, and the insulating layer is a single layer or a multilayer film of two or more layers. The semiconductor substrate according to claim 3. 請求項１から請求項１３の何れかに記載の半導体基板を内蔵した半導体パッケージ。   A semiconductor package incorporating the semiconductor substrate according to claim 1. 半導体基板の一方の面に第１絶縁層を形成する工程と、
第１絶縁層に形成されたレジストをマスクとして第１絶縁層をエッチングして第１絶縁層を貫通する第２の開口部を形成する工程と、
前記第２の開口部に第３配線層を形成する工程と、
前記第１絶縁層の上に前記第３配線層に導通する第１配線層を形成する工程と、
前記半導体基板の他方の面に形成されたレジストをマスクとして前記半導体基板をエッチングして前記半導体基板の他方の面から前記第３配線層が露出するように第２の開口部よりも開口面積が大きい第１の開口部を形成する工程と、
前記半導体基板の他方の面と前記第１の開口部の内側に第２絶縁層を形成する工程と、
前記第１の開口部の底部に形成された前記第２絶縁層を除去して前記第３配線層を露出させる工程と、
前記第１の開口部の内側に前記第３配線層に導通すると共に前記半導体基板の他方の面に達する第２配線層を形成する工程と
を有する半導体基板の製造方法。 Forming a first insulating layer on one surface of the semiconductor substrate;
Etching the first insulating layer using the resist formed in the first insulating layer as a mask to form a second opening penetrating the first insulating layer;
Forming a third wiring layer in the second opening;
Forming a first wiring layer electrically connected to the third wiring layer on the first insulating layer;
The semiconductor substrate is etched using a resist formed on the other surface of the semiconductor substrate as a mask so that the third wiring layer is exposed from the other surface of the semiconductor substrate so that the opening area is larger than the second opening. Forming a large first opening;
Forming a second insulating layer on the other surface of the semiconductor substrate and on the inside of the first opening;
Removing the second insulating layer formed at the bottom of the first opening to expose the third wiring layer;
Forming a second wiring layer which is electrically connected to the third wiring layer inside the first opening and reaches the other surface of the semiconductor substrate. 前記第２の開口部を形成する工程はドライエッチング工法やウェットエッチング工法により形成する
請求項１５記載の半導体基板の製造方法。 16. The method of manufacturing a semiconductor substrate according to claim 15, wherein the step of forming the second opening is formed by a dry etching method or a wet etching method. 前記第３配線層を形成する工程はＣＶＤ法やスパッタリング法、蒸着法等により形成する
請求項１５記載の半導体基板の製造方法。 16. The method of manufacturing a semiconductor substrate according to claim 15, wherein the step of forming the third wiring layer is formed by a CVD method, a sputtering method, a vapor deposition method, or the like. 前記第３配線層と前記第１配線層を同時に形成する
請求項１５記載の半導体基板の製造方法。 The method of manufacturing a semiconductor substrate according to claim 15, wherein the third wiring layer and the first wiring layer are formed simultaneously.
JP2009077897A 2009-03-27 2009-03-27 Semiconductor substrate, method of manufacturing semiconductor substrate, and semiconductor package Pending JP2010232400A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009077897A JP2010232400A (en) 2009-03-27 2009-03-27 Semiconductor substrate, method of manufacturing semiconductor substrate, and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009077897A JP2010232400A (en) 2009-03-27 2009-03-27 Semiconductor substrate, method of manufacturing semiconductor substrate, and semiconductor package

Publications (1)

Publication Number Publication Date
JP2010232400A true JP2010232400A (en) 2010-10-14

Family

ID=43047956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009077897A Pending JP2010232400A (en) 2009-03-27 2009-03-27 Semiconductor substrate, method of manufacturing semiconductor substrate, and semiconductor package

Country Status (1)

Country Link
JP (1) JP2010232400A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013219146A (en) * 2012-04-06 2013-10-24 Ulvac Japan Ltd Semiconductor device manufacturing method
WO2014038176A1 (en) * 2012-09-05 2014-03-13 株式会社デンソー Semiconductor device producing method
JP2014060265A (en) * 2012-09-18 2014-04-03 Win Semiconductors Corp Compound semiconductor integrated circuit
JP2014517534A (en) * 2011-06-06 2014-07-17 マイクロン テクノロジー， インク． Semiconductor structure having through-substrate interconnects and method for forming through-substrate interconnects
US8981532B2 (en) 2011-11-30 2015-03-17 Ps4 Luxco S.A.R.L. Semiconductor device and manufacturing method thereof
EP2893553A4 (en) * 2012-09-05 2016-05-11 Res Triangle Inst Electronic devices utilizing contact pads with protrusions and methods for fabrication
CN109390273A (en) * 2017-08-02 2019-02-26 三星电子株式会社 Semiconductor devices

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529483A (en) * 1991-07-19 1993-02-05 Rohm Co Ltd Semiconductor integrated device
JP2005294582A (en) * 2004-03-31 2005-10-20 Nec Electronics Corp Method of manufacturing semiconductor device
JP2006041450A (en) * 2004-07-27 2006-02-09 Zycube:Kk Semiconductor integrated circuit device and its manufacturing method
JP2006237594A (en) * 2005-01-31 2006-09-07 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
JP2007012854A (en) * 2005-06-30 2007-01-18 Shinko Electric Ind Co Ltd Semiconductor chip and its manufacturing method
JP2008210952A (en) * 2007-02-26 2008-09-11 Sanyo Electric Co Ltd Manufacturing method of semiconductor device, manufacturing method of silicone interposer and manufacturing method of semiconductor module
JP2008251721A (en) * 2007-03-29 2008-10-16 Fujikura Ltd Through wiring board and its manufacturing method
JP2009016773A (en) * 2007-07-02 2009-01-22 Spansion Llc Semiconductor device, and manufacturing method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529483A (en) * 1991-07-19 1993-02-05 Rohm Co Ltd Semiconductor integrated device
JP2005294582A (en) * 2004-03-31 2005-10-20 Nec Electronics Corp Method of manufacturing semiconductor device
JP2006041450A (en) * 2004-07-27 2006-02-09 Zycube:Kk Semiconductor integrated circuit device and its manufacturing method
JP2006237594A (en) * 2005-01-31 2006-09-07 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
JP2007012854A (en) * 2005-06-30 2007-01-18 Shinko Electric Ind Co Ltd Semiconductor chip and its manufacturing method
JP2008210952A (en) * 2007-02-26 2008-09-11 Sanyo Electric Co Ltd Manufacturing method of semiconductor device, manufacturing method of silicone interposer and manufacturing method of semiconductor module
JP2008251721A (en) * 2007-03-29 2008-10-16 Fujikura Ltd Through wiring board and its manufacturing method
JP2009016773A (en) * 2007-07-02 2009-01-22 Spansion Llc Semiconductor device, and manufacturing method thereof

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10121738B2 (en) 2011-06-06 2018-11-06 Micron Technology, Inc. Semiconductor constructions
US9583419B2 (en) 2011-06-06 2017-02-28 Micron Technology, Inc. Semiconductor constructions having through-substrate interconnects
JP2014517534A (en) * 2011-06-06 2014-07-17 マイクロン テクノロジー， インク． Semiconductor structure having through-substrate interconnects and method for forming through-substrate interconnects
US8981532B2 (en) 2011-11-30 2015-03-17 Ps4 Luxco S.A.R.L. Semiconductor device and manufacturing method thereof
JP2013219146A (en) * 2012-04-06 2013-10-24 Ulvac Japan Ltd Semiconductor device manufacturing method
JP2014067992A (en) * 2012-09-05 2014-04-17 Denso Corp Semiconductor device manufacturing method
CN104603918A (en) * 2012-09-05 2015-05-06 株式会社电装 Semiconductor device producing method
EP2893553A4 (en) * 2012-09-05 2016-05-11 Res Triangle Inst Electronic devices utilizing contact pads with protrusions and methods for fabrication
US9349644B2 (en) 2012-09-05 2016-05-24 Denso Corporation Semiconductor device producing method
WO2014038176A1 (en) * 2012-09-05 2014-03-13 株式会社デンソー Semiconductor device producing method
JP2014060265A (en) * 2012-09-18 2014-04-03 Win Semiconductors Corp Compound semiconductor integrated circuit
CN109390273A (en) * 2017-08-02 2019-02-26 三星电子株式会社 Semiconductor devices
CN109390273B (en) * 2017-08-02 2023-09-22 三星电子株式会社 Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Similar Documents

Publication Publication Date Title
TWI460836B (en) Conductive pillar for semiconductor substrate and method of manufacture
TWI458071B (en) Chip package and fabrication method thereof
US8324736B2 (en) Manufacturing process and structure of through silicon via
JP3972846B2 (en) Manufacturing method of semiconductor device
JP4492196B2 (en) Semiconductor device manufacturing method, circuit board, and electronic apparatus
JP2004297019A (en) Semiconductor device, circuit board, and electronic apparatus
TWI551199B (en) Substrate with electrical interconnector structure and manufacturing method thereof
KR20090076832A (en) Semiconductor apparatus and method for manufacturing the same
JP2012099548A (en) Method for manufacturing through wiring board and through wiring board
JP2010232400A (en) Semiconductor substrate, method of manufacturing semiconductor substrate, and semiconductor package
JP2006237594A (en) Semiconductor device and manufacturing method thereof
JP2007036060A (en) Semiconductor device and manufacturing method thereof
JP4765947B2 (en) Semiconductor device and manufacturing method thereof
TW202008539A (en) Assembly structure, method of bonding using the same, and circuit board therefor
CN108666284A (en) The manufacturing method and semiconductor device of semiconductor device
JP2007180303A (en) Semiconductor device and manufacturing method thereof, and electronic apparatus
TW201644016A (en) Chip package and manufacturing method thereof
JP2007221080A (en) Semiconductor device, and method for manufacturing same
JP5460069B2 (en) Semiconductor substrate, semiconductor package, and semiconductor substrate manufacturing method
JP4155154B2 (en) Semiconductor device, circuit board, and electronic device
JP2010205921A (en) Semiconductor apparatus, and method of manufacturing semiconductor apparatus
JP2006041148A (en) Method for manufacturing semiconductor device, semiconductor device, and electronic apparatus
JP5091962B2 (en) Semiconductor device
JP5873145B2 (en) Method for manufacturing through wiring board
JP2004281793A (en) Semiconductor device and its manufacturing method, circuit board, and electronic equipment

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120110

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130730

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130806

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130926

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140415