JP2014060265A - Compound semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor integrated circuit including a number of metal layers each composed of at least one Cu layer.SOLUTION: A compound semiconductor integrated circuit comprises: a substrate; at least one compound semiconductor electronic device; a first metal layer; a protective layer, a plurality of second metal layers and at least one dielectric layer. The first metal layer contains Au and is electrically connected at least partially to the compound semiconductor electronic device. The protective layer covers the compound semiconductor electronic device and at least a part of the first metal layer. Each layer of the plurality of second metal layers at least contains a Cu layer and at least a part of the second metal layers is electrically connected to the first metal layer. The at least one dielectric layer isolate the second metal layers adjacent to each other. The second metal layer is used for formation of a passive electronic component.

Description

  The present invention relates to a compound semiconductor integrated circuit, and more particularly to a compound semiconductor integrated circuit including a plurality of metal layers each composed of at least a Cu layer.

  In recent years, compound semiconductor monolithic microwave integrated circuits (MMICs) have been widely applied to mobile communication and sensor devices, which has increased the demand for highly integrated and high performance MMICs. Conventionally, electronic components in MMIC, such as transistors, capacitors, resistors, inductors, and transmission lines, are arranged two-dimensionally. For high integration of devices, 3DMMIC has been developed in which passive components are three-dimensionally arranged on a compound semiconductor device. In the compound semiconductor MMIC, Au is generally used for passive components and interconnections in order to prevent cross contamination. However, the high cost of Au limits the thickness of passive components. For example, with respect to transmission lines, Au transmission lines used in 3DMMIC are smaller in width than those used in conventional MMICs, which increases resistance and may cause signal loss and excess noise. Circuit performance such as power gain in the power amplifier and noise figure in the low-noise amplifier is degraded by an increase in the resistance of the transmission line. To improve circuit performance, the thickness of the Au layer must be increased, which increases the overall manufacturing cost significantly. Therefore, the circuit performance using the Au metal layer is limited by the price of Au. The price of Cu is very cheap compared to Au, and the electrical conductivity and thermal conductivity of Cu are also very good. Therefore, it is preferable to develop a 3DMMIC structure in which Au is replaced with Cu.

  The main object of the present invention is to provide a compound semiconductor integrated circuit comprising a large number of metal layers, each layer comprising at least one Cu layer. The multiple metal layers can be used to form passive electronic components that are three-dimensionally formed on other devices. By using Cu for the compound semiconductor integrated circuit, the conductivity can be improved and the material cost can be reduced. Furthermore, since Cu is low in cost, it is possible to produce a thicker metal layer that significantly reduces the resistance of the metal layer.

  To achieve the above object, the present invention provides a compound comprising a substrate, at least one compound semiconductor electronic device, a first metal layer, a protective layer, a plurality of second metal layers, and at least one dielectric layer. A semiconductor integrated circuit is provided. The first metal layer contains Au and does not contain Cu, and is at least partially electrically connected to the compound semiconductor electronic device. The protective layer covers the compound semiconductor electronic device and at least a part of the first metal layer. Each of the plurality of second metal layers includes at least a Cu layer, and at least a part of the second metal layer is electrically connected to the first metal layer. Each set of adjacent second metal layers is separated by a dielectric layer.

  Another object of the present invention is to provide a compound semiconductor integrated circuit comprising a large number of metal layers, each layer consisting of at least one Cu layer, and a back surface metal layer used for ground connection of the electronic device by through-substrate via holes. In this way, this ground connection can be made in the vicinity of the device, which improves the power gain of the electronic device.

  In order to achieve the above-described object, the compound semiconductor integrated circuit provided by the present invention further includes a back metal layer, the substrate further includes at least one through-substrate via hole, and the through-substrate via hole includes the substrate. The back metal layer covers the inner surface of the through-substrate via hole and at least a part of the back surface of the substrate.

  In practice, the substrate described above consists of GaAs, SiC or sapphire.

  In practice, the compound semiconductor electronic device described above is a FET or HBT.

  In practice, the compound semiconductor electronic device described above is a GaN FET.

  In practice, the thickness of the Cu layer described above is 3 μm or more.

  In practice, the plurality of second metal layers described above form at least one ground.

  In practice, the dielectric layer described above comprises a PBO (polybenzoxazole) dielectric material.

  In implementation, the thickness of the dielectric layer made of PBO is 10 μm or more and 30 μm or less.

  In practice, the protective layer described above consists of SiN.

  In practice, the second metal layer described above forms a microstrip line, a coupler or an inductor.

  In practice, the back metal layer described above is at least partially made of Cu.

  The present invention will be more fully understood with reference to the following drawings and detailed description of the preferred embodiments.

It is the schematic which shows sectional drawing of one Embodiment of this invention. It is the schematic which shows sectional drawing of other embodiment of this invention. 1 is a circuit diagram of a low noise amplifier provided by the present invention. FIG. 4 is a schematic diagram showing a top view of the layout of the low noise amplifier shown in FIG. 3. FIG. 4 is a schematic diagram showing a top view of the layout of the low noise amplifier shown in FIG. 3.

  FIG. 1 illustrates a book comprising a substrate 101, at least one compound semiconductor electronic device 110, a first metal layer 120, a protective layer 130, a plurality of second metal layers 140, and at least one dielectric layer 150. It is the schematic which shows sectional drawing of one Embodiment of the compound semiconductor integrated circuit concerning invention. The substrate 101 is made of a semi-insulating or insulating material such as GaAs, SiC or sapphire. The compound semiconductor electronic device 110 is formed on the substrate 101. The compound semiconductor electronic device 110 can be an FET or HBT mainly made of GaAs. The compound semiconductor electronic device 110 may be a GaN FET. The first metal layer 120 is formed on the compound semiconductor electronic device 110 and is at least partially electrically connected to the compound semiconductor electronic device 110. The first metal layer 120 can be used to form passive electronic components such as the electrode 121, the capacitor 122, or the resistor of the compound semiconductor electronic device 110. The first metal layer 120 includes Au, and a contact region between the first metal layer 120 and the compound semiconductor electronic device 110 is made of Au or Au having a thin adhesive metal such as Ti underneath. Cu easily diffuses into a compound semiconductor such as GaAs and forms a carrier trap level. Therefore, when a metal layer containing Cu is brought into direct contact with a compound semiconductor electronic device, device characteristics are deteriorated. However, by forming the electrical connection mainly through a metal layer made of Au and not containing Cu, contamination of the compound semiconductor electronic device due to Cu can be prevented. The protective layer 130 covers the compound semiconductor electronic device 110 and at least a part of the first metal layer 120, and the electronic device 110 is a layer made of another material, particularly a layer containing Cu. The plurality of second metal layers 140 are separated from each other. The protective layer 130 is preferably made of SiN. At least one of the plurality of second metal layers 140 is at least partially electrically connected to the first metal layer 120, and the thickness of the Cu layer in the second metal layer 140 is 3 μm or more. It can be. The second metal layer 140 may be used to form at least one ground 141 and other passive electronic components such as a microstrip line 142, a coupler 143, or an inductor 144. Two adjacent second metal layers 140 are separated by a dielectric layer 150. The dielectric layer 150 should be thick enough to separate the electronic devices 110, 122, and 123 from the metal layer so that the effect of capacitive or inductive coupling on device performance is reduced. I must. The film thickness of the PBO (polybenzoxazole) dielectric material can be increased even after curing. In addition, the moisture resistance and layer stress resistance of PBO is superior to typical dielectric materials such as polyimide and BCB. The dielectric layer 150 is preferably made of a PBO (polybenzoxazole) dielectric material, and the distance between the two second metal layers 140 is in the range of 10 to 30 μm.

  FIG. 2 is a schematic diagram showing a cross-sectional view of another embodiment of the compound semiconductor integrated circuit according to the present invention, in which the structure shown in FIG. 1 is further provided with a back metal layer 160 and at least one through-substrate via hole 161. . The through-substrate via hole 161 passes through the substrate 101. The back metal layer 160 covers the inner surface of the through-substrate via hole 161 and at least a part of the back surface of the substrate 101. The back metal layer 160 is preferably made of Cu at least partially from the viewpoint of reducing electrical resistance and reducing material costs. In this embodiment, the back metal layer 160 can be used as a ground connection for the electronic device connected via the through-substrate via hole 161.

  FIG. 3 is a circuit diagram of a two-stage low noise amplifier provided by the present invention. This circuit includes two active electronic devices 110, microstrip lines 142a to 142g, capacitors 122, resistors 123, RF input terminals, RF output terminals, ground 141, and backside metal used for ground connection. Layer 160. The electronic device is a 0.15 μm gate pHEMT. The microstrip line is used for impedance / noise matching and DC bias. 4A and 4B are schematic diagrams showing a top view of the layout of the low noise amplifier circuit in the broken line region and the alternate long and short dash line region of FIG. FIG. 4A shows a top view of the layout of the first stage (dashed area) of the amplifier. The microstrip line 142a is a short stub for applying a bias to the gate electrode of the pHEMT. Microstrip lines 142b and 142c are used to obtain noise matching. The microstrip line 142d is used to obtain impedance matching at the output of the pHEMT. The microstrip lines 142a, 142c and 142d are formed above the ground 141. A layout in which microstrip lines are closely packed in a small area is thus achieved. FIG. 4B shows a top view of the layout of the second stage (dashed line area) of the amplifier. The microstrip lines 142e and 142f are used to obtain impedance matching at the time of input and output of the pHEMT, respectively. The microstrip line 142g is a short stub for applying a bias to the drain of the pHEMT. Also, these microstrip lines are formed above the ground, enabling a dense layout in a small area. The pHEMT uses a through-substrate via hole 161 that facilitates the formation of a source ground connection on the back metal layer 160 in the vicinity of the electronic device. In this embodiment, the distance between the ground 141 and the microstrip line is about 10 μm. The thickness of the Cu layer of the ground 141 and the microstrip line is about 3 μm, and the width of the microstrip line is about 15 μm. In this case, the spacing between two adjacent microstrip lines can be as small as 30 μm. The metal sheet resistance is reduced by a factor of 2 for the 3 μm Cu layer compared to the 2 μm Au layer. In a conventional design using Au microstrip lines, the low noise amplifier has a gain of 15 dB with a noise figure of 3.0 dB. In the low noise amplifier using Cu microstrip lines provided by the present invention, the noise figure improvement is over 1 dB compared to the conventional design.

In summary, the present invention certainly achieves the aforementioned object of providing a compound semiconductor integrated circuit comprising a number of metal layers, each layer comprising at least one Cu layer. The present invention has the following advantages:
1. The thick Cu layer provided by the present invention can reduce the resistance of thin microstrip lines formed using Au in the prior art. Excess losses and excess noise caused by high resistance can be reduced, and besides, the high conductivity of Cu further improves the performance of the integrated circuit.
2. Compared to the use of Au, the use of Cu significantly reduces the manufacturing cost of the metal plate production by approximately 50% or more.
3. By using Au for electrical connection with the compound semiconductor device, it is possible to prevent the performance from being deteriorated by contamination with Cu.
4). By using a PBO dielectric layer for the interlayer insulation of the metal layer, a thick film can be formed, and the influence of the upper metal layer on the lower electronic device can be suppressed and the moisture resistance and mechanical stability can be improved.
5. By using the through-substrate via hole for the ground connection of the electronic device, it becomes possible to perform the ground connection in the vicinity of the device, thereby increasing the power gain of the electronic device.

  The above description with reference to the drawings is only for the preferred embodiment of the present invention. Many equivalent local variations and modifications can be made by those skilled in the art to which the invention pertains, which do not depart from the spirit of the invention and fall within the scope defined by the appended claims. Should be considered.

Claims (20)

A substrate,
At least one compound semiconductor electronic device formed on the substrate;
A first metal layer comprising Au formed on the compound semiconductor electronic device and at least partially electrically connected to the compound semiconductor electronic device;
A protective layer covering at least part of the compound semiconductor electronic device and the first metal layer;
A plurality of second metal layers, each layer including at least a Cu layer, formed on the protective layer, and at least one layer partially electrically connected to the first metal layer When,
A compound semiconductor integrated circuit comprising at least one dielectric layer separating adjacent second metal layers.   2. The compound semiconductor integrated circuit according to claim 1, wherein the substrate is made of GaAs, SiC or sapphire.   The compound semiconductor integrated circuit according to claim 1, wherein the compound semiconductor electronic device is an FET or an HBT.   The compound semiconductor integrated circuit according to claim 1, wherein the compound semiconductor electronic device is a GaN FET.   The compound semiconductor integrated circuit according to claim 1, wherein the thickness of Cu is 3 μm or more.   The compound semiconductor integrated circuit according to claim 1, wherein the plurality of second metal layers form at least one ground.   2. The compound semiconductor integrated circuit according to claim 1, wherein the dielectric layer is made of a PBO (polybenzoxazole) dielectric material.   8. The compound semiconductor integrated circuit according to claim 7, wherein the dielectric layer has a thickness in the range of 10 μm to 30 μm.   The compound semiconductor integrated circuit according to claim 1, wherein the protective layer is made of SiN.   The compound semiconductor integrated circuit according to claim 1, wherein the second metal layer forms a microstrip line, a coupler, or an inductor. The compound semiconductor integrated circuit according to claim 1, further comprising a back metal layer, wherein the substrate further includes at least one through-substrate via hole.
The substrate through via hole penetrates the substrate,
The back metal layer is a compound semiconductor integrated circuit that covers an inner surface of the through-substrate via hole and at least a part of the back side of the substrate.   The compound semiconductor integrated circuit according to claim 11, wherein the back metal layer is at least partially made of Cu.   The compound semiconductor integrated circuit according to claim 11, wherein the substrate is made of GaAs, SiC, or sapphire.   The compound semiconductor integrated circuit according to claim 11, wherein the compound semiconductor electronic device is an FET or an HBT.   The compound semiconductor integrated circuit according to claim 11, wherein the compound semiconductor electronic device is a GaN FET.   The compound semiconductor integrated circuit according to claim 11, wherein the thickness of Cu is 3 μm or more.   12. The compound semiconductor integrated circuit according to claim 11, wherein the dielectric layer is made of a PBO (polybenzoxazole) dielectric material.   The compound semiconductor integrated circuit according to claim 17, wherein the dielectric layer has a thickness in a range of 10 μm to 30 μm.   The compound semiconductor integrated circuit according to claim 11, wherein the protective layer is made of SiN.   The compound semiconductor integrated circuit according to claim 11, wherein the second metal layer forms a microstrip line, a coupler, or an inductor.

Images