JPH04302166A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device in which a high-resistance element is formed on a semiconductor substrate in a small space. CONSTITUTION:The method of manufacturing the above semiconductor device has process of forming a first conductor wiring 3 on a first interlayer insulating film 2 formed on a semiconductor substrate 1, a process of forming a second interlayer insulating film 4 thereon, a process of forming a second conductor wiring 5 on the film 4, a process of forming a third interlayer insulating film 6 thereon, a process of forming a hole 7 reaching from the surface of this film 6 the film 2 and a process of filling this hole 7 with a conductor 8.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for easily forming a high resistance element on a semiconductor substrate in a small space.

0002

2. Description of the Related Art As semiconductor integrated circuits become more highly integrated, it has become necessary to miniaturize each circuit element. A conventional method for manufacturing a semiconductor device for forming a high resistance element will be described below. FIG. 3 is a cross-sectional view of a high resistance element for explaining a conventional method of manufacturing a semiconductor device. After a polycrystalline silicon film is formed on a silicon oxide film 2 formed on a semiconductor substrate 1, phosphorus (P) is diffused into the polycrystalline silicon film, and conductive wiring 3 is formed by photolithography and etching. A plan view of the high resistance element formed in this way is shown in FIG.
Using specific resistance ρ, cross-sectional area S and length L, R=ρ(L
/S), and in order to increase the resistance value R, it is necessary to decrease the cross-sectional area S or increase the length L.

0003

However, in the above-mentioned conventional configuration, in order to obtain high resistance, a large space must be taken for forming the conductor wiring 3, which has the problem of hindering high integration. was.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can narrow the space for forming a high-resistance element even with the same design standards as the conventional method. .

[0005]

SUMMARY OF THE INVENTION In order to achieve this object, the method for manufacturing a semiconductor device of the present invention includes alternately forming conductive wiring and an insulating film on a first insulating film formed on a semiconductor substrate. A hole is formed from the uppermost insulating film to the first insulating film at the folding point of the conductor wiring, and the conductor wiring is interconnected by filling this hole with a conductor.

[0006]

[Operation] With this structure, the conductor wiring can be stacked and the conductor wiring can be folded back at the intermediate point, so a high resistance element can be formed in about half the space compared to the conventional method.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a high resistance element for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. First, on a first interlayer insulating film 2 made of a silicon oxide film or the like formed on a semiconductor substrate 1, a polycrystalline silicon film which will become a first conductor wiring 3 after patterning is formed. Phosphorus (P) is diffused into this polycrystalline silicon film to adjust the sheet resistance to 3 to 7Ω. Next, the first conductor wiring 3 is formed by photolithography and etching. Next, a second interlayer insulating film 4 made of a silicon oxide film or the like is formed. Next, a polycrystalline silicon film that will later become the second conductor wiring 5 is formed on this second interlayer insulating film 4,
Diffuse phosphorus (P) and adjust sheet resistance to 3-7Ω. Next, a second conductor wiring 5 is formed by photolithography and etching so as to overlap the first conductor wiring 3. Next, after forming the third interlayer insulating film 6, a hole 7 extending from the surface to at least the first conductor wiring 3 is formed. Next, the hole 7 is filled with an aluminum film 8 to connect the first conductor wiring 3 and the second conductor wiring 5.

FIG. 2 is a plan view of the high resistance element formed by the above steps. As shown in FIG. 2, the first conductor wiring 3 and the second conductor wiring 5 overlap, and the terminal of the high resistance element is connected to the end 3a of the first conductor wiring 3 and the end of the second conductor wiring 5. 5a, and the turning point is the hole 7. FIG. 1 is a diagram obtained by cutting FIG. 2 along line A-B.

Although silicon oxide films are used as the interlayer insulating films 2, 4, and 5 in this embodiment, other insulating films such as silicon nitride films may be used. In addition, the first conductor wiring 3
Although the aluminum film 8 is used to connect the second conductor wiring 5 to the second conductor wiring 5, a film made of a high melting point metal such as molybdenum or tungsten or a silicide thereof may also be used. Furthermore, if folding points and patterning are considered, the present invention is not limited to a two-layer wiring structure, but can also be applied to a three-layer wiring structure or a four-layer wiring structure.

0010

As described above, the present invention alternately stacks conductive wiring and insulating films on a first insulating film formed on a semiconductor substrate, and at the folding point of the conductive wiring, the uppermost layer By forming a hole reaching from the insulating film to the first insulating film and filling this hole with a conductor to interconnect the conductor wiring, the conductor wiring can be stacked, and the conductor wiring can be stacked. Since it can be folded back at a point, it is possible to realize an excellent method for manufacturing a semiconductor device that can form a high-resistance element in about half the space compared to the conventional method.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a high resistance element for explaining a method of manufacturing a semiconductor device in an embodiment of the present invention.

[Figure 2] Plan view of the same high resistance element

[Figure 3] Cross-sectional view of a high-resistance element to explain a conventional method of manufacturing a semiconductor device

[Figure 4] Plan view of the same high resistance element

[Explanation of symbols]

1 Semiconductor substrate 2 First interlayer insulating film 3 First conductor wiring 4 Second interlayer insulating film 5 Second conductor wiring 6 Third interlayer insulating film 7 Hole 8 Conductor

Claims (1)

[Claims] 1. A step of forming a first wiring film on a first interlayer insulating film formed on a semiconductor substrate, and then patterning the wiring film to form a first conductor wiring. , forming a second interlayer insulating film on at least the first conductor wiring; and after forming a second wiring film on the second interlayer insulating film, patterning the second wiring film; a step of forming a second conductor wiring by
forming a third interlayer insulating film on the conductor wiring;
A method for manufacturing a semiconductor device, comprising: forming a hole from the surface of the third interlayer insulating film to the first interlayer insulating film; and filling the hole with a conductor.