JPH03120826A - Formation of metal wiring of semiconductor device - Google Patents
Formation of metal wiring of semiconductor deviceInfo
- Publication number
- JPH03120826A JPH03120826A JP26042589A JP26042589A JPH03120826A JP H03120826 A JPH03120826 A JP H03120826A JP 26042589 A JP26042589 A JP 26042589A JP 26042589 A JP26042589 A JP 26042589A JP H03120826 A JPH03120826 A JP H03120826A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal wiring
- heat treatment
- silicon dioxide
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 35
- 239000002184 metal Substances 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000001257 hydrogen Substances 0.000 claims abstract description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 52
- 229910052782 aluminium Inorganic materials 0.000 claims description 19
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 3
- 238000007493 shaping process Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 34
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 17
- 239000000377 silicon dioxide Substances 0.000 abstract description 17
- 238000009792 diffusion process Methods 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 230000000087 stabilizing effect Effects 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 150000002431 hydrogen Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の金属配線形成方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for forming metal wiring in a semiconductor device.
従来、半導体集積回路などの半導体装置の金属配線はア
ルミニウムを主成分とする金属が用いられている。アル
ミニウムを主成分とした金属配線を用いた従来技術につ
いて第3図を用いて説明する。Conventionally, metal wiring of semiconductor devices such as semiconductor integrated circuits has been made of a metal containing aluminum as a main component. A conventional technique using metal wiring mainly composed of aluminum will be explained with reference to FIG.
第3図(a)〜(e)は従来の半導体装置の金属配線形
成方法を説明するための工程順に配置した半導体チップ
の縦断面図である。FIGS. 3A to 3E are vertical cross-sectional views of semiconductor chips arranged in the order of steps for explaining a conventional method of forming metal wiring in a semiconductor device.
まず、第3U(a>に示すように、P型シリコン基板1
上にトランジスタ等の機能素子(N型拡散層4を代表と
して示す)を形成後公知のCVD技術を用い厚さ0.8
μmの二酸化シリコン膜2を成長させ、機能素子間の接
続等の為コンタクトホールを開孔する。そして、アルミ
ニウム膜3を厚さ1.0μm被着後公知のホトエツチン
グの技術を用いてアルミニウム配線に整形する。First, as shown in the 3rd U (a>), a P-type silicon substrate 1
After forming a functional element such as a transistor (the N-type diffusion layer 4 is shown as a representative) on top, it is deposited to a thickness of 0.8 mm using a known CVD technique.
A silicon dioxide film 2 having a thickness of μm is grown, and contact holes are formed for connections between functional elements. After depositing the aluminum film 3 to a thickness of 1.0 μm, it is shaped into an aluminum wiring using a known photoetching technique.
その後コンタクトホール内でのN型拡散層4とアルミニ
ウム配線(3)との接触抵抗を下げる為350〜450
℃での熱処理を行なう。After that, in order to lower the contact resistance between the N-type diffusion layer 4 and the aluminum wiring (3) in the contact hole,
Perform heat treatment at ℃.
通常この熱処理はトランジスタの安定化を兼ねるので水
素を含む雰囲気中(水素ガスと窒化ガスをぼぼ1:1で
混合したもの)で行なわれる。この段階で、第3図(b
)に示すように、アルミニウム膜3に突起10a、10
bが生じることがある。Usually, this heat treatment also serves to stabilize the transistor, so it is carried out in an atmosphere containing hydrogen (hydrogen gas and nitriding gas mixed at a ratio of approximately 1:1). At this stage, as shown in Figure 3 (b)
), the aluminum film 3 has protrusions 10a, 10
b may occur.
その後、第3図(c)に示すように、半導体チップの表
面を保護する為CVD技術を用いて二酸化シリコン膜9
を厚さ2,0μm被着する。Thereafter, as shown in FIG. 3(c), a silicon dioxide film 9 is formed using CVD technology to protect the surface of the semiconductor chip.
A thickness of 2.0 μm is applied.
そして、第3図(d)に示すように、ホトレジスト膜1
1を用いたホトエツチングの技術を用いて半導体チップ
と外部端子と接続する為二酸化シリコン膜に開孔7を設
ける。Then, as shown in FIG. 3(d), the photoresist film 1
Openings 7 are formed in the silicon dioxide film for connection to the semiconductor chip and external terminals using a photoetching technique using No. 1.
上述した従来の半導体装置の金属配線形成方法は、金属
膜を所定パターンに整形した後コンタクトホール部での
金属膜とN型拡散層との抵触抵抗を下げる目的とトラン
ジスタの安定化の目的で通常水素を含む雰囲気で350
℃〜450℃の熱処理が行なわれる。しかし、特にアル
ミニウムを主成分とする金属膜に350℃〜450℃の
熱処理を行なうと突起(ヒロック)が発生するという欠
点がある。この金属配線の突起は特に線幅の太い配線に
発生しやすく表面(10a)と側面(10b)両方に発
生する0表面の突起10aのところでは、第3図(d)
に示すように、二酸化シリコン膜の表面がホトレジスト
膜に覆われずに露出し、次のエツチング工程で絶縁膜(
9)がエツチングされ、突起が露出することがある。ま
た金属配線の側面に発生する突起10bは隣りの金属配
線と短絡し製造歩留を下げ微細加工の妨げとなる。The conventional method for forming metal wiring in a semiconductor device described above is usually performed after shaping a metal film into a predetermined pattern for the purpose of lowering the contact resistance between the metal film and the N-type diffusion layer at the contact hole portion and for the purpose of stabilizing the transistor. 350 in an atmosphere containing hydrogen
A heat treatment is performed at a temperature of 450°C to 450°C. However, there is a drawback in that when a metal film containing aluminum as a main component is subjected to heat treatment at 350 DEG C. to 450 DEG C., protrusions (hillocks) are generated. This metal wiring protrusion is particularly likely to occur in wiring with a thick line width, and occurs on both the front surface (10a) and the side surface (10b).
As shown in Figure 2, the surface of the silicon dioxide film is exposed without being covered with the photoresist film, and the insulating film (
9) may be etched and the protrusions may be exposed. In addition, the protrusions 10b generated on the side surfaces of the metal wiring cause a short circuit with the adjacent metal wiring, lowering the manufacturing yield and hindering microfabrication.
本発明の半導体装置の金属配線形成方法は、基板上に金
属膜を被着した後所定のパターンの金属配線に整形する
工程と、前記金属配線を覆って絶縁膜を形成する工程と
、水素を含む雰囲気中で熱処理を行なう工程とを含むと
いうものである。The method for forming metal wiring in a semiconductor device according to the present invention includes a step of depositing a metal film on a substrate and then shaping the metal wiring into a predetermined pattern, a step of forming an insulating film covering the metal wiring, and a step of forming an insulating film to cover the metal wiring. The process includes a step of performing heat treatment in an atmosphere containing
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)〜(d)は本発明の一実施例を説明するた
めの工程順に配置した半導体チップの縦断面図である。FIGS. 1(a) to 1(d) are longitudinal cross-sectional views of semiconductor chips arranged in the order of steps for explaining one embodiment of the present invention.
まず、第1図(a)に示すように、P型シリコン基板1
上にトランジスタ等の機能素子(N型拡散層4を代表と
して示す)を形成後公知のCVD技術を用い厚さ0.8
μmの二酸化シリコン膜2を成長させ、機能素子間の接
続等の為コンタクトホールを開孔する。アルミニウム膜
3を厚さ1.0μmで形成し公知のホトエツチングで所
定のパターンに整形する。この状態のものを基板として
、第1図(b)に示すように、プラズマCVD法により
整形されたアルミニウム膜3を覆って、二酸化シリコン
膜5を厚さ0.2μm形成し、水素を含む雰囲気(水素
ガスと窒素ガスを1:1で混合したもの)で350〜4
50℃の熱処理を行ないN型拡散層4とアルミニウム膜
との接触抵抗を下げ、トランジスタの安定化処理を行な
う。First, as shown in FIG. 1(a), a P-type silicon substrate 1
After forming a functional element such as a transistor (the N-type diffusion layer 4 is shown as a representative) on top, it is deposited to a thickness of 0.8 mm using a known CVD technique.
A silicon dioxide film 2 having a thickness of μm is grown, and contact holes are formed for connections between functional elements. An aluminum film 3 is formed to a thickness of 1.0 μm and shaped into a predetermined pattern by known photoetching. Using this state as a substrate, as shown in FIG. 1(b), a silicon dioxide film 5 with a thickness of 0.2 μm was formed covering the aluminum film 3 shaped by the plasma CVD method, and an atmosphere containing hydrogen was formed. (1:1 mixture of hydrogen gas and nitrogen gas) 350~4
A heat treatment is performed at 50° C. to lower the contact resistance between the N-type diffusion layer 4 and the aluminum film, and to stabilize the transistor.
その後、第1図(c)に示すように、CVD法により窒
化シリコン膜を厚さ2.0μm形成する。そして、第1
図(d)に示すように、公知のホトエツチングを用いて
外部端子と接続する為の開孔7を設ける。Thereafter, as shown in FIG. 1(c), a silicon nitride film is formed to a thickness of 2.0 μm by CVD. And the first
As shown in Figure (d), an opening 7 for connection to an external terminal is provided using known photoetching.
二酸化シリコン膜の厚さは、実際上0.1μmあれば熱
処理時に突起の発生を抑える事ができる。In practice, if the thickness of the silicon dioxide film is 0.1 μm, the generation of protrusions during heat treatment can be suppressed.
また実施例では熱処理前に二酸化シリコン膜を、熱処置
後に窒化シリコン膜をそれぞれ形成したが二酸化シリコ
ン膜あるいは窒化シリコン膜のいずれか一方を二度にわ
けて被着してもよい。いずれにせよ、はじめにアルミニ
ウム膜を覆う絶縁膜の種類と厚さは、熱処理時にヒロッ
クの発生を抑えるのに十分な機械的強度を有しかつ水素
を透過して機能素子の安定化をはかることができるよう
に実験的に定めればよい。二度目に被着する絶縁膜は、
眉間絶縁膜やカバー絶縁膜として一度目の絶縁膜では不
足する分を補うため被着するのであるから、場合によっ
ては省略してもよい。Further, in the embodiment, a silicon dioxide film was formed before the heat treatment, and a silicon nitride film was formed after the heat treatment, but either the silicon dioxide film or the silicon nitride film may be deposited in two parts. In any case, first, the type and thickness of the insulating film covering the aluminum film must be such that it has sufficient mechanical strength to suppress the occurrence of hillocks during heat treatment, and is capable of permeating hydrogen to stabilize the functional element. It should be determined experimentally so that it can be done. The second insulating film is
Since the glabella insulating film and the cover insulating film are deposited to compensate for the insufficiency in the first insulating film, they may be omitted depending on the case.
第2図(a)、(b)は一実施例の変形を説明するため
の半導体チップの縦断面図である。FIGS. 2(a) and 2(b) are longitudinal sectional views of a semiconductor chip for explaining a modification of one embodiment.
第1図を用いて説明したようにコンタクトホールを形成
した後、スパッタ法にて窒化チタン膜8を0.1μmの
厚さ、アルミニウム膜3を1.0μmの厚さで形成した
後公知のホトエツチングで所定のパターンを形成するく
第2図(a))。その後二酸化シリコン膜9を厚さ1.
0μmの厚さで形成し水素を含む雰囲気中で350〜4
50℃の熱処理を行なう(第2図(b))。そして一実
施例で説明したように、アルミニウム配線上の二酸化シ
リコン膜に開孔を設けて半導体集積回路を得る。After forming the contact hole as explained using FIG. 1, a titanium nitride film 8 with a thickness of 0.1 μm and an aluminum film 3 with a thickness of 1.0 μm are formed by sputtering, followed by known photoetching. 2(a)) to form a predetermined pattern. Thereafter, a silicon dioxide film 9 is formed to a thickness of 1.
Formed with a thickness of 0 μm and heated in an atmosphere containing hydrogen at 350~4
Heat treatment is performed at 50° C. (FIG. 2(b)). Then, as described in one embodiment, openings are provided in the silicon dioxide film on the aluminum wiring to obtain a semiconductor integrated circuit.
このように、金属膜はアルミニウムの単層膜に限らず、
アルミニウムを主成分として含む金属薄膜あるいは多層
膜であってもよい。又、二酸化シリコン膜は窒化シリコ
ン膜に比較すると水素を透過し易いので、1〜2μmの
厚さまで被着してもトランジスタなどの機能素子の安定
化を行うことができる。In this way, metal films are not limited to single-layer aluminum films;
It may be a metal thin film or a multilayer film containing aluminum as a main component. Further, since silicon dioxide film is more permeable to hydrogen than silicon nitride film, functional elements such as transistors can be stabilized even when deposited to a thickness of 1 to 2 μm.
また実施例ではアルミニウム配線とN型拡散層との接触
構造のものについて述べたがP型拡散層、多結晶シリコ
ン配線層等の他の配線層とアルミニウム配線の接触構造
のものについても本発明を適用することができる。Further, in the embodiment, a contact structure between an aluminum wiring and an N-type diffusion layer has been described, but the present invention can also be applied to a contact structure between an aluminum wiring and other wiring layers such as a P-type diffusion layer or a polycrystalline silicon wiring layer. Can be applied.
以上説明したように本発明は、金属配線をバターニング
した後の熱処理を絶縁膜を形成した後に行なう事により
、金属配線に突起が発生する事を抑える事ができ、信頼
性が高く製造歩留の良い半導体集積回路を得る事ができ
る効果がある。As explained above, in the present invention, by performing heat treatment after patterning the metal wiring after forming an insulating film, it is possible to suppress the occurrence of protrusions on the metal wiring, thereby increasing reliability and manufacturing yield. This has the effect of making it possible to obtain a semiconductor integrated circuit with good quality.
第1図(a)〜(d)、第2図(a)、(b)及び第3
図(a)〜(e)はそれぞれ本発明の一実施例、一実施
例の変形及び従来例を説明するための工程順に配置した
半導体チップの断面図である。
1・・・P型Si基板、2・・・二酸化シリコン膜、3
・・・アルミニウム膜、4・・・N型拡散層、5・・・
二酸化シリコン膜、6・・・窒化シリコン膜、7・・・
開孔、8・・・窒化チタン膜、9・・・二酸化シリコン
膜、10a、10b・・・突起、11・・・ホトレジス
ト膜。Figure 1 (a) to (d), Figure 2 (a), (b) and Figure 3
Figures (a) to (e) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining an embodiment of the present invention, a modification of the embodiment, and a conventional example, respectively. 1... P-type Si substrate, 2... Silicon dioxide film, 3
... Aluminum film, 4... N-type diffusion layer, 5...
Silicon dioxide film, 6... Silicon nitride film, 7...
Opening, 8...Titanium nitride film, 9...Silicon dioxide film, 10a, 10b...Protrusion, 11...Photoresist film.
Claims (2)
属配線に整形する工程と、前記金属配線を覆って絶縁膜
を形成する工程と、水素を含む雰囲気中で熱処理を行な
う工程とを含むことを特徴とする半導体装置の金属配線
形成方法。(1) A step of depositing a metal film on a substrate and then shaping it into metal wiring in a predetermined pattern, a step of forming an insulating film covering the metal wiring, and a step of performing heat treatment in an atmosphere containing hydrogen. A method for forming metal wiring in a semiconductor device, the method comprising:
少なくとも一層有している請求項(1)記載の半導体装
置の金属配線形成方法。(2) The method for forming metal wiring in a semiconductor device according to claim (1), wherein the metal film has at least one metal thin film containing aluminum as a main component.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26042589A JPH03120826A (en) | 1989-10-04 | 1989-10-04 | Formation of metal wiring of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26042589A JPH03120826A (en) | 1989-10-04 | 1989-10-04 | Formation of metal wiring of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03120826A true JPH03120826A (en) | 1991-05-23 |
Family
ID=17347758
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26042589A Pending JPH03120826A (en) | 1989-10-04 | 1989-10-04 | Formation of metal wiring of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03120826A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05243226A (en) * | 1992-03-03 | 1993-09-21 | Nec Corp | Manufacture of semiconductor device |
-
1989
- 1989-10-04 JP JP26042589A patent/JPH03120826A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05243226A (en) * | 1992-03-03 | 1993-09-21 | Nec Corp | Manufacture of semiconductor device |
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