JPH0290616A - Through-hole forming method for interlayer insulating film - Google Patents
Through-hole forming method for interlayer insulating filmInfo
- Publication number
- JPH0290616A JPH0290616A JP24500888A JP24500888A JPH0290616A JP H0290616 A JPH0290616 A JP H0290616A JP 24500888 A JP24500888 A JP 24500888A JP 24500888 A JP24500888 A JP 24500888A JP H0290616 A JPH0290616 A JP H0290616A
- Authority
- JP
- Japan
- Prior art keywords
- film
- window
- polyimide
- silicon
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011229 interlayer Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 17
- 229920001721 polyimide Polymers 0.000 claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 15
- 238000010030 laminating Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 44
- 239000010410 layer Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002075 main ingredient Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の層間絶縁膜にスルーホー
ルを形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming through holes in an interlayer insulating film of a semiconductor integrated circuit device.
従来、半導体集積回路装置の多層配線を形成する場合、
配線層間には層間絶縁膜を形成して互いに絶縁を図り、
接続する部分のみ層間絶縁膜に窓、いわゆるスルーホー
ルを開けて、そのスルーホールを金属層で埋めて層間の
配線を接続していた。Conventionally, when forming multilayer wiring for semiconductor integrated circuit devices,
An interlayer insulating film is formed between the wiring layers to insulate them from each other.
Windows, or so-called through holes, were opened in the interlayer insulating film only in the areas to be connected, and the through holes were filled with a metal layer to connect the wiring between the layers.
また、この層間絶縁膜として、通常、二酸化シリコン膜
が最も多く部用されている。しかしながら、この二酸化
シリコン膜を形成する際に、半導体基板をかなり高温に
熱する必要があり、この高い温度のためにアルミニウム
金属蒸着層にヒロックなどの微小突起を生じ、層間絶縁
膜に多数のピンホールを発生させる問題がある。また、
この層間絶縁膜を厚く形成するために、化学的気相成長
法等で膜を成長すると、アルミニウムとの膨張係数の違
いにより層間絶縁膜に亀裂を生じなりする等問題がある
。従って、この二酸化シリコン膜の代りに、例えば、特
公昭51−44871号にはボリイミド樹脂層を層間絶
縁膜として使用することが提案されている。このポリイ
ミド樹脂層にスルーホールを開ける場合には、酸素プラ
ズマを用いた等方性プラズマエツチング法でスルーホー
ルを開けている。Further, as this interlayer insulating film, a silicon dioxide film is usually used most often. However, when forming this silicon dioxide film, it is necessary to heat the semiconductor substrate to a fairly high temperature, and this high temperature causes minute protrusions such as hillocks on the aluminum metal vapor deposited layer, and many pins on the interlayer insulating film. There is a problem that causes holes. Also,
If a chemical vapor deposition method or the like is used to grow the interlayer insulating film to make it thick, there are problems such as cracks in the interlayer insulating film due to the difference in expansion coefficient between aluminum and aluminum. Therefore, instead of this silicon dioxide film, for example, Japanese Patent Publication No. 51-44871 proposes to use a polyimide resin layer as an interlayer insulating film. When making through holes in this polyimide resin layer, the through holes are made by an isotropic plasma etching method using oxygen plasma.
上述した従来のスルーホール形成方法では、下地の表面
の段差形状や寸法の違いにより局所的に膜厚に差がある
ため、膜厚の薄い所にスルーホールを形成する場合には
、エツチング時間の影響で他のスルーホールより大きな
スルーホールが開けられるという問題点がある。また、
別法として、異方性エツチング法、例えば、リアクティ
ブエツチング法によりスルーホールを形成する場合には
、開けられたスルーホールの断面形状が急峻になり、コ
ンタクトとなる金属層の接着力が弱く剥れを引起し導通
不良となる問題がる。In the conventional through-hole forming method described above, there are local differences in film thickness due to differences in the step shape and dimensions on the surface of the base, so when forming through-holes in areas with thin film thickness, the etching time is There is a problem in that a through hole that is larger than other through holes can be opened due to the influence. Also,
Alternatively, when a through hole is formed by an anisotropic etching method, such as a reactive etching method, the cross-sectional shape of the drilled through hole becomes steep, and the adhesive strength of the metal layer that becomes the contact is weak, resulting in peeling. There is a problem that this may cause a problem of poor conductivity.
本発明の目的は、層間絶縁膜と接着力のより高いコンタ
クトが得られるとともに安定した寸法のスルーホールが
得られる層間絶縁膜スルーホール形成方法を提供するこ
とにある。An object of the present invention is to provide a method for forming a through-hole in an interlayer insulating film, which allows a contact with an interlayer insulating film with higher adhesive strength and a through-hole with stable dimensions to be obtained.
本発明の層間絶縁膜スルーホール形成方法は、−主面上
の配線を含めた半導体基板表面にシリコンを含んだ第1
のポリイミド膜と前記第1のポリイミド膜上に重ねてシ
リコンを含まない第2のポリイミド膜を形成してなる層
間絶縁膜形成工程と、前記第1のポリイミド膜に第1の
窓を形成するとともに前記第2のポリイミド膜に前記第
1の窓より所定の大きさだけ大きく且つ前記第1の窓と
同一中心軸をもつ第2の窓を形成する工程とを含んで構
成される。The method for forming an interlayer insulating film through hole of the present invention includes: - a first layer containing silicon on the surface of a semiconductor substrate including wiring on the main surface;
forming a second polyimide film not containing silicon overlying the polyimide film and the first polyimide film; forming a first window in the first polyimide film; forming a second window in the second polyimide film that is larger than the first window by a predetermined size and has the same central axis as the first window.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の第1の実施例を説明するための半導体
チップの工程順に示した半導体チップの断面図である。FIG. 1 is a cross-sectional view of a semiconductor chip shown in the order of manufacturing steps for explaining a first embodiment of the present invention.
この実施例は、2ミクロン程度の設計ルールにおけるL
SIに適用した場合である。In this example, L in a design rule of about 2 microns is
This is the case when applied to SI.
まず、第1図(a)に示すように、半導体基板1上に、
公知の方法により、例えば、4μm程度の幅をもつアル
ミニウムの第1の配線2を形成する。First, as shown in FIG. 1(a), on a semiconductor substrate 1,
A first wiring 2 made of aluminum and having a width of, for example, about 4 μm is formed by a known method.
次に、アルミニウムの第1の配線2を含む半導体基板1
の表面にシリコンを含んだポリイミド溶液をスピンコー
タにより半導体基板に滴下してポリイミドの塗布膜を形
成し、窒素雰囲気中約200℃以下の温度で乾燥して厚
さ0.8μmの第1のポリイミド膜3を形成する0次に
、第1図(b)に示すよううに、シリコンを含まないポ
リイミド液をスピンコータにより半導体基板に滴下し、
厚さ0.8μmのポリイミド塗布膜を形成し、窒素雰囲
気中で段階的に温度上昇させ、約400℃以下で熱処理
して約1.0μm程度の第2のポリイミド膜4に成膜す
る。次に、第1図(C)に示すように、第2のポリイミ
ド膜4の上に、第2のポリイミド膜4より厚い約2μm
の厚さのホトレジスト膜5を形成し、ホトリソグラフィ
法により窓6を開ける0次に、第1図(d)に示すよう
に、四ふつ化炭素(CF4)ガスと酸素との混合ガスで
圧力5Paにて異方性エツチング法である逆反応性エツ
チングを行い、窓6の底部のポリイミド膜3及び4を除
去して窓6を窓6aに深く形成する。次に、第1図(e
)に示すように、ホトリソグラフィ法により窓6aのホ
トレジスト膜5を窓6aより大きく除去して、窓6bを
形成する。このホトレジスト膜5をマスクにして、四ふ
っ化炭素(CF4 )ガスと酸素との混合ガスで圧力5
Paにて異方性エツチング法である逆反応性エツチング
を行い、第1及び第2のポリイミド膜3及び4を除去す
る。このとき、第2のポリイミド膜4のみエツチング除
去され、第1のポリイミド膜3はエツチングが進行せず
、もとの形状を保つことになる6次に、第1図<r>に
示すように、通常の溶媒にてホトレジスト膜5を除去し
、金属蒸着法によりアルミニウムの第2の配線7を形成
して第1の配線2と接続する。このように、スルーホー
ルである窓を階段状にエツチングして作れば、第1のポ
リイミド膜に膜厚の段差があっても横方向のエツチング
が進まないので、ばらつきの少ない窓の寸法が得られる
だけではなく、配線である蒸着金属層と層間絶縁膜であ
るポリイミド膜との密着面積をより増大させたことにな
る
第2図は本発明の第2の実施例を説明するための半導体
チップの工程順に示した半導体チップの断面図である。Next, the semiconductor substrate 1 including the first wiring 2 made of aluminum is
A polyimide solution containing silicon is dropped onto the semiconductor substrate using a spin coater to form a polyimide coating film on the surface of the semiconductor substrate, and dried at a temperature of about 200°C or less in a nitrogen atmosphere to form a first polyimide film with a thickness of 0.8 μm. Next, as shown in FIG. 1(b), a polyimide solution containing no silicon is dropped onto the semiconductor substrate using a spin coater.
A polyimide coating film with a thickness of 0.8 μm is formed, the temperature is raised stepwise in a nitrogen atmosphere, and a heat treatment is performed at about 400° C. or lower to form a second polyimide film 4 with a thickness of about 1.0 μm. Next, as shown in FIG. 1(C), a layer of about 2 μm thicker than the second polyimide film 4 is coated on the second polyimide film 4.
A photoresist film 5 with a thickness of Reverse reactive etching, which is an anisotropic etching method, is performed at 5 Pa to remove the polyimide films 3 and 4 at the bottom of the window 6, thereby forming the window 6 deeply in the window 6a. Next, in Figure 1 (e
), a larger portion of the photoresist film 5 on the window 6a than the window 6a is removed by photolithography to form a window 6b. Using this photoresist film 5 as a mask, a mixed gas of carbon tetrafluoride (CF4) gas and oxygen was applied to the
Reverse reactive etching, which is an anisotropic etching method, is performed at Pa to remove the first and second polyimide films 3 and 4. At this time, only the second polyimide film 4 is etched away, and the first polyimide film 3 is not etched and retains its original shape.Next, as shown in FIG. Then, the photoresist film 5 is removed using an ordinary solvent, and a second wiring 7 made of aluminum is formed by metal vapor deposition and connected to the first wiring 2. In this way, if the windows, which are through-holes, are etched in a stepped manner, even if there are steps in the thickness of the first polyimide film, the lateral etching will not proceed, resulting in window dimensions with little variation. In addition to increasing the adhesion area between the vapor-deposited metal layer, which is the wiring, and the polyimide film, which is the interlayer insulating film, Figure 2 shows a semiconductor chip for explaining a second embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor chip shown in the order of steps.
この実施例は第1の実施例のホトレジスト膜の代りにシ
リコン酸化膜を用いた例である。この実施例の工程は、
第1の実施例の第1図(b)までは同じである。まず、
第2図(a)で示すように、圧力100Pa程度のシラ
ン(SiH4)と酸化窒素(N20)との混合ガス雰囲
気中で、半導体基板温度を約300℃に加熱し、プラズ
マ酸化して第2のポリイミド膜4の上に厚さ0.2μm
のシリコン酸化膜8を形成する0次に、第2図(b)に
示すように、ホトレジスト膜をシリコン酸化膜8の上に
形成し、ホトリソグラフィ法によりホトレジスト膜を選
択的に除去してホトマスクであるホトレジスト膜5を形
成する。This embodiment is an example in which a silicon oxide film is used in place of the photoresist film of the first embodiment. The steps in this example are:
The steps up to FIG. 1(b) of the first embodiment are the same. first,
As shown in FIG. 2(a), the semiconductor substrate temperature is heated to about 300°C in a mixed gas atmosphere of silane (SiH4) and nitrogen oxide (N20) at a pressure of about 100 Pa, plasma oxidation is performed, and a second on the polyimide film 4 with a thickness of 0.2 μm.
Next, as shown in FIG. 2(b), a photoresist film is formed on the silicon oxide film 8, and the photoresist film is selectively removed by photolithography to form a photomask. A photoresist film 5 is formed.
次に、四ふっ化炭素(CF4 )ガスを主体にした逆反
応性エツチングを行い、ホトレジスト膜5及びシリコン
酸化膜8にスルーホールである窓6Cを開ける0次に、
第2図(c)に示すように、第1の実施例の第1図(d
)及び(e)で説明した工程と同じ方法で行い、第1及
び第2のポリイミド膜3及び4を選択的に除去してスル
ーホールである窓6cをエツチングして窓6dに形成す
る。Next, reverse reactive etching using carbon tetrafluoride (CF4) gas as the main ingredient is performed to open windows 6C, which are through holes, in the photoresist film 5 and silicon oxide film 8.
As shown in FIG. 2(c), FIG.
) and (e), the first and second polyimide films 3 and 4 are selectively removed, and the window 6c, which is a through hole, is etched to form the window 6d.
このとき、第2のポリイミド膜の横方向のエツチングが
他の層より進むので、第2のポリイミド膜のみ大きい穴
が形成される0次に、第2図(d)に示すように、ぶつ
化水素(HF)でシリコン酸化膜8を除去し、金属蒸着
法により、アルミニウムを蒸着し、アルミニウム金属蒸
着層を選択的にエツチング除去して、第2の配線7を形
成して下層のアルミニウム第1の配線2と接続する。At this time, since the lateral etching of the second polyimide film is more advanced than the other layers, large holes are formed only in the second polyimide film. The silicon oxide film 8 is removed with hydrogen (HF), aluminum is deposited by a metal vapor deposition method, and the aluminum metal vapor deposited layer is selectively etched away to form the second wiring 7 and the underlying aluminum first layer is removed. Connect to wiring 2.
なお、この実施例で使用したホトレジスト膜は第1の実
施例に用いたレジスト膜と比較してより薄いホトレジス
ト膜て済む。その理由は、通常、四ふっ化炭素(CF4
>ガスを主体にした逆反応性エツチングでは、レジス
ト膜は膜減りしないからである。このことは、逆に言え
ば、ホトリソグラフィによりレジスト膜に比較的に微細
な開口を形成出来ることが言えるので、この実施例は第
1の実施例よりは利点がある。Note that the photoresist film used in this example is thinner than the resist film used in the first example. The reason is usually carbon tetrafluoride (CF4
>This is because the resist film does not decrease in reverse reactive etching that uses gas as its main ingredient. Conversely, it can be said that relatively fine openings can be formed in the resist film by photolithography, so this embodiment has an advantage over the first embodiment.
以上説明した実施例以外に、エツチングマスクとして、
ホトレジスト膜やシリコン酸化膜以外に、例えば、アル
ミニウムやチタニウムのような金属膜を使用しても良く
、この場合のエツチング方法は塩素ガスを用いた逆反応
性エツチングを行うことによりスルーホールを形成出来
る。また、これらの金属膜を除去するには、アルミニウ
ムの場合は、温化されたりん酸液に浸けることにより除
去される。チタニウムの場合は、アンモニア水と過酸化
水素水の混合液に浸けることにより除去出来る。In addition to the embodiments described above, as an etching mask,
In addition to photoresist films and silicon oxide films, metal films such as aluminum and titanium may also be used, and in this case, through-holes can be formed by performing reverse reactive etching using chlorine gas. . Further, in order to remove these metal films, in the case of aluminum, it is removed by immersing it in a heated phosphoric acid solution. In the case of titanium, it can be removed by soaking it in a mixture of aqueous ammonia and hydrogen peroxide.
以上説明したように本発明は、シリコンの含むポリイミ
ド膜の上にシリコンの含まないポリイミド膜を重ねて形
成し層間絶縁膜とし、シリコンを含むポリイミド膜に小
さい穴を、シリコンの含まないポリイミド膜に大きい穴
を開けてなるスルーホールを設けたので、シリコンを含
むポリイミド膜は横方向のエツチングが進まないので、
このポリイミド膜の膜厚に段差があっても、ばらつきの
少ない穴が得られる。また、二つのポリイミド膜の穴の
大きさでなる段差を設けることにより金属と層間絶縁膜
との接着面積を増加することが出来る。従って、層間絶
縁膜とコンタクトとの密着力をより高められるともに安
定した寸法のスルーホールが得られるという効果がある
。As explained above, in the present invention, a polyimide film that does not contain silicon is layered on top of a polyimide film that contains silicon to form an interlayer insulating film, and small holes are formed in the polyimide film that contains silicon to form a polyimide film that does not contain silicon. Since we created a large through hole, the polyimide film containing silicon will not be etched in the lateral direction.
Even if there is a step difference in the thickness of this polyimide film, holes with little variation can be obtained. Further, by providing a step formed by the size of the holes in the two polyimide films, the adhesion area between the metal and the interlayer insulating film can be increased. Therefore, there is an effect that the adhesion between the interlayer insulating film and the contact can be further enhanced, and a through hole with stable dimensions can be obtained.
第1図は本発明の第1の実施例を説明するための半導体
チップの工程順に示した半導体チップの断面図、第2図
は本発明の第2の実施例を説明するための半導体チップ
の工程順に示した半導体チップの断面図である。
1・・・半導体基板、2・・・第1の配線、3・・・第
1のポリイミド膜、4・・・第2のポリイミド膜、5・
・・ホトレジスト膜、6.6a、6b、6C56d ・
・・窓、7・・・第2の配線、8・・・酸化膜。FIG. 1 is a sectional view of a semiconductor chip shown in the order of manufacturing steps for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor chip shown in the order of steps. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First wiring, 3... First polyimide film, 4... Second polyimide film, 5...
・Photoresist film, 6.6a, 6b, 6C56d ・
...Window, 7...Second wiring, 8...Oxide film.
Claims (1)
んだ第1のポリイミド膜と前記第1のポリイミド膜上に
重ねてシリコンを含まない第2のポリイミド膜を形成し
てなる層間絶縁膜形成工程と、前記第1のポリイミド膜
に第1の窓を形成するとともに前記第2のポリイミド膜
に前記第1の窓より所定の大きさだけ大きく且つ前記第
1の窓と同一中心軸をもつ第2の窓を形成する工程とを
含んだことを特徴とする層間絶縁膜スルーホール形成方
法。An interlayer insulating film formed by forming a first polyimide film containing silicon on the surface of the semiconductor substrate including wiring on one main surface, and a second polyimide film not containing silicon overlaid on the first polyimide film. forming a first window in the first polyimide film and having a predetermined size larger than the first window in the second polyimide film and having the same central axis as the first window; A method for forming a through hole in an interlayer insulating film, the method comprising the step of forming a second window.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24500888A JPH0750707B2 (en) | 1988-09-28 | 1988-09-28 | Method for forming interlayer insulating film through hole |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24500888A JPH0750707B2 (en) | 1988-09-28 | 1988-09-28 | Method for forming interlayer insulating film through hole |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0290616A true JPH0290616A (en) | 1990-03-30 |
JPH0750707B2 JPH0750707B2 (en) | 1995-05-31 |
Family
ID=17127203
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24500888A Expired - Lifetime JPH0750707B2 (en) | 1988-09-28 | 1988-09-28 | Method for forming interlayer insulating film through hole |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0750707B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007524249A (en) * | 2004-02-26 | 2007-08-23 | シーメンス アクチエンゲゼルシヤフト | System having electrical components and electrical connection conductors of the components and method of manufacturing the system |
JP2010067650A (en) * | 2008-09-09 | 2010-03-25 | Sharp Corp | Semiconductor device, manufacturing method for the semiconductor device, and power module |
-
1988
- 1988-09-28 JP JP24500888A patent/JPH0750707B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007524249A (en) * | 2004-02-26 | 2007-08-23 | シーメンス アクチエンゲゼルシヤフト | System having electrical components and electrical connection conductors of the components and method of manufacturing the system |
JP2010067650A (en) * | 2008-09-09 | 2010-03-25 | Sharp Corp | Semiconductor device, manufacturing method for the semiconductor device, and power module |
Also Published As
Publication number | Publication date |
---|---|
JPH0750707B2 (en) | 1995-05-31 |
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