JPH0428231A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0428231A JPH0428231A JP13320390A JP13320390A JPH0428231A JP H0428231 A JPH0428231 A JP H0428231A JP 13320390 A JP13320390 A JP 13320390A JP 13320390 A JP13320390 A JP 13320390A JP H0428231 A JPH0428231 A JP H0428231A
- Authority
- JP
- Japan
- Prior art keywords
- film
- protective film
- electrode
- wiring
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 230000001681 protective effect Effects 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229920001721 polyimide Polymers 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 13
- 229920005989 resin Polymers 0.000 claims abstract description 13
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 7
- 238000001020 plasma etching Methods 0.000 claims abstract description 7
- 239000004642 Polyimide Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 8
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 4
- 229910001882 dioxygen Inorganic materials 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 22
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 239000007789 gas Substances 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は半導体装置の製造方法に関し、特に半導体装置
の上層に耐湿性に優れた保護膜を形成する方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a protective film with excellent moisture resistance on the upper layer of a semiconductor device.
一般に、半導体装置の組立工程において、半導体装置に
対する機械的損傷や、水分の浸入や汚染による半導体装
置の劣化を防ぐ目的で、半導体装置の最上層に耐湿性に
優れた保護膜を設けることが行われている。従来におけ
る、この種の保護膜の製造方法を第２図を用いて説明す
る。Generally, during the assembly process of semiconductor devices, a protective film with excellent moisture resistance is provided on the top layer of the semiconductor device in order to prevent mechanical damage to the semiconductor device and deterioration of the semiconductor device due to moisture intrusion and contamination. It is being said. A conventional method for manufacturing this type of protective film will be explained with reference to FIG.
先ず、第２図（ａ）のように、表面に絶縁膜を有する半
導体基板１に、アルミニウム配線２およびアルミニウム
ボンディング電極３を形成する。First, as shown in FIG. 2(a), aluminum interconnections 2 and aluminum bonding electrodes 3 are formed on a semiconductor substrate 1 having an insulating film on its surface.
その後、同図（ｂ）のように、プラズマＣＶＤ法により
原料ガスとしてＳ ｉ Ｈ４、ＮＨ３を導入し、圧力を
約ｌ ｔｏｒｒ、温度を約３００”Ｃとした条件にて約
１μｍの膜厚のシリコンナイトライド膜を形成し、これ
を保護膜５とする。なお、原料ガスとしてＳｉＨ４，Ｎ
Ｈ，、Ｎ２０を用いて同様の条件でシリコンオキシナイ
トライド膜を付け、これを保護膜としてもよい。Thereafter, as shown in the same figure (b), SiH4 and NH3 were introduced as raw material gases by plasma CVD, and a film with a thickness of about 1 μm was formed at a pressure of about 1 torr and a temperature of about 300"C. A silicon nitride film is formed and used as the protective film 5.SiH4,N
A silicon oxynitride film may be applied as a protective film using H, N20 under similar conditions.
ついで、同図（Ｃ）のように、前記アルミニウムボンデ
ィング電極３を外部電極と接続するために、フォトレジ
スト６をマスクとしてアルミニウムボンディング電極３
上の保護膜５を選択除去する。この際の、エツチングガ
スとしては、酸素を含んだフッ化ガスを用いたプラズマ
エツチング法が利用される。Next, as shown in FIG. 3C, in order to connect the aluminum bonding electrode 3 to an external electrode, the aluminum bonding electrode 3 is formed using the photoresist 6 as a mask.
The upper protective film 5 is selectively removed. At this time, a plasma etching method using a fluoride gas containing oxygen is used as the etching gas.
ついで、同図（ｄ）のように、フォ１へレジスト６を酸
素ガスを用いたプラズマ除去により除去することで、保
護膜５が完成される。Then, as shown in FIG. 1D, the resist 6 on the photo resist 1 is removed by plasma removal using oxygen gas, thereby completing the protective film 5.
〔発明が解決しようとする課題］
ところで、上述したような半導体装置においては、半導
体基板の表面に生じる段差はアルミニウム配線２やアル
ミニラ１、ボンディング電極３による段差が最も大きな
ものとなっている。また、回路の高集積化に伴って配線
間隔が小さくなる傾向にあり、前記した段差が更に顕著
なものとされている。この点、アルミニウム配線等の膜
厚を薄くして段差を緩和することが考えられるが、この
対策では回路の要求特性を満たずことが困難になり、し
かも回路の製造方法も変えてしまう度合いが大きいため
採用することはできない。[Problems to be Solved by the Invention] Incidentally, in the semiconductor device as described above, the largest step difference occurring on the surface of the semiconductor substrate is the step caused by the aluminum wiring 2, the aluminum lamination 1, and the bonding electrode 3. Further, as circuits become more highly integrated, the spacing between wiring lines tends to become smaller, and the above-mentioned step difference becomes even more noticeable. In this regard, it is possible to reduce the thickness of the aluminum wiring to reduce the level difference, but this measure makes it difficult to meet the required characteristics of the circuit, and it also requires changing the manufacturing method of the circuit. It cannot be used because it is too large.
したがって、このような段差の上層に前記したような保
護膜５を形成すると、この種の保護膜５に用いられるプ
ラズマＣＶＤ膜は、滑らかな基板表面に付けられた場合
は、非常に優れた性能を示すが、急峻で深い段差の側面
に（＝ｊけられた場合には膜厚が薄く、膜質も悪いとい
う性質があるため、回路の微細化に伴って段差形状が厳
しくなると、保護膜の性能、特に耐湿性が劣化するとい
う問題が生じる。Therefore, when the above-mentioned protective film 5 is formed on the upper layer of such a step, the plasma CVD film used for this type of protective film 5 has very excellent performance when applied to a smooth substrate surface. However, if the side surface of a steep and deep step is cut (=j), the film thickness will be thin and the film quality will be poor. A problem arises in that performance, especially moisture resistance, deteriorates.
本発明の目的は、半導体基板の表面段差を緩和して保護
膜の性能を向上させた半導体装置の製造方法を提供する
ことにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that improves the performance of a protective film by reducing the surface level difference of a semiconductor substrate.
本発明の製造方法は、半導体基板上に所要パターンの配
線や電極を形成する工程と、全面にポリイミド等の樹脂
膜を形成して前記配線や電極を覆う工程と、前記樹脂膜
をプラズマエツチング法によりエツチングし、前記配線
や電極間にのみ前記樹脂膜を残す工程と、前記配線や電
極および樹脂膜を含む全面にプラズマＣＶＤ法により保
護膜を形成する工程とを含んでいる。The manufacturing method of the present invention includes a step of forming wirings and electrodes in a desired pattern on a semiconductor substrate, a step of forming a resin film such as polyimide on the entire surface to cover the wirings and electrodes, and a plasma etching method for the resin film. The method includes a step of etching to leave the resin film only between the wirings and electrodes, and a step of forming a protective film on the entire surface including the wirings, electrodes and resin film by plasma CVD.
本発明方法によれば、配線や電極間に残された樹脂膜に
よって半導体基板の表面の段差を緩和するため、上層に
形成される保護膜を平坦状態に形成することが可能とな
り、保護膜の性能を十分に発揮させることが可能となる
。According to the method of the present invention, the step difference on the surface of the semiconductor substrate is alleviated by the resin film left between the wiring and the electrodes, so that the protective film formed as an upper layer can be formed in a flat state. It becomes possible to fully demonstrate performance.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を工程順に示す縦断面図であ
る。FIG. 1 is a longitudinal sectional view showing an embodiment of the present invention in the order of steps.
先ず、第１図（ａ）のように、表面に絶縁膜を有する半
導体基板Ｉの表面に既知の方法にてアルミニウム配線２
やアルミニウムボンディング電極３を形成した後、約２
００ｃｐのポリイミド溶液を基板表面に滴下し、毎分５
０００回転にて３０秒間スピン塗布する。この後、１０
０°Ｃ，１時間、２５０°Ｃ３０秒間、４００°Ｃ，１
時間それぞれ窒素中にて加熱することにより、前記アル
ミニウム配線２やアルミニウムボンディング電極３を覆
う膜厚１．５μｍのポリイミド膜４を形成する。First, as shown in FIG. 1(a), an aluminum wiring 2 is formed on the surface of a semiconductor substrate I having an insulating film on the surface by a known method.
After forming the aluminum bonding electrode 3, about 2
A polyimide solution of 00 cp was dropped onto the substrate surface at a rate of 5 per minute.
Spin coating at 000 rpm for 30 seconds. After this, 10
0°C, 1 hour, 250°C, 30 seconds, 400°C, 1
By heating in nitrogen for each time, a polyimide film 4 having a thickness of 1.5 μm covering the aluminum wiring 2 and the aluminum bonding electrode 3 is formed.
次いで、直径約６０ｃｍの平行平板型リアクティブイオ
ンエッヂング装置（図示せず）にて酸素ガスを導入し、
圧力１０ｐａにし、／１．ＯＯＷの高周波電力を印加し
て同図（ｂ）のように、前記ポリイミド膜４をエツチン
グする。このとき、ポリイミド膜４のエツチングレート
は毎分１５００人であり、８分間エツチングを行なう。Next, oxygen gas was introduced using a parallel plate type reactive ion etching device (not shown) with a diameter of about 60 cm.
Set the pressure to 10pa, /1. By applying OOW high frequency power, the polyimide film 4 is etched as shown in FIG. 4(b). At this time, the etching rate of the polyimide film 4 was 1500 per minute, and etching was performed for 8 minutes.
これによってアルミニウム配線２やアルミニウムボンデ
ィング電極３間にのみポリイミド膜４を残し、この残さ
れたポリイミド膜４により前記アルミニラ１、配線２や
アルミニウムボンディング電極３の段差を緩和させる。As a result, the polyimide film 4 is left only between the aluminum wiring 2 and the aluminum bonding electrode 3, and the remaining polyimide film 4 alleviates the level difference between the aluminum wire 1, the wiring 2, and the aluminum bonding electrode 3.
次いで、同図（Ｃ）のように、プラズマＣＶＤ法を用い
、ＮＨ３とＳｉＴ］４とＮ２ガスを用いた既知の方法に
より、保護膜としてのシリコンナイトライド膜（シリコ
ン窒化膜）５を１μｍの厚さに形成する。Next, as shown in the same figure (C), a silicon nitride film (silicon nitride film) 5 as a protective film is formed to a thickness of 1 μm using a plasma CVD method using a known method using NH3, SiT]4, and N2 gas. Form into a thick layer.
次いで、同図（ｄ）のように、全面にフォトレジスト６
を塗布し、アルミニウムボンディング電極３上に窓を開
口し、かつこのフォトレジスト６を利用したフォトリソ
グラフィ法を用いてアルミニウムボンディング電極３上
のシリコンナイトライド膜５を選択的に除去する。除去
方法としては、枚葉型プラズマエツチング装置を用い、
酸素を２０％含んだＣＦ４ガスを用いて圧力Ｑ、５ｔｏ
ｒｒにし、２００Ｗの高周波電力を用いることによって
３分間でエツチングされる。Next, as shown in the same figure (d), a photoresist 6 is applied to the entire surface.
A window is opened on the aluminum bonding electrode 3, and the silicon nitride film 5 on the aluminum bonding electrode 3 is selectively removed using a photolithography method using the photoresist 6. The removal method uses a single-wafer plasma etching device.
Pressure Q, 5to using CF4 gas containing 20% oxygen
rr and etched in 3 minutes using 200W of high frequency power.
さらに、同図（ｅ）のように、酸素プラズマを用いた通
常のレジストプラズマ除去装置にてフォトレジスト６を
除去する。これにより、略平坦な状態の保護膜５が完成
される。Furthermore, as shown in FIG. 6(e), the photoresist 6 is removed using an ordinary resist plasma removal apparatus using oxygen plasma. As a result, the protective film 5 in a substantially flat state is completed.
なお、アルミニウムボンディング電極３の露呈面は外部
電極との電気接続を行うために利用されるものであるこ
とは言うまでもない。It goes without saying that the exposed surface of the aluminum bonding electrode 3 is used for electrical connection with an external electrode.
したがって、このように形成される保護膜５は、アルミ
ニウム配線２やアルミニウムボンディング電極３の段差
がポリイミド膜４によって緩和されるため、保護膜５は
平坦な状態で形成されることになり、耐湿性等の優れた
性能を発揮させることができる。これにより、半導体装
置の表面保護機能を十分に発揮させ、半導体装置の耐湿
性等の信頼性を向上させることが可能となる。Therefore, in the protective film 5 formed in this way, the step difference between the aluminum wiring 2 and the aluminum bonding electrode 3 is alleviated by the polyimide film 4, so the protective film 5 is formed in a flat state, and has moisture resistance. It is possible to exhibit excellent performance such as. This makes it possible to fully exhibit the surface protection function of the semiconductor device and improve reliability such as moisture resistance of the semiconductor device.
なお、ポリイミド膜４のエツチング方法とじては、枚葉
型プラズマエツチング装置を用い、酸素ガスを導入し、
０．５ｔｏｒｒの圧力にし、かつ半導体基板を１００°
Ｃに加熱した条件にてエツチングしてもよい。この場合
のポリイミド膜のエツチングレートは毎分約３００ＯＡ
であり、約３．５分のエツチングを行うことにより良好
なエツチングができる。The etching method for the polyimide film 4 is to use a single-wafer type plasma etching device, introduce oxygen gas,
The pressure is 0.5 torr, and the semiconductor substrate is held at 100°.
Etching may be performed under heating conditions of C. The etching rate of the polyimide film in this case is approximately 300 OA per minute.
Therefore, good etching can be achieved by etching for about 3.5 minutes.
また、シリコンナイトライド膜の代わりにプラズマＣＶ
Ｄ法によって成膜可能なプラズマオキシナイトライドを
利用してもよい。Also, instead of silicon nitride film, plasma CV
Plasma oxynitride, which can be formed into a film by method D, may be used.
以上説明したように本発明は、半導体基板上に形成した
配線や電極間に樹脂膜を残した状態で全面にプラズマＣ
ＶＤ法により保護膜を形成しているので、配線や電極間
に残された樹脂膜によって半導体基板の表面の段差を緩
和することができ、保護膜を平坦状態に形成することを
可能にして、保護膜の性能を十分に発揮させ、耐湿性等
の信頼性を高め半導体装置を製造することができる効果
がある。As explained above, in the present invention, plasma is applied to the entire surface of a semiconductor substrate while leaving a resin film between wirings and electrodes formed on the semiconductor substrate.
Since the protective film is formed using the VD method, the resin film left between the wiring and electrodes can reduce the level difference on the surface of the semiconductor substrate, making it possible to form the protective film in a flat state. This has the effect of allowing the performance of the protective film to be fully exhibited, improving reliability such as moisture resistance, and making it possible to manufacture semiconductor devices.
また、この場合、電極上には樹脂膜が存在していないた
め、電極上に開口を設けた場合でも、保護膜の開口部分
から内部への水分の侵入を防ぐことができ、耐湿性を劣
化させることはない。In addition, in this case, since there is no resin film on the electrode, even if an opening is provided on the electrode, moisture can be prevented from entering the inside through the opening in the protective film, reducing moisture resistance. I won't let you.
第１図（ａ）ないしくｅ）は本発明の製造方法を工程順
に示す断面図、第２図（ａ）ないしくｄ）は従来の製造
方法を工程順に示す断面図である。
１・・・半導体基板、２・・・アルミニウム配線、３・
・・アルミニウムボンディング電極、４・・・ポリイミ
ド膜、５・・・保護膜（シリコンナイトライド膜）、６
・・・フォトレジスト。
塚FIGS. 1(a) to 1e) are cross-sectional views showing the manufacturing method of the present invention in the order of steps, and FIGS. 2(a) to d) are sectional views showing the conventional manufacturing method in the order of steps. 1... Semiconductor substrate, 2... Aluminum wiring, 3...
... Aluminum bonding electrode, 4... Polyimide film, 5... Protective film (silicon nitride film), 6
...Photoresist. Mound
Claims (1)
る工程と、全面にポリイミド等の樹脂膜を形成して前記
配線や電極を覆う工程と、前記樹脂膜をプラズマエッチ
ング法によりエッチングし、前記配線や電極間にのみ前
記樹脂膜を残す工程と、前記配線や電極および樹脂膜を
含む全面にプラズマＣＶＤ法により保護膜を形成する工
程とを含むことを特徴とする半導体装置の製造方法。1. A step of forming wiring and electrodes in a desired pattern on a semiconductor substrate, a step of forming a resin film such as polyimide on the entire surface to cover the wiring and electrodes, and etching the resin film by a plasma etching method. A method for manufacturing a semiconductor device, comprising: a step of leaving the resin film only between wirings and electrodes; and a step of forming a protective film on the entire surface including the wirings, electrodes and resin film by plasma CVD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13320390A JPH0428231A (en) | 1990-05-23 | 1990-05-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13320390A JPH0428231A (en) | 1990-05-23 | 1990-05-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0428231A true JPH0428231A (en) | 1992-01-30 |
Family
ID=15099144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13320390A Pending JPH0428231A (en) | 1990-05-23 | 1990-05-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0428231A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1128323A2 (en) | 1999-12-27 | 2001-08-29 | Seiko Epson Corporation | Printer, printing method, and data storage medium |
| KR100353328B1 (en) * | 1999-03-15 | 2002-09-18 | 주성엔지니어링(주) | Method of forming TiN thin film |
| EP1615305A1 (en) * | 2004-07-06 | 2006-01-11 | Seiko Epson Corporation | VCSEL or LED with resin around the central portion to lower capacitance |
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| CN103579303A (en) * | 2012-08-02 | 2014-02-12 | 丰田自动车株式会社 | Semiconductor device and manufacturing method of same |
-
1990
- 1990-05-23 JP JP13320390A patent/JPH0428231A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8115284B2 (en) | 1996-12-04 | 2012-02-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument |
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7511362B2 (en) | 1996-12-04 | 2009-03-31 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7842598B2 (en) | 1996-12-04 | 2010-11-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
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| US7312476B2 (en) | 2004-07-06 | 2007-12-25 | Seiko Epson Corporation | Optical element and its manufacturing method |
| CN100409515C (en) * | 2004-07-06 | 2008-08-06 | 精工爱普生株式会社 | Optical element and its manufacturing method |
| CN103579303A (en) * | 2012-08-02 | 2014-02-12 | 丰田自动车株式会社 | Semiconductor device and manufacturing method of same |
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| CN103579303B (en) * | 2012-08-02 | 2017-06-06 | 丰田自动车株式会社 | Semiconductor device and its manufacture method |
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