JPH05251443A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05251443A
JPH05251443A JP4737792A JP4737792A JPH05251443A JP H05251443 A JPH05251443 A JP H05251443A JP 4737792 A JP4737792 A JP 4737792A JP 4737792 A JP4737792 A JP 4737792A JP H05251443 A JPH05251443 A JP H05251443A
Authority
JP
Japan
Prior art keywords
film
layer film
lower layer
semiconductor device
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4737792A
Other languages
Japanese (ja)
Inventor
Masataka Narita
政隆 成田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP4737792A priority Critical patent/JPH05251443A/en
Publication of JPH05251443A publication Critical patent/JPH05251443A/en
Pending legal-status Critical Current

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Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve a step coverage of an upper layer film on a step generated at an edge of a lower layer film. CONSTITUTION:A surface of a lower layer film 2 slightly inside from a part to become an edge of the film 2 is roughed. Thus, since adhesive strength of a mask is low outside from the roughed surface 6, side etching at the time of patterning the lower layer film is advanced, a tapered surface 7 is generated at the edge of the lower layer film, thereby improving a step coverage of an upper layer film 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体基板上に部分的
に形成された膜の縁部に生ずる段差にまたがって上層膜
が形成される半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which an upper layer film is formed over a step formed at an edge of a film partially formed on a semiconductor substrate.

【0002】[0002]

【従来の技術】半導体装置において基板上に被着する膜
としては、絶縁膜、電極あるいは配線を形成する金属な
どの導体膜、パッシベーション膜などがあり、それらが
積層される構造も多いことはよく知られている。その
際、下層の膜の縁部に生ずる段差部にまたがって上層膜
が形成されるときには、いわゆるステップカバレージの
問題が存在する。ステップカバレージを良好にするため
には、上層膜の膜厚を厚くするなどの方法がとられる。
2. Description of the Related Art In a semiconductor device, a film deposited on a substrate includes an insulating film, a conductor film such as a metal forming an electrode or a wiring, a passivation film, etc., and it is often the case that these structures are laminated. Are known. At that time, there is a problem of so-called step coverage when the upper layer film is formed straddling a step portion generated at the edge portion of the lower layer film. In order to improve the step coverage, a method such as increasing the film thickness of the upper layer film is used.

【0003】[0003]

【発明が解決しようとする課題】しかし、上層膜の膜厚
を厚くすることは、長い成膜時間を必要とし、さらにそ
の上に膜を形成するときのステップカバレージに悪い影
響がある。また、例えば図2に示すように、シリコン基
板1の上に形成された酸化膜2の縁部にまたがるAl配線
膜3を厚くしても、くびれ31、32が生ずることは基本的
に変化がなく、クラック発生等の問題があった。
However, increasing the film thickness of the upper layer film requires a long film forming time, and further has a bad influence on the step coverage when the film is formed thereon. Further, for example, as shown in FIG. 2, even if the Al wiring film 3 extending over the edge portion of the oxide film 2 formed on the silicon substrate 1 is thickened, the constrictions 31 and 32 are basically generated. However, there was a problem such as crack generation.

【0004】本発明の目的は、このような問題を解決
し、上層膜の膜厚を厚くすることなしに良好なステップ
カバレージが得られる信頼性の高い半導体装置の製造方
法を提供することにある。
An object of the present invention is to solve such problems and to provide a highly reliable method for manufacturing a semiconductor device which can obtain good step coverage without increasing the thickness of the upper layer film. .

【0005】[0005]

【課題を解決するための手段】上記の目的を達成するた
め、本発明は、下層膜の縁部に生ずる段差にまたがって
上層膜が設けられる半導体装置の製造方法において、選
択的エッチングのためのマスクに覆われる下層膜の表面
のマスクの縁部となるべき部分より所定の距離だけ離れ
た内側の部分を予め粗らしておき、そののちマスクパタ
ーンを形成して選択的エッチングを行い、上層膜がまた
がって設けられる下層膜の縁部にテーパ面を形成するも
のとする。そして、マスクがフォトマスク膜よりなるこ
と、下層膜が酸化膜であり、その表面を窒素ガス中で熱
処理するかあるいはプラズマエッチングで粗らすことが
有効である。
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device in which an upper layer film is provided over a step formed at an edge of the lower layer film. The inner portion of the surface of the lower layer film covered with the mask, which is separated from the portion to be the edge of the mask by a predetermined distance, is roughened in advance, and then a mask pattern is formed to selectively etch the upper layer film. The taper surface is formed at the edge of the lower layer film that is provided over. Then, it is effective that the mask is made of a photomask film, the lower layer film is an oxide film, and the surface thereof is heat-treated in nitrogen gas or roughened by plasma etching.

【0006】[0006]

【作用】上層膜がまたがって設けられる下層膜をパター
ニングするときのエッチングマスクの被着する表面が、
マスク縁部となるべき部分よりやや内側で粗らされてい
ると、マスクはその粗面とはよく密着するがその外側で
は密着がよくないため、エッチング液がその密着のよく
ない界面に侵入し下層膜の縁部にテーパ面が生ずる。そ
のため、この縁部にまたがって形成される上層膜のステ
ップカバレージは良好となる。
[Function] The surface to which the etching mask is applied when patterning the lower layer film provided over the upper layer film is
If the mask is roughened slightly inside the part that should be the edge of the mask, the mask adheres well to the rough surface but not to the outside, so that the etching solution penetrates into the interface where adhesion is poor. A tapered surface occurs at the edge of the lower layer film. Therefore, the step coverage of the upper layer film formed over the edge portion is good.

【0007】[0007]

【実施例】以下、図2と共通の部分に同一の符号を付し
た図1(a) 〜(i) を引用して本発明の一実施例について
説明する。まずシリコン基板1の上に熱酸化法等で1〜
1.5μmの厚さのシリコン酸化膜2を形成する (同図
(a))。次にその上にCVD法などでシリコン窒化膜4を
形成する (同図(b))。この窒化膜4の上にフォトリソグ
ラフィによりフォトレジスト膜5のパターンを形成し
(同図(c))、露出した窒化膜4をエッチングで除去する
(同図(d))。この際生じた窒化膜4のパターンは、その
後形成される酸化膜2のパターンの縁部の外側から縁部
の内側まで1〜1.5μmだけ入った位置まで達してい
る。次いでレジスト膜5を灰化したのち、酸化膜2の表
面の露出部分6を窒素雰囲気でのアニールによって粗ら
す (同図(e))。このあと、残った窒化膜4を除去し (同
図(f))、粗面6の1〜1.5μm外側まで被着するフォト
レジスト膜5のパターンを形成する (同図(g))。この状
態で酸化膜2のエッチングをすると、レジスト膜5の密
着強度は、粗面6より外側では弱いため、エッチング液
が界面に侵入してサイドエッチングが進み、酸化膜2の
縁部に約40℃の角度θをもつテーパ面7が生ずる (同図
(h))。従って、このテーパ面7を有する段差をまたがっ
て形成する配線用Al膜3のステップカバレージが良好に
なり、くびれ形状も生じない (同図(i )) 。なお、酸化
膜6の粗面化はプラズマエッチングによって行うことも
できる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 (a) to 1 (i) in which the same parts as those in FIG. First, 1 to 1 on the silicon substrate 1 by a thermal oxidation method or the like.
A silicon oxide film 2 having a thickness of 1.5 μm is formed (the same figure)
(a)). Next, a silicon nitride film 4 is formed thereon by a CVD method or the like (FIG. 2B). A pattern of the photoresist film 5 is formed on the nitride film 4 by photolithography.
((C) of the same figure), the exposed nitride film 4 is removed by etching
(Figure (d)). The pattern of the nitride film 4 generated at this time reaches a position where the pattern of the oxide film 2 to be formed thereafter is located within 1 to 1.5 μm from the outside of the edge to the inside of the edge. Next, after the resist film 5 is ashed, the exposed portion 6 on the surface of the oxide film 2 is roughened by annealing in a nitrogen atmosphere (FIG. 7E). After that, the remaining nitride film 4 is removed (FIG. 3F), and a pattern of the photoresist film 5 is formed so as to be deposited to the outside of 1 to 1.5 μm of the rough surface 6 (FIG. 2G). When the oxide film 2 is etched in this state, the adhesion strength of the resist film 5 is weaker outside the rough surface 6, so that the etching solution penetrates into the interface and side etching proceeds, and the edge of the oxide film 2 is exposed to about 40%. A tapered surface 7 having an angle θ of ℃ is generated (Fig.
(h)). Therefore, the step coverage of the wiring Al film 3 formed across the step having the tapered surface 7 becomes good, and the constricted shape does not occur ((i) in the same figure). The oxide film 6 may be roughened by plasma etching.

【0008】[0008]

【発明の効果】本発明によれば、下層膜のパターニング
前にその縁部となる部分より内側の部分で下層膜の表面
を粗面化してマスクとなる膜の密着性を向上させること
により、密着性の劣る部分でサイドエッチングが進むた
め、下層膜縁部にテーパ面を有する段差が生ずる。この
結果、上層膜のステップカバレージが良好となり、上層
膜厚を薄くすることができるので、成膜設備の稼働率が
向上し、また信頼性の高い半導体装置が製造できる。
According to the present invention, before the patterning of the lower layer film, the surface of the lower layer film is roughened at a portion inside the edge portion thereof to improve the adhesion of the film serving as a mask. Since side etching proceeds in a portion having poor adhesion, a step having a tapered surface is generated at the edge of the lower layer film. As a result, the step coverage of the upper layer film is improved and the upper layer film thickness can be reduced, so that the operating rate of the film forming equipment is improved and a highly reliable semiconductor device can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の酸化膜上の配線膜形成工程
を(a) ないし(i) の順に示す断面図
FIG. 1 is a sectional view showing the steps of forming a wiring film on an oxide film according to an embodiment of the present invention in the order of (a) to (i).

【図2】従来の酸化膜段差部上の配線膜を示す断面図FIG. 2 is a cross-sectional view showing a wiring film on a conventional oxide film step portion.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 酸化膜 3 Al膜 4 窒化膜 5 フォトレジスト膜 6 粗面 7 テーパ面 1 Silicon substrate 2 Oxide film 3 Al film 4 Nitride film 5 Photoresist film 6 Rough surface 7 Tapered surface

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】下層膜の縁部に生ずる段差にまたがって上
層膜が設けられる半導体装置の製造方法において、選択
的エッチングのためのマスクに覆われる下層膜の表面の
縁部となるべき部分より所定の距離だけ離れた内側の部
分を予め粗らしておき、そののちマスクパターンを形成
して選択的エッチングを行い、上層膜がまたがって設け
られる下層膜の縁部にテーパ面を形成することを特徴と
する半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, wherein an upper layer film is provided so as to extend over a step generated at an edge portion of a lower layer film, and a portion to be an edge portion of a surface of the lower layer film covered with a mask for selective etching. It is possible to roughen the inner part that is separated by a predetermined distance in advance, then form a mask pattern and perform selective etching to form a tapered surface at the edge of the lower layer film over which the upper layer film is provided. A method of manufacturing a semiconductor device having a feature.
【請求項2】マスクがフォトレジスト膜よりなる請求項
1記載の半導体装置の製造方法。
2. The method for manufacturing a semiconductor device according to claim 1, wherein the mask is made of a photoresist film.
【請求項3】下層膜が酸化膜であり、その表面を窒素ガ
ス中での熱処理により粗らす請求項1あるいは2記載の
半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the lower layer film is an oxide film, and the surface thereof is roughened by heat treatment in nitrogen gas.
【請求項4】下層膜が酸化膜であり、その表面をプラズ
マエッチングにより粗らす請求項1あるいは2記載の半
導体装置の製造方法。
4. The method for manufacturing a semiconductor device according to claim 1, wherein the lower layer film is an oxide film and the surface thereof is roughened by plasma etching.
JP4737792A 1992-03-05 1992-03-05 Manufacture of semiconductor device Pending JPH05251443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4737792A JPH05251443A (en) 1992-03-05 1992-03-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4737792A JPH05251443A (en) 1992-03-05 1992-03-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05251443A true JPH05251443A (en) 1993-09-28

Family

ID=12773409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4737792A Pending JPH05251443A (en) 1992-03-05 1992-03-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05251443A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999020686A3 (en) * 1997-10-20 1999-09-30 Uniroyal Chem Co Inc Organic materials stabilized by compounds containing both amine and hindered phenol functionalities
CN113764350A (en) * 2020-09-30 2021-12-07 台湾积体电路制造股份有限公司 Method of manufacturing transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999020686A3 (en) * 1997-10-20 1999-09-30 Uniroyal Chem Co Inc Organic materials stabilized by compounds containing both amine and hindered phenol functionalities
CN113764350A (en) * 2020-09-30 2021-12-07 台湾积体电路制造股份有限公司 Method of manufacturing transistor

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