JPS6035825B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS6035825B2
JPS6035825B2 JP13688379A JP13688379A JPS6035825B2 JP S6035825 B2 JPS6035825 B2 JP S6035825B2 JP 13688379 A JP13688379 A JP 13688379A JP 13688379 A JP13688379 A JP 13688379A JP S6035825 B2 JPS6035825 B2 JP S6035825B2
Authority
JP
Japan
Prior art keywords
film
conductive material
insulating film
electrode wiring
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13688379A
Other languages
Japanese (ja)
Other versions
JPS5661145A (en
Inventor
敏男 倉橋
敏彦 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13688379A priority Critical patent/JPS6035825B2/en
Publication of JPS5661145A publication Critical patent/JPS5661145A/en
Publication of JPS6035825B2 publication Critical patent/JPS6035825B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関し、特に平坦な表面
を有する埋込配線層の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a buried wiring layer having a flat surface.

集積回路装置(IC)や大規模集積回路装置(BI)に
多く用いられている多層配線を形成するには、所定のパ
ターンに従って形成された第1の配線体表面を絶縁膜で
被覆し、この絶縁膜に所定のパターンに従って閉口を設
け、次いで第2の配線体を被覆せしめるという方法が用
いられている。
To form multilayer wiring, which is often used in integrated circuit devices (IC) and large-scale integrated circuit devices (BI), the surface of a first wiring body formed according to a predetermined pattern is covered with an insulating film, and this A method is used in which a closure is provided in an insulating film according to a predetermined pattern, and then a second wiring body is covered.

しかしこのような方法では工程が進むにつれ半導体基板
表面の凹凸の段差が大きくなるのでパターニングが困難
になり、また絶縁膜の閉口の肩部における第2の配線体
を膜切れを生じる等の問題がある。
However, with this method, as the process progresses, the unevenness of the surface of the semiconductor substrate becomes larger, making patterning difficult, and there are also problems such as film breakage of the second wiring body at the shoulder of the closing part of the insulating film. be.

そこでこれの改善のため、第1図aに示すごとくシリコ
ン基板1表表面を被覆する二酸化シリコン膜2上に例え
ば燐シリケートグラス(PSG)よりなる絶縁膜3を、
形成すべき電極配線パターンを閉口部4とするホトレジ
スト膜5をマスクとして選択的に除去して絶縁膜3に閉
口6を設ける。
Therefore, in order to improve this, an insulating film 3 made of, for example, phosphorous silicate glass (PSG) is coated on the silicon dioxide film 2 covering the surface of the silicon substrate 1, as shown in FIG. 1a.
A photoresist film 5 with the electrode wiring pattern to be formed as a closed part 4 is selectively removed using a mask to provide a closed part 6 in the insulating film 3.

次いで同図bに示すようにアルミニウム(山)等電極配
線用導電材料を蒸着法或いはスパッタリング法を用いて
シリコン基板表面に彼着せしめ前記開□6内及びホトレ
ジスト膜5上に導電材料膜7及び7′を形成する。次い
で前記ホトレジスト膜5をプラズマ・アツシャ法等によ
り除去して、該ホトレジスト膜5上に被着せる導電材料
膜7′をリフトオフして同時に除去し、同図cに示すよ
うに絶縁膜3に導電材料層7則ち配線体7が埋込まれ且
つ片坦な表面を有する電極配線層を形成する方法が提唱
されている。
Next, as shown in Figure b, a conductive material for electrode wiring, such as aluminum (mountain), is deposited on the surface of the silicon substrate by vapor deposition or sputtering, and a conductive material film 7 and 7' is formed. Next, the photoresist film 5 is removed by a plasma attachment method or the like, and the conductive material film 7' deposited on the photoresist film 5 is lifted off and removed at the same time, and the conductive material is applied to the insulating film 3 as shown in FIG. A method has been proposed for forming an electrode wiring layer in which the layer 7, that is, the wiring body 7 is embedded and has a flat surface.

しかしこの方法も第2図aに示すごとく、絶縁膿3をホ
トレジスト膜5をマスクとしてエッチングする際にサイ
ドエッチングが避けられずホトレジスト膜5機部下側に
おいては横方向のエッチングも進行する。
However, as shown in FIG. 2A, in this method, side etching is unavoidable when the insulating pus 3 is etched using the photoresist film 5 as a mask, and lateral etching also progresses below the photoresist film 5.

そのため微細パターンの開口6及び6′を微細間隔で配
設するような場合には、同図bに示すように閉口6及び
6′間の絶縁膜3′の頂部の中が非常に狭いものとなり
ホトレジスト膜が剥離してしまう。
Therefore, when the openings 6 and 6' of a fine pattern are arranged at minute intervals, the inside of the top of the insulating film 3' between the closed openings 6 and 6' becomes very narrow, as shown in Figure b. The photoresist film peels off.

このあと前述のごとくアルミニウム(AI)等導電材料
を被着し、リフトオフ法により導電材料膜の不要部分を
除去しようちしても同図cに示すように前記閉口6,6
′に形成された導電材料膜7,7′間を分離することが
できない。
After that, as described above, even if a conductive material such as aluminum (AI) is deposited and an unnecessary portion of the conductive material film is removed by the lift-off method, the closed holes 6, 6 as shown in FIG.
It is not possible to separate the conductive material films 7 and 7' formed on the conductive material films 7 and 7'.

本方法はこのような難点を有するため微細パターンの電
極配線を形成することがむづかしいという問題がある。
Since this method has such drawbacks, it is difficult to form electrode wiring with a fine pattern.

本発明の目的は上記問題点を解消して微細パターン且つ
微細間隔の電極配線の形成を可能ならしめる埋込電極配
線層の形成方法を提供することにある。本発明の半導体
装置の製造方法の特徴は、半導体基板表面に電極配線を
形成するに当り、形成すべき電極配線パターンに従って
ホトレジスト膜を前記半導体基板表面に形成する工程と
、前記半導体基板表面に絶縁膜及び該絶縁膜との間にエ
ッチングの選択性を有する材料よりなる薄膜とを積層し
て被着する工程と、前記ホトレジスト膜を除去すること
により該ホトレジスト膜上に緋着せる前記絶縁膜及び薄
膜を同時に除去する工程と、前記半導体基被表面に電極
配線用導電材料膜を被着する工程と、前記薄膜を除去す
ることにより該薄膜上に被着せる電極配線用導電材料膜
を同時に除去する工程とを含むことにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a buried electrode wiring layer that solves the above-mentioned problems and enables the formation of electrode wiring with fine patterns and minute intervals. The method for manufacturing a semiconductor device of the present invention is characterized by a step of forming a photoresist film on the surface of the semiconductor substrate in accordance with an electrode wiring pattern to be formed when forming electrode wiring on the surface of the semiconductor substrate, and a step of forming an insulating film on the surface of the semiconductor substrate. A step of laminating and depositing a thin film made of a material having etching selectivity between the film and the insulating film, and removing the photoresist film to make the insulating film and the thin film scarlet on the photoresist film. a step of simultaneously removing a conductive material film for electrode wiring on the surface of the semiconductor substrate; and a step of simultaneously removing a conductive material film for electrode wiring to be deposited on the thin film by removing the thin film. It is to include.

以下本発明の半導体装置の製造方法の実施例を図面を用
いて説明する。
Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings.

第3図は上記実施例を工程の順に示す要部断面図である
FIG. 3 is a sectional view of a main part showing the above embodiment in the order of steps.

同図aに示すようにシリコン基板1表面を被覆する二酸
化シリコン(Si02)膜2上に形成すべき電極配線パ
ターンに従ってホトレジスト膜5を凡そ1.5〔仏m〕
の厚さに形成する。
As shown in FIG. 1A, the photoresist film 5 is coated approximately 1.5 [m] in accordance with the electrode wiring pattern to be formed on the silicon dioxide (Si02) film 2 covering the surface of the silicon substrate 1.
Form to a thickness of .

次いで同図bに示すように例えば一酸化シリコン(Si
○)よりなる絶縁膜3を凡そ1〔ムm〕の厚さに、更に
多結晶シリコンよりなる薄膜8を凡そ1000〔A〕の
厚丸こ蒸着法或いはスパッタリング法を用いて被着する
Next, as shown in Figure b, for example, silicon monoxide (Si
A thin film 8 made of polycrystalline silicon is deposited to a thickness of about 1 mm using circular evaporation or sputtering to a thickness of about 1000 A.

この時ホトレジスト膜5の厚さはSi○膜3と多結晶シ
リコンよりなる薄膜8の厚さの和よりも厚いので、ホト
レジスト膜5上に被着せるSi○膜3′及び薄膜8′は
Si○膜3及び薄膜8とは接続してし、ない。
At this time, the thickness of the photoresist film 5 is thicker than the sum of the thicknesses of the Si○ film 3 and the thin film 8 made of polycrystalline silicon. The membrane 3 and the thin membrane 8 are connected and not connected.

次いで前記ホトレジスト膜5をアツシャ法等を用いて除
去することにより、ホトレジスト膜5上に被着せるSi
○膜3′及び薄膜8′を同時に除去するりフトオフ法に
より、同図cに示すようにSi0よりなる絶縁膜3に関
口6を形成する。
Next, the photoresist film 5 is removed using an atssia method or the like to remove the Si deposited on the photoresist film 5.
○A gate 6 is formed in the insulating film 3 made of Si0 as shown in FIG.

該開ロ6を形成するに当ってエッチング法を用いていな
いので前述のごときサイドエッチングを生じることはな
い。
Since no etching method is used to form the opening 6, side etching as described above does not occur.

従って微細中の関口を微細間隔で精度良く形成すること
ができる。次いで同図dに示すようにアルミニウム (N)等の電極配線用導電材料を蒸着法またはスパッタ
リング法により凡そ1〔〆m〕の厚さに被着する。
Therefore, it is possible to accurately form fine-sized sekiguchi at fine intervals. Next, as shown in Figure d, a conductive material for electrode wiring such as aluminum (N) is deposited to a thickness of about 1 m by vapor deposition or sputtering.

この時も関口6内に被着せる導電材料層7と前記薄膜8
上に被着せる導電材料膜7′は接続していない。
At this time as well, the conductive material layer 7 and the thin film 8 to be deposited inside the Sekiguchi 6
The conductive material film 7' deposited thereon is not connected.

次いで同図eに示すように前記多結晶シリコン薄膜8を
、四塩化炭素(CF4)と酸素(02)との混合気体を
反応ガスとするプラズマエッチング法により除去するこ
とにより薄膜8上に被看せる導電材料膜7′を同時に除
去する。
Next, as shown in FIG. At the same time, the conductive material film 7' is removed.

以上により絶縁膜3に埋込まれた導電材料膜7を電極配
線体とする埋込配線層9が形成された。
Through the above steps, a buried wiring layer 9 having the conductive material film 7 buried in the insulating film 3 as an electrode wiring body was formed.

該錘込配線層9は絶縁膜3と電極配線体7の表面がほぼ
平坦な面をなすので、これを用いて多層配線を形成して
も断線を生じることがなく、しかもサイドエッチングが
ないので微細パターンの配線を精度よく形成することが
できる。上記工程中重要なことは薄膜8上の導電材料膜
′7′をリフトオフ可能とするため薄膜8と絶縁膜3の
材料を、薄膜8のみを選択的にエッチング可能な組み合
せとすることである。
Since the surfaces of the insulating film 3 and the electrode wiring body 7 of the plummeted wiring layer 9 form a substantially flat surface, there will be no disconnection even if multilayer wiring is formed using this layer, and there is no side etching. Fine pattern wiring can be formed with high precision. What is important in the above steps is to use a combination of materials for the thin film 8 and the insulating film 3 that allows only the thin film 8 to be selectively etched in order to enable the conductive material film '7' on the thin film 8 to be lifted off.

この選択エッチング可能な材料の組み合せの例のいくつ
かを第1表に示す。
Table 1 shows some examples of material combinations that can be selectively etched.

上記実施例は電極配線体を構成する導電材料をアルミニ
ウム(AI)とした場合について説明したが、導電材料
はアルミニウムに限定する必要はない。
Although the above embodiments have been described with reference to the case where the conductive material constituting the electrode wiring body is aluminum (AI), the conductive material does not need to be limited to aluminum.

例えば本発明を用いてMOSIC等に多く用いられる多
結晶シリコン配線体を形成する場合には、絶縁膜と薄膜
の材料の組み合せを第1表のNo.2,No.4或いは
No.5とすることにより実施できる。
For example, when using the present invention to form a polycrystalline silicon wiring body often used in MOSICs, etc., the combination of insulating film and thin film materials should be selected as shown in Table 1. 2, No. 4 or No. This can be implemented by setting 5.

上述のごとく本発明は使用する導電材料に応じて絶縁膜
と薄膜の材料を選択エッチング可能な組み合せを選択す
ることにより実施できる。また上記実施例では埋込配線
層を一層のみ形成する場合について説明したが、上記実
施例を繰り返し実施する等の方法により微細パターンの
多層配線を精度よく容易に形成できる。
As described above, the present invention can be implemented by selecting a combination of materials for the insulating film and thin film that can be selectively etched depending on the conductive material used. Further, in the above embodiments, the case where only one buried wiring layer is formed has been described, but by repeating the above embodiments, etc., it is possible to easily form multilayer wiring with fine patterns with high precision.

以上説明したごとく本発明によれば微細且つ高密度のし
かも平坦な表面を有する埋込配線層を精度よく容易に形
成することができる。
As described above, according to the present invention, a buried wiring layer having a fine, high-density, and flat surface can be easily formed with high precision.

従って断線や短絡を生じることなく多層化も容易となる
Therefore, multi-layering can be easily achieved without causing disconnections or short circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は従来の埋込配線の形成方法の説明に
供する要部断面図、第3図は本発明の実施例を示す要部
断面図である。 1・・・・・・半導体基板、3,3′・・・・・・絶縁
膜、5・・・…ホトレジスト膜、6……関口、7,7′
……導電材料膜、8・・・・・・薄膜、9・・・・・・
埋込配線層。 努〆図髪2図 弟3図
FIGS. 1 and 2 are sectional views of essential parts for explaining a conventional buried wiring forming method, and FIG. 3 is a sectional view of essential parts showing an embodiment of the present invention. 1... Semiconductor substrate, 3, 3'... Insulating film, 5... Photoresist film, 6... Sekiguchi, 7, 7'
... Conductive material film, 8... Thin film, 9...
Embedded wiring layer. Tsutomu hair 2 illustration younger brother 3 illustration

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板表面に電極配線を形成するに当り、形成
すべき電極配線パターンに従つてホトレジスト膜を前記
半導体基板表面に形成する工程と、絶縁膜及び該絶縁膜
との間にエツチングの選択性を有する材料よりなる薄膜
とを前記半導体基板表面積層して被着する工程と、前記
ホトレジスト膜を除去することにより該ホトレジスト膜
上に被着せる前記絶縁膜及び薄膜を同時に除去する工程
と、前記半導体表面に電極配線用導電材料膜を被着する
工程と、前記薄膜を除去することにより該薄膜上に被着
せる導電材料膜を同時に除去する工程とを含むことを特
徴とする半導体装置の製造方法。
1. When forming electrode wiring on the surface of a semiconductor substrate, a step of forming a photoresist film on the surface of the semiconductor substrate according to the electrode wiring pattern to be formed, and etching selectivity between the insulating film and the insulating film. a step of laminating and depositing a thin film made of a material on the semiconductor substrate surface; a step of simultaneously removing the insulating film and the thin film deposited on the photoresist film by removing the photoresist film; A method for manufacturing a semiconductor device, comprising the steps of: depositing a conductive material film for electrode wiring on the substrate; and removing the thin film and simultaneously removing the conductive material film deposited on the thin film.
JP13688379A 1979-10-23 1979-10-23 Manufacturing method of semiconductor device Expired JPS6035825B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13688379A JPS6035825B2 (en) 1979-10-23 1979-10-23 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13688379A JPS6035825B2 (en) 1979-10-23 1979-10-23 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5661145A JPS5661145A (en) 1981-05-26
JPS6035825B2 true JPS6035825B2 (en) 1985-08-16

Family

ID=15185765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13688379A Expired JPS6035825B2 (en) 1979-10-23 1979-10-23 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6035825B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6319618U (en) * 1986-07-22 1988-02-09
JPS63179322U (en) * 1987-05-14 1988-11-21
JPH08246569A (en) * 1995-03-09 1996-09-24 Yoshinori Yamauchi Earthquake-proof wall panel, and building ventilation construction method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177126A (en) * 1992-12-01 1994-06-24 Alps Electric Co Ltd Formation of multilayer thin film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6319618U (en) * 1986-07-22 1988-02-09
JPS63179322U (en) * 1987-05-14 1988-11-21
JPH08246569A (en) * 1995-03-09 1996-09-24 Yoshinori Yamauchi Earthquake-proof wall panel, and building ventilation construction method

Also Published As

Publication number Publication date
JPS5661145A (en) 1981-05-26

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