JPS5871638A - Etching method - Google Patents

Abstract

PURPOSE:To enable isolation by using a minute quantity of insulating material with a flattened surface by a method wherein only the contour (periphery) of an insular active region to be electrically isolated from other regions is selectively etched. CONSTITUTION:A mask pattern 12 composed of SiO2 film is formed on an Si substrate 11, to be followed by the formation on the entire surface of an Si3N4 film 13. By means of the reactive sputter etching method wherein Freon works as the reactive gas, said Si3N4 film 13 is etched. By this, the Si3N4 film 13 is removed, except the part, Si3N4 film 14, positioned on the side of the SiO2 film 12. The surface of the substrate 11 is then lightly oxidated, for the formation of an SiO2 film 15. The exposed surface 16 of the substrate 11 is etched by the well-known selective etching method.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an etching method, and more particularly to an etching method capable of finely etching the outline of a master pattern.

In the manufacture of various semiconductor devices, when forming independent island regions, conventionally, all portions other than the island regions have been removed by etching.

If the island-like regions are formed in this way, only the remaining island-like regions will be high and a step will be formed between them and other parts, which will cause problems in subsequent steps.

Therefore, in order to prevent the occurrence of such surface defects, regions other than the island-like regions must be buried so that one surface is flat, with the island-like regions electrically isolated.

FIG. 1 shows an example of a conventional insulation isolation method.
As shown in FIG. 1, a mask 2 is formed on a silicon substrate 1, and a hole 5 is formed leaving an island region 3.4.

Next, as shown in FIG. 1(2), an oxide film 6 is formed on the surface of the hole 5, and then silicon oxide, polycrystalline silicon, or the like 7 is filled into the hole 5 by a well-known CVD method or the like.

To flatten the upper part of the hole thus formed,
Methods have been proposed, such as removing silicon oxide existing in areas other than the holes by etching, and selectively growing polycrystalline silicon inside the holes, but the process is complicated and, for example, the flatness of the surface cannot be improved. There were some problems, such as not being very good, and solutions were requested.

The present invention has been made to solve the above-mentioned conventional problems, and is performed by selectively etching only the contour (periphery) of the island-shaped active region that should be separated from other regions at once. )1 The surface is flattened and fine isolation of insulators is possible.

Hereinafter, the present invention will be described in detail with reference to Examples.

Example 1 FIG. 2 is a process diagram showing an embodiment of the present invention.

First, as shown in FIG. 2(1), a well-known photoetching method is applied onto the silicon substrate 11.

1 After forming the mask pattern 12 consisting of 5101 m
Using the well-known CVD (Chemical Vapor Deposition) method.

84, N4 film 13 was formed on the entire surface.

When the above Si, N, and N films are etched by a reactive sputter etching method using Freon gas as a reactive gas, since this etching method causes almost no side etching, the film is not etched to 54 as shown in FIG. 2(2). It is possible to leave only the Si, N4 film 14 deposited on the sides of 12 and remove the 8i, N, film deposited on the other parts. The surface of the substrate 110 is lightly oxidized to give 8i0. membrane 15
form.

The remaining 8i, N, and film 14 are removed by etching using phosphoric acid as an etchant, and the surface 16 of the substrate 11 is exposed. At this time, as is clear from FIG. 2(2), only a very narrow portion of the periphery of the membrane 12 is exposed.

The exposed surface 16 of the substrate is then etched using a well-known selective etching method.

At this time, as the selective etching method mentioned above, CCZ4 and 0,
If you use a good quality sputter etch using a mixed gas of
As mentioned above, since the StO pattern can be etched vertically without side etching, a narrow groove 17 is formed at the periphery of the StO pattern 12, as shown in FIG. 2(3). Ru. In this etching method, the etching speed ratio of s8' and StO is t! Since it is 20 or more, StO,
Groove 17 without etching much of membrane 12.15.
can be formed.

The width of the groove 17 is determined by the thickness of the 81aNm film 14 deposited on the side surface of the stow pattern 12.

For example, it is possible to easily form a groove with a width of about 0.1 μm, and to control the width of the groove with an error of about 0.01 μm, which is different from normal CVD.

After removing the 5ift film 15 by etching with a hydrofluoric acid solution, an 8i0 film that continuously covers the substrate 11 and the groove 170 surface is removed.
．． After forming the film 18 by a well-known thermal oxidation method, s
z, N, 19 is deposited on the entire surface to fill the groove 17 as shown in FIG. 2(4).

As described above, according to the present invention, the width of the groove can be made extremely narrow, so that the groove can be filled with an extremely thin insulating film, and there are few irregularities on the surface, resulting in extremely high flatness.

In this embodiment, the inside of the groove was filled with SM and N4, but since the width of the groove is extremely narrow, the inside of the groove can be easily filled even if the increase in volume due to thermal oxidation is utilized.

FIG. 2(4) shows an example in which the active region 20 is insulated and isolated by the grooves formed in this way. It can also be used as an active region.

For example, if the mask pattern 23 is arranged as shown in FIG. 3(1) and the process is performed according to the above steps,
A region 25 in which a groove 24 having the planar shape shown in FIG. 3(2) is formed and should normally be inactive can be used as an active region.

At this platform. Since the inactive area is only $24, the required direct injection is significantly reduced and the density is the same.

Example 2 FIG. 4 is a process diagram showing another embodiment of the present invention.

First, as shown in FIG. 4(1), Si and N4h12 are placed on the sides of the StO film 26 used as a mask pattern.
7 is applied. This step can be performed once in the same manner as in Example 1.

A photoresist pattern 28 is formed on the portion other than the film 26 of 8iQ. At this time, in order to prevent the ends of the photoresist pattern 28 from overlapping the Sho film 26 and the Si, N4 film 27, they were formed with a distance from each other, taking into account an error in alignment.

After coating the entire surface with a photoresist film 29.

Si, N4f deposited on the side surface of the film 26
Remove the above photoresist until the top of i27 is exposed.
3Ashed and removed by plasma.

In this way, as shown in FIG. 4 (2).

The void between the Si, N, film 27 and the photoresist butter/28 is filled with the photoresist 29, and h
The upper end of S'@N4 a 27 is exposed and the next structure is obtained.

Then, as in the case of Example 1, Sj, N.

After removing the film 27, the exposed Bi substrate 11 is removed.

If etching is performed using an etching method with very little undercut, such as reactive sputter etching or microwave plasma etching, a groove 30 with a very narrow width will be formed as shown in FIG.

As is clear from the above description, the present invention exposes the surface of the substrate by removing the film deposited on the side edges of the mask pattern, and etches the exposed portion to form a groove. be.

The width of the exposed portion of the substrate is determined by the thickness of the removed film, which can be made extremely thin using the well-known CVD method. With etching, it is possible to etch almost vertically with almost no undercuts, making it possible to form extremely narrow grooves with a width of 1, which is impossible with conventional methods. There are seven steps to perform the separation.

In addition, in the above embodiment, the mask pattern is sio,
8i as a film, a film deposited on the side surface of the mask pattern;
N and membrane were used, respectively.

However, one membrane that can be used in the present invention is StO.

The present invention is not limited to the Si film and the N4 film, and many material films can be used.

That is, since the film deposited on the side surface is selectively removed without removing the mask pattern, films made of materials having significantly different etching speeds can be appropriately selected and used.

Also, the film deposited on the substrate surface during S formation.

As in the first embodiment, a film made of the same material as the mask pattern may be used, or as in the second embodiment, a film made of a different material may be used.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing a conventional insulation isolation method, FIGS. 2 and 4 are process diagrams showing different embodiments of the present invention, and FIG. 3 is a diagram showing the planar shape of a trench formed according to the present invention. It is a figure showing an example. 1.11...Si substrate 2 T11 mask, 3.4.
... Island-like region, 5,17.30 ... Hole, 6,15.1
8...Oxide film, 12,23.26...Mask pattern, 13°14.19...5isN<M@20,
25...Active region. 21.22... Inactive region, 28... Photoresist pattern, 29... Photoresist film. ￥I 1 Figure χ Z Figure Z Figure 7 fJ3 Figure

Claims (1)

[Claims] 1. After removing the film deposited on the side surface of the mask pattern formed on the surface of the semiconductor substrate to expose the surface of the semiconductor substrate, the exposing of the semiconductor substrate An etching method characterized in that a groove is formed in the semiconductor substrate by etching the etched portion. 2. The etching method according to claim 1, wherein the etching is performed by reactive sputter etching or microwave plasma etching.