JPS6410096B2 - - Google Patents
Info
- Publication number
- JPS6410096B2 JPS6410096B2 JP13380080A JP13380080A JPS6410096B2 JP S6410096 B2 JPS6410096 B2 JP S6410096B2 JP 13380080 A JP13380080 A JP 13380080A JP 13380080 A JP13380080 A JP 13380080A JP S6410096 B2 JPS6410096 B2 JP S6410096B2
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- wiring body
- sidewalls
- substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 7
- 239000011261 inert gas Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 8
- 238000000992 sputter etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に下
層配線体の肩部における上層配線体の断線を防止
する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for preventing disconnection of an upper layer wiring body at a shoulder portion of a lower layer wiring body.
LSI，超LSI等微細パターンを高密度に配設す
る半導体装置の配線は、幅の狭い配線体を微小間
隔でしかも多層化して形成される。そのため半導
体基板上に被着したアルミニウム（Al）等の金
属膜をパターニングするのに、垂直にエツチング
することのできるリアリテイブ・イオン・エツチ
ング法が用いられる。 Wiring for semiconductor devices such as LSIs and VLSIs in which fine patterns are arranged at high density is formed by multiple layers of narrow wiring bodies spaced at minute intervals. Therefore, to pattern a metal film such as aluminum (Al) deposited on a semiconductor substrate, a realistic ion etching method is used which allows vertical etching.
リアクテイブ・イオン・エツチング法はサイ
ド・エツチングを殆んど生じないので、これを用
いて形成した配線体の壁面はほぼ垂直となり、従
つて所望のパターンを精度良く形成できる。 Since the reactive ion etching method hardly causes side etching, the walls of the wiring body formed using this method are almost vertical, so that a desired pattern can be formed with high precision.
その反面配線体の肩部はほぼ直角となるため、
この上に絶縁膜を被覆し、更にその上に上層配線
体を形成した場合に、上述の配線体肩部における
段差のため上層配線体の断線を生じやすい。 On the other hand, the shoulders of the wiring body are almost at right angles, so
When an insulating film is coated on top of this and an upper layer wiring body is further formed thereon, the upper layer wiring body is likely to be disconnected due to the step difference at the shoulder portion of the wiring body.
本発明の目的はパターニングの精度を損なうこ
となく、配線体の肩部をなだらかにし得る半導体
装置の製造方法を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which the shoulders of a wiring body can be made gentle without impairing patterning accuracy.
本発明の特徴は、半導体基板表面に金属膜を被
着し、該金属膜を所定のパターンに従つて選択的
に除去して側壁が基板に略垂直な断面形状を有す
るように金属膜パターンを形成し、該金属膜パタ
ーンに不活性ガスイオンの衝撃を加えて、該側壁
の頂部の角の金属原子を該側壁に沿つて落下させ
て側壁底部の該基板上に堆積させる工程を含むこ
とにある。 The present invention is characterized in that a metal film is deposited on the surface of a semiconductor substrate, and the metal film is selectively removed according to a predetermined pattern to form a metal film pattern such that the sidewall has a cross-sectional shape substantially perpendicular to the substrate. and bombarding the metal film pattern with inert gas ions to cause metal atoms at the top corners of the sidewalls to fall along the sidewalls and deposit on the substrate at the bottom of the sidewalls. be.
以下本発明の一実施例を図面を用いて説明す
る。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を工程の順に示す要
部断面図である。先ず同図ａに示すようにシリコ
ン基板１表面を被覆する二酸化シリコン（SiO2）
膜２上にアルミニウム（Al）のような金属を蒸
着法またはスパツタリング法により被着してAl
膜３を形成し、更にその上に所定のパターンに従
つてホトレジスト膜４を選択的に形成する。 FIG. 1 is a sectional view of a main part showing an embodiment of the present invention in the order of steps. First, as shown in Figure a, silicon dioxide (SiO 2 ) is coated on the surface of a silicon substrate 1.
A metal such as aluminum (Al) is deposited on the film 2 by vapor deposition or sputtering.
A film 3 is formed, and a photoresist film 4 is selectively formed thereon according to a predetermined pattern.
次に同図ｂに示すように上記ホトレジスト膜を
マスクとするリアクテイブ・イオン・エツチング
によりAl膜３を選択的に除去してAl配線体３′を
形成し、ホトレジスト膜４を除去する。ここまで
の工程は通常の工程に従つて進めてよい。 Next, as shown in FIG. 4B, the Al film 3 is selectively removed by reactive ion etching using the photoresist film as a mask to form an Al wiring body 3', and the photoresist film 4 is removed. The steps up to this point may be carried out according to normal steps.
次にスパツタエツチング装置或いはイオンミリ
ング装置等を用いて、上記シリコン基板１の表面
にほぼ垂直に不活性ガスイオンを照射する。例え
ば平行平板電極のスパツタエツチング装置を用
い、圧力が約２×10-4〔Torr〕のアルゴン（Ar）
雰囲気にて、13.56MHzの高周波電力を加え、電
流を凡そ0.5〔ｍＡ／cm3〕流す。このようにするこ
とにより同図ｃに示すようにシリコン基板１表面
にほぼ垂直にAr+イオン５が照射され、Al配線体
３′はAr+イオン衝撃を受けて肩部６のAl粒子
（または原子）が下方にずり落ちて図示の如く肩
部６がなだらかになる。このAl粒子（または原
子）のずり落ちる量即ち変形させる度合はイオン
照射時間を調節することにより制御できる。本実
施例ではAl配線体３′の始めの寸法を厚さ約１
〔μｍ〕、幅を約２〔μｍ〕に形成しておき、イオ
ン照射後に幅が約2.6〔μｍ〕即ち片側凡そ0.3〔μ
ｍ〕づつずり落ちるように制御した。このように
して肩部６がなだらかに形成されたAl配線体
３″が得られた。 Next, using a sputter etching device, an ion milling device, or the like, the surface of the silicon substrate 1 is irradiated with inert gas ions almost perpendicularly. For example, using a sputter etching device with parallel plate electrodes, use argon (Ar) at a pressure of approximately 2×10 -4 [Torr].
In an atmosphere, a high frequency power of 13.56 MHz is applied, and a current of approximately 0.5 [mA/cm 3 ] is caused to flow. By doing this, Ar + ions 5 are irradiated almost perpendicularly to the surface of the silicon substrate 1, as shown in FIG. atoms) slide downward, and the shoulder 6 becomes gentle as shown in the figure. The amount by which the Al particles (or atoms) slip down, that is, the degree to which they are deformed, can be controlled by adjusting the ion irradiation time. In this embodiment, the initial dimension of the Al wiring body 3' is approximately 1 mm thick.
[μm], with a width of about 2 [μm], and after ion irradiation, the width becomes about 2.6 [μm], that is, about 0.3 [μm] on one side.
It was controlled so that it would slide down by [m]. In this way, an Al wiring body 3'' in which the shoulder portion 6 was formed smoothly was obtained.
なお上記工程において雰囲気はArに限定され
るものではないが、SiO2膜２に損傷を与えない
ため、非リアクテイブの状態とすることが必要
で、それには反応性を持たない不活性ガスを用い
る。 Note that the atmosphere in the above process is not limited to Ar, but in order not to damage the SiO 2 film 2, it is necessary to be in a non-reactive state, and an inert gas with no reactivity is used for this purpose. .
このあとは通常の工程に従つて進めて良く、即
ち同図ｄに示すように、Al配線体３″表面を含む
シリコン基板１上にリンシリケート・ガラス
（PSG）層のような絶縁膜７を形成し、その上に
Al等よりなる上層配線体８を形成する。このよ
うにして本発明に係る多層配線を有する半導体装
置が完成する。 After this, you can proceed according to the usual process, that is, as shown in FIG. form and on it
An upper layer wiring body 8 made of Al or the like is formed. In this way, a semiconductor device having multilayer wiring according to the present invention is completed.
本発明は上記一実施例に示した二層配線のみな
らず３層以上の多層配線を形成する場合にも勿論
適用し得る。 The present invention can of course be applied not only to the two-layer wiring shown in the above embodiment, but also to the formation of multilayer wiring of three or more layers.
また配線体材料もAlに限定されるものではな
く、モリブデン、タングステン、銅又はそれらの
シリサイドでもよい。 Further, the material of the wiring body is not limited to Al, but may be molybdenum, tungsten, copper, or silicide thereof.
以上説明したごとく本発明によれば配線体の肩
部をなだらかなものとすることができ、従つてこ
れを用いて形成した多層配線においては上層配線
体の断線を生じることがない。 As explained above, according to the present invention, the shoulder portion of the wiring body can be made gentle, and therefore, in the multilayer wiring formed using this, disconnection of the upper layer wiring body does not occur.
第１図は本発明の一実施例を示す要部断面図で
ある。
図において、１は半導体基板、３は金属膜、
３′，３″は金属配線体、５はイオン流、６は肩部
を示す。
FIG. 1 is a sectional view of a main part showing an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 3 is a metal film,
3' and 3'' are metal wiring bodies, 5 is an ion flow, and 6 is a shoulder.
Claims (1)
を所定のパターンに従つて選択的に除去して側壁
が基板に略垂直な断面形状を有するように金属膜
パターンを形成し、該金属膜パターンに不活性ガ
スイオンの衝撃を加えて、該側壁の頂部の角の金
属原子を該側壁に沿つて落下させて該側壁底部の
該基板上に堆積させる工程を含むことを特徴とす
る半導体装置の製造方法。1. A metal film is deposited on the surface of a semiconductor substrate, and the metal film is selectively removed according to a predetermined pattern to form a metal film pattern such that the side wall has a cross-sectional shape substantially perpendicular to the substrate. A semiconductor characterized by comprising the step of bombarding the film pattern with inert gas ions to cause metal atoms at the top corners of the sidewalls to fall along the sidewalls and deposit on the substrate at the bottom of the sidewalls. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13380080A JPS5759355A (en) | 1980-09-26 | 1980-09-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13380080A JPS5759355A (en) | 1980-09-26 | 1980-09-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5759355A JPS5759355A (en) | 1982-04-09 |
| JPS6410096B2 true JPS6410096B2 (en) | 1989-02-21 |
Family
ID=15113316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13380080A Granted JPS5759355A (en) | 1980-09-26 | 1980-09-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5759355A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4569708A (en) * | 1984-07-16 | 1986-02-11 | Shinko Kosen Kogyo Kabushiki Kaisha | Method for covering cables with sheaths for corrosion protection and/or aesthetics |
| JPS6281065A (en) * | 1985-10-04 | 1987-04-14 | Hosiden Electronics Co Ltd | Thin film transistor |
| JPS6280626A (en) * | 1985-10-04 | 1987-04-14 | Hosiden Electronics Co Ltd | Liquid crystal display element |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7701559A (en) * | 1977-02-15 | 1978-08-17 | Philips Nv | CREATING SLOPES ON METAL PATTERNS, AS WELL AS SUBSTRATE FOR AN INTEGRATED CIRCUIT PROVIDED WITH SUCH PATTERN. |
-
1980
- 1980-09-26 JP JP13380080A patent/JPS5759355A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5759355A (en) | 1982-04-09 |
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