JPS6281065A - Thin film transistor - Google Patents

Thin film transistor

Info

Publication number
JPS6281065A
JPS6281065A JP60221667A JP22166785A JPS6281065A JP S6281065 A JPS6281065 A JP S6281065A JP 60221667 A JP60221667 A JP 60221667A JP 22166785 A JP22166785 A JP 22166785A JP S6281065 A JPS6281065 A JP S6281065A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor layer
thin film
film transistor
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60221667A
Other languages
Japanese (ja)
Inventor
Shigeo Aoki
茂雄 青木
Yasuhiro Ukai
育弘 鵜飼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hosiden Electronics Co Ltd
Original Assignee
Hosiden Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hosiden Electronics Co Ltd filed Critical Hosiden Electronics Co Ltd
Priority to JP60221667A priority Critical patent/JPS6281065A/en
Priority to EP86113674A priority patent/EP0217406B1/en
Priority to DE8686113674T priority patent/DE3685623T2/en
Priority to AT86113674T priority patent/ATE77177T1/en
Priority to KR1019860008313A priority patent/KR900000066B1/en
Publication of JPS6281065A publication Critical patent/JPS6281065A/en
Priority to US07/222,296 priority patent/US4864376A/en
Priority to US07/399,141 priority patent/US5061648A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)

Abstract

PURPOSE:To finely perform the gradation display and to enable a high-speed operation by a method wherein the semiconductor layer is made thinner and its resistivity is made sufficiently higher by forming the opposing side surfaces of source and drain electrodes each into a tapered surface. CONSTITUTION:The opposing side surfaces of a drain electrode 15a and a source electrode 19a are formed into tapered surfaces 31 and 32. Therefore, a semiconductor layer 21 is made sufficiently thinner, its resistivity is increased, the OFF-state resistance of a thin film transistor is hard to be affected by the external light, a large OFF-state resistance can be obtained and a light-shielding layer 25 can be omitted. Furthermore, ohmic contact layers 27 and 28 are formed over the whole surfaces of these tapered surfaces 31 and 32, and the semiconductor layer 22 and the electrodes 15a and 19a can be brought into an ohmic contact with each other over a sufficient area. Therefore, the characteristics of a drain current (a) us a drain voltage (b) become good ones having no offset as indicated by solid lines. Furthermore, the maximum drain current also is increased, a current can be supplied to a display electrode at high speed, a high speed operation becomes possible and furthermore, as the characteristics have no offset, the control range is wide in the case of the gradation display and moreover, the gradation display can be performed sufficiently and accurately.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は例えば特に大市債高精細なアクティブ液晶表
示素子の各表示電極を選択するためのスイッチ素子に適
する薄膜トランジスタ（二関するものである。DETAILED DESCRIPTION OF THE INVENTION "Industrial Application Field" The present invention relates to a thin film transistor suitable as a switching element for selecting each display electrode of a large, high-definition active liquid crystal display element, for example.

「従来の技術」 まず従来のアクティブ液晶表示素子を第５図を参照して
説明する。ガラスのような透明基板１１及び１２が近接
対向して設けられ、その周縁部にはスペーサ１３が介在
され、これら透明基板１１゜１２間に液晶１４が封入さ
れている。一方の透明基板１１の内面に表示電極１５が
複数形成され、これら各表示電極１５に接してそれぞれ
スイッチング素子として薄膜トランジスタ１６が形成さ
れ、その薄膜トランジスタ１６のドレインは表示電極１
５に接続されている。これら複数の表示電極１５と対向
して他方の透明基板１２の内面に透明な共通電極１７が
形成されている。"Prior Art" First, a conventional active liquid crystal display element will be explained with reference to FIG. Transparent substrates 11 and 12 such as glass are provided close to each other, a spacer 13 is interposed at the periphery thereof, and a liquid crystal 14 is sealed between these transparent substrates 11 and 12. A plurality of display electrodes 15 are formed on the inner surface of one transparent substrate 11, and a thin film transistor 16 is formed as a switching element in contact with each display electrode 15, and the drain of the thin film transistor 16 is connected to the display electrode 11.
5. A transparent common electrode 17 is formed on the inner surface of the other transparent substrate 12, facing the plurality of display electrodes 15.

表示電極１５は例えば画素電極であって第６図に示すよ
うに、透明基板１１上に正方形の表示電極１５が行及び
列に近接配列されており、表示電極１５の各行配列と近
接し、かつこれに沿ってそれぞれダートバス１８が形成
され、また表示電極１５の各列配列と近接してそれに沿
ってソースパス１９がそ゛れぞれ形成されている。これ
ら各ダートパス１８及びソースパス１９の交差点におい
て薄膜トランジスタ１６が設けられ、各薄膜トランジス
タ１６のダートは両パスの交差点位置においてゲートパ
ス１８に接続され、各ソースはソースパス１９にそれぞ
れ接続され、更に各ドレインは表示電極１５に接続され
ている。The display electrodes 15 are, for example, pixel electrodes, and as shown in FIG. 6, square display electrodes 15 are arranged close to each other in rows and columns on the transparent substrate 11. Dirt buses 18 are formed along these lines, and source paths 19 are formed adjacent to and along each column arrangement of display electrodes 15. A thin film transistor 16 is provided at the intersection of each dirt path 18 and source path 19, the dirt of each thin film transistor 16 is connected to the gate path 18 at the intersection of both paths, each source is connected to the source path 19, and each drain is connected to the gate path 18. It is connected to the display electrode 15.

これらケ０−トパス１８とソースパス１９との各一つを
選択してそれら間に電圧を印加し、その電圧が印加され
た薄膜トランジスタ１６のみが導通し、その導通した薄
膜トランジスタ１６のドレインに接続された表示電極１
５に電荷を蓄積して表示電極１５と共通電極１７との間
の液晶１４の部分においてのみ電圧を印加し、これによ
って表示電極１５の部分のみを光透明或は光遮断とする
ことによって選択的な表示を行う。この表示電極１５に
蓄積した電荷を放電させることによって表示を消去させ
ることができる。By selecting each one of the keto path 18 and the source path 19 and applying a voltage between them, only the thin film transistor 16 to which the voltage has been applied becomes conductive, and is connected to the drain of the thin film transistor 16 that has become conductive. Display electrode 1
5, and apply a voltage only to the portion of the liquid crystal 14 between the display electrode 15 and the common electrode 17, thereby selectively making only the portion of the display electrode 15 transparent or blocking light. display. The display can be erased by discharging the charges accumulated in the display electrodes 15.

薄膜トランジスタ１６は従来においては例えば第６図及
び第８図に示すように構成されていた。The thin film transistor 16 has conventionally been constructed as shown in FIGS. 6 and 8, for example.

即ち透明基板１１上に表示電極１５とソース・々ス１９
とがＩＴＯのような透明導電膜によって形成され、表示
電極１５及びソースパス１９の互に平行近接した部分間
にまたがってアモルファスシリコンのような半導体層２
１が形成され、更にその上窒化シリコンなどのダート絶
縁膜２２が形成される。このケ°−ト絶縁膜２２上にお
いて半導体層２１を介して表示電極１５及びノースパス
１９とそれぞれ一部重なってダート電極２３が形成され
る。That is, a display electrode 15 and a source 19 are disposed on a transparent substrate 11.
is formed of a transparent conductive film such as ITO, and a semiconductor layer 2 such as amorphous silicon is formed across parallel and adjacent portions of the display electrode 15 and the source path 19.
A dirt insulating film 22 made of silicon nitride or the like is further formed thereon. A dart electrode 23 is formed on the gate insulating film 22 so as to partially overlap the display electrode 15 and the north path 19 with the semiconductor layer 21 in between.

ダート電極２３の一端はダートバス１８に接続される。One end of the dart electrode 23 is connected to the dart bus 18.

このようにしてｒ−）電極２３とそれぞれ対向した表示
電極１５、ソース・マス１９はそれぞれドレイン電極１
５ａ、ソース電極１９ａを構成し、これら電極１５ａ、
１９ａ、半導体層２１、ダート絶縁膜２２、ｒ−）電極
２３によって薄膜トランジスタ１６が構成される。デー
ト電極２３及びゲートパス１８は同時に形成され、例え
ばアルミニウムによって構成される。In this way, the display electrode 15 and the source mass 19, which are opposite to the r-) electrode 23, are connected to the drain electrode 1, respectively.
5a, constitutes the source electrode 19a, and these electrodes 15a,
19a, the semiconductor layer 21, the dirt insulating film 22, and the r-) electrode 23 constitute the thin film transistor 16. The date electrode 23 and the gate path 18 are formed at the same time and are made of aluminum, for example.

なお半導体層２２は光が当ると導電性を示すいわゆる光
導電効果を持つため、その薄膜トランジスタ１６が不導
通の時に外部から光が半導体層２２に入射されるとオフ
抵抗が小さくなり、トランジスタ１６のオンオフ比が低
下する。このため第８図に示すように透明基板１１に半
導体層２２と対向して遮光層２５が形成され、遮光層２
５上だ保護層２６が形成され、その保護層２６上にドレ
イン電極１５ａ、ソース電極１９ａなどが形成されてい
る。またドレイン電極１５ａ及びソース電極１９ａと半
導体層２２とのオーミック接触を良好にするためｎプラ
スのオーミック接触層２７．２８がそれぞれ形成され、
その上に半導体層２２が形成されている。更に液晶に対
する保護のためにダート電極２４上に全体を覆って保護
層２９が形成されている。Note that the semiconductor layer 22 has a so-called photoconductive effect that shows conductivity when exposed to light, so if light is incident on the semiconductor layer 22 from the outside while the thin film transistor 16 is non-conducting, the off-resistance of the transistor 16 decreases. On-off ratio decreases. For this reason, as shown in FIG. 8, a light shielding layer 25 is formed on the transparent substrate 11 facing the semiconductor layer 22.
A protective layer 26 is formed on the protective layer 5, and a drain electrode 15a, a source electrode 19a, etc. are formed on the protective layer 26. Further, in order to improve the ohmic contact between the drain electrode 15a and the source electrode 19a and the semiconductor layer 22, n-plus ohmic contact layers 27 and 28 are formed, respectively.
A semiconductor layer 22 is formed thereon. Furthermore, a protective layer 29 is formed to cover the entire dart electrode 24 to protect the liquid crystal.

「発明が解決しようとする問題点」 表示画面の大きい液晶表示素子とするとそのソースパス
１９及びゲートパス１８の長さが長くなり、また精細な
表示をするには表示電極１５の分布密度を大とする必要
がちシ、従って何れの場合においてもソースパス１９の
長さが長くなり、かつ薄膜トランジスタ１６及び表示電
極１５の分布密度を高くする必要がある。このようにす
ると選択されたソースパス１９の電源に近い側と離れた
側とで電圧降下により電圧が異ガリ、このためその選択
された表示電極に対する印加電圧が場所によって異なっ
て、全体として輝度傾斜が生じ、つまシミ源から離れる
に従って輝度が低下する。このような点からソースパス
１９の厚さを十分厚くすることが好ましい。つまりソー
スパス１９の厚さを十分厚くしてその抵抗値を小さくし
、表示面の全面にわたって同一輝度が得られるようにす
ることが好ましい。"Problems to be Solved by the Invention" When a liquid crystal display element with a large display screen is used, the lengths of the source path 19 and gate path 18 become long, and the distribution density of the display electrodes 15 must be increased in order to provide a fine display. Therefore, in either case, the length of the source path 19 becomes long, and it is necessary to increase the distribution density of the thin film transistor 16 and the display electrode 15. In this way, the voltage is different due to a voltage drop between the side close to the power supply of the selected source path 19 and the side far away from the power supply, and therefore the voltage applied to the selected display electrode differs depending on the location, resulting in a brightness gradient as a whole. occurs, and the brightness decreases as the distance from the stain source increases. From this point of view, it is preferable to make the source path 19 sufficiently thick. In other words, it is preferable to make the source path 19 sufficiently thick to reduce its resistance value so that the same brightness can be obtained over the entire display surface.

また半導体層２２の光導電効果にもとすき外部の光によ
って薄膜トランジスタが影響されないようにするては半
導体層２２をなるべく薄くした方がよい。ところで従来
においては電極１５８゜１９ａとなるべき透明導電膜を
形成し、更にオーミック接二゛蝙層；２７．ｚｓとなる
べきｎプラス層を形成し、その後エツチングによって所
定の形状として表示電極１５やソースパス１９を形成し
ていた。その際に高密度のパタンを得るため、横方向の
エンチングが少なく、基板１１に対して垂直方向のエツ
チングのみが主として行われるような異方性エツチング
処理を行っていた。従ってソースパス１９の側面は基板
１１と垂直であり、ソースパス１９の厚さを十分厚くす
ると、パス１９の側面に対し半導体層２２が良好に付着
しなくなるため、半導体層２２の厚さもある程度以上必
要とし、従来においては例えば１０００Ｘ位の厚さを必
要としていた。このように半導体層２２の厚さが比較的
厚いため、光による光導電効果が薄膜トランジスタに大
きく影響していた。このため第８図について述べたよう
に遮光層２５を必要としており、それだけ製造工程が複
雑となっていた。また小形化するに従ってオーミック接
触層２７．２８の幅が狭くなり、それだけこれら電極１
５ａ、１９ａと半導体層２２とのオーミック接触が良好
なものとならなかった。このため薄膜トランジスタ１６
のドレイン電圧対ドレイン電流特性にオフセットがあり
、ドレイン電圧をある程度以上大きくしないとドレイン
電流が流れ始めない。従って階調表示を行う場合に制御
範囲が狭いものとなっていた。Furthermore, in order to prevent the thin film transistor from being affected by external light due to the photoconductive effect of the semiconductor layer 22, it is better to make the semiconductor layer 22 as thin as possible. By the way, in the conventional method, a transparent conductive film to be the electrode 158° 19a is formed, and an ohmic contact layer; 27. An n-plus layer to become zs is formed, and then the display electrode 15 and source path 19 are formed into a predetermined shape by etching. At this time, in order to obtain a high-density pattern, an anisotropic etching process is performed in which etching in the lateral direction is small and etching is mainly performed in the vertical direction with respect to the substrate 11. Therefore, the side surface of the source path 19 is perpendicular to the substrate 11, and if the thickness of the source path 19 is made sufficiently thick, the semiconductor layer 22 will not adhere well to the side surface of the path 19. Conventionally, a thickness of about 1000X was required, for example. Since the semiconductor layer 22 is relatively thick as described above, the photoconductive effect caused by light has a large influence on the thin film transistor. For this reason, as described with reference to FIG. 8, the light shielding layer 25 is required, which complicates the manufacturing process accordingly. Furthermore, as the size becomes smaller, the width of the ohmic contact layers 27 and 28 becomes narrower, and these electrodes 1
The ohmic contact between 5a and 19a and the semiconductor layer 22 was not good. Therefore, the thin film transistor 16
There is an offset in the drain voltage vs. drain current characteristics of the device, and the drain current will not start flowing unless the drain voltage is increased beyond a certain level. Therefore, the control range when performing gradation display is narrow.

「問題点を解決するための手段」 この発明によればソース電極とドレイン電極との対向す
る側面はそれぞれテーパ面とされて、そのテーパ面の全
面にわたってオーミック接触層が形成され、そのオーミ
ック接触層を介して半導体層が形成されている。このよ
うにドレイン電極、ソース電極の対向側面はテーノや面
となっているため、その上に形成される半導体層を薄く
、例えば、５００Ｘ以下、１００乃至２００Ｘ、つまシ
従来の１０分の工程度にすることができ、従って半導体
層の抵抗を十分高くすることができ、また薄いため光導
電効果によるオフ時の抵抗を十分高くすることができる
。"Means for Solving the Problem" According to the present invention, the opposing side surfaces of the source electrode and the drain electrode are each made into a tapered surface, and an ohmic contact layer is formed over the entire surface of the tapered surface. A semiconductor layer is formed through the . Since the opposing sides of the drain electrode and source electrode are flat surfaces, the semiconductor layer formed thereon can be thinned, for example, by 500X or less, 100 to 200X, or less than the conventional 10 minute process time. Therefore, the resistance of the semiconductor layer can be made sufficiently high, and since it is thin, the off-state resistance due to the photoconductive effect can be made sufficiently high.

またドレイン電極及びソース電極としてリン又はホウ素
を含む透明電極を用いると、半導体層を例えばプラズマ
ＣＶＤ法によって形成する際に、そのリンやホウ素が透
明電極から析出して半導体層に拡散し、ドレイン電極、
ソース電極と接触する部分の全面にｎプラス層或いはｐ
ブラフ層のオーミック接触層が自動的に得られる。しか
もこれら透明電極のインジュウムや錫などが半導体層に
浸入するのが、そのリン或いはホウ素との結合によって
阻止され、良好な半導体層が得られる。Furthermore, if a transparent electrode containing phosphorus or boron is used as the drain electrode and source electrode, when forming the semiconductor layer by, for example, plasma CVD, the phosphorus or boron will precipitate from the transparent electrode and diffuse into the semiconductor layer, causing the drain electrode to ,
An n-plus layer or p
The ohmic contact layer of the bluff layer is automatically obtained. Furthermore, indium, tin, and the like of these transparent electrodes are prevented from penetrating into the semiconductor layer by their combination with phosphorus or boron, resulting in a good semiconductor layer.

「実施例」 第１図はこの発明による薄膜トランジスタの実施例を示
し、第８図と対応する部分には同一符号を付しである。Embodiment FIG. 1 shows an embodiment of a thin film transistor according to the present invention, and parts corresponding to those in FIG. 8 are given the same reference numerals.

この発明においてはドレイン電極１５ａ、ソース電極１
９ａの対向側面はチーｉｅ面３１．３２とされている。In this invention, the drain electrode 15a, the source electrode 1
The opposite side surface of 9a is a chiie surface 31.32.

このテーパ面３１　、３２は例えば、透明導電膜を形成
した後、その透明導電膜をエツチングして表示電極１５
、更にソースパス１９を形成する際に、等方性エツチン
グを施すことにより形成する。つまりそのエツチングは
基板１１に対して垂直方向と水平方向とに同一速度で行
われ、このチーツク面３１．３２はそれぞれ基板１１に
対し４５°程度のものとなる。These tapered surfaces 31 and 32 are formed by, for example, forming a transparent conductive film and then etching the transparent conductive film to form the display electrodes 15.
Furthermore, when forming the source path 19, it is formed by performing isotropic etching. That is, the etching is performed at the same speed in the vertical and horizontal directions with respect to the substrate 11, and the cheek surfaces 31, 32 are each at an angle of about 45° to the substrate 11.

このテーパ面３１．３２の少くとも全面におい−て例え
ばｎプラスのオーミック接触層２７　、２８が形成され
、更にその上に半導体層２２がアモルファスシリコンに
よって形成される。この上にダート絶縁膜２３、ｒ−）
電極２４を形成し、更に保護層２９を形成する。For example, n-plus ohmic contact layers 27 and 28 are formed on at least the entire surface of the tapered surfaces 31 and 32, and a semiconductor layer 22 made of amorphous silicon is formed thereon. On this, a dirt insulating film 23, r-)
An electrode 24 is formed, and a protective layer 29 is further formed.

オーミック接触層２７．２８としては表示電極１５、ソ
ースパス１９を形成した後、ｎプラス層を全面にわたっ
て形成し、そのｎプラス層を所定のパタンにエツチング
処理した後、半導体層２２を形成してもよいが、次のよ
うにするのが好ましい。すなわち電極１５、ソースパス
１９として例えばＩＴＯ（酸化インジウム及び酸化錫）
や酸化錫などが用いられるが、これら透明電極として、
例えばリンを含んだものを用いる。このようにリンを含
んだものを用いるとオーミック接触層２７゜２８のみを
形成するための工程を設けることなく半導体層２２を電
極１５ａ、１９ａ上に例えば基板１１を２００℃乃至３
００℃程度とし、プラズマＣＶＤ法により直接形成する
。その際に電極１５ａ。As the ohmic contact layers 27 and 28, after forming the display electrode 15 and the source path 19, an n-plus layer is formed over the entire surface, and after etching the n-plus layer into a predetermined pattern, the semiconductor layer 22 is formed. However, it is preferable to do the following. That is, for example, ITO (indium oxide and tin oxide) is used as the electrode 15 and the source path 19.
and tin oxide are used, but as these transparent electrodes,
For example, use one containing phosphorus. If a material containing phosphorus is used in this way, the semiconductor layer 22 can be formed on the electrodes 15a and 19a by heating the substrate 11 at 200°C to 30°C without providing a process for forming only the ohmic contact layers 27 and 28.
The temperature is about 00° C., and the film is directly formed by plasma CVD. At that time, the electrode 15a.

１９ａ中のリンが析出し、これが半導体層２２に拡散し
、ｎプラスのオーミック接触層３１．３２が電極１５ａ
、１９ａとの接触面に自動的に得られる。しかもこの場
合は透明電極１５ａ、１９ａ中のインジュウムや錫など
がその透明電極中のリンと結合して析出し難くなり、イ
ンソユウムや錫が半導体層２２に拡散して悪影響を及ぼ
すおそれもない。Phosphorus in 19a is precipitated and diffused into the semiconductor layer 22, and n-plus ohmic contact layers 31 and 32 form electrodes 15a.
, 19a automatically. Furthermore, in this case, indium, tin, and the like in the transparent electrodes 15a and 19a combine with phosphorus in the transparent electrodes and are difficult to precipitate, and there is no fear that indium or tin will diffuse into the semiconductor layer 22 and have an adverse effect.

このようにこの発明においてはドレイン電極１５ａ、ソ
ース電極１９ａの対向側面はチー１８面３１．３２とさ
れているため、半導体層２２を十分薄く、例えば１００
乃至２００Ｘ程度にしても、その電極１５ａ、１９ａと
の対接面に全面にわたり良好に接触する。このように半
導体層２２を薄くすると、その抵抗値が大きくなり、薄
膜トランジスタのオフ抵抗が外部の光によって影響され
難く、大きなオフ抵抗が得られ、遮光層２５を省略する
ことができる。In this way, in the present invention, since the opposite side surfaces of the drain electrode 15a and the source electrode 19a are made into a chi 18 plane 31.32, the semiconductor layer 22 is made sufficiently thin, for example, 100 mm.
Even at a magnification of about 200X, the contact surface with the electrodes 15a and 19a can be satisfactorily contacted over the entire surface. When the semiconductor layer 22 is made thinner in this manner, its resistance value increases, the off-resistance of the thin film transistor is less likely to be affected by external light, a large off-resistance is obtained, and the light shielding layer 25 can be omitted.

またオーミック接触層２７．２８がこのチー１８面３１
．３２の全面にわたって形成され、十分な面積をもって
半導体層２２と電極１５ａ、１９ａとをオーミック接触
させることができ、このためドレイン電圧対ドレイン電
流特性は第２図に実線で示すようにオフセットのない良
好なものとなる。Also, the ohmic contact layer 27, 28 is on this chip 18 surface 31.
．． The semiconductor layer 22 and the electrodes 15a, 19a can be brought into ohmic contact with a sufficient area, and therefore the drain voltage vs. drain current characteristics are good with no offset, as shown by the solid line in FIG. Become something.

従来においては点線で示すようにオフセットがあり、し
かも最大ドレイン電流もこの発明によるものよりも小さ
なものであった。従ってそれだけ従来のものよりも高速
度で表示電極に対し電流を供給することができ、高速動
作が可能となり、かつオフセットがないために階調表示
の場合、その制御範囲が広く、かつ十分きめ細かに行う
ことが可能となる。In the conventional case, there was an offset as shown by the dotted line, and the maximum drain current was also smaller than that according to the present invention. Therefore, it is possible to supply current to the display electrodes at a higher speed than conventional ones, enabling high-speed operation, and since there is no offset, the control range is wide and sufficiently detailed in the case of gradation display. It becomes possible to do so.

薄膜トランゾスタのゲート電圧をＩＯＶ、ドレイン電圧
を５ｖとした時のＯＮ電流は第３図のように半導体層２
２の厚さに余り関係なく一定であるが、ＯＦＦ電流はダ
ート電圧Ｏｖ１　ドレイン電圧５ｖで、薄膜トランジス
タの半導体層２２の厚さにより、また外来光によって変
化する。この発明では半導体層２２の厚さを例えば５０
０に即ちｏ、ｏｓミクロン以下にすることができ、従来
は薄くても０．１ミクロンつまり１００ＯＸ位必要とし
た場合と比べてオフ電流を著しく少なくすることができ
る。このため第４図に示すようにデート電圧に対するド
レイン電流の変化は、半導体層２２の厚さが０．０３μ
ｍ、チャネル長が１０ミクロン、チャネル幅が１００ミ
クロンの場合において外部の光が０の場合は実線４１に
示すように著しく小さなドレイン電流であり、１０，０
００ルツクスの外来光がある状態において遮光層２５を
設けない場合においても点線４２のようにドレイン電流
は可成シ小さく、十分なオンオフ比が得られることが判
る。なお外来光が１００，０００ルツクスの場合は遮光
層を設けて点線４３のようなドレイン電流特性となる。When the gate voltage of the thin film transistor is IOV and the drain voltage is 5V, the ON current is as shown in Figure 3.
The OFF current is constant regardless of the thickness of the semiconductor layer 22 of the thin film transistor, but the OFF current varies depending on the thickness of the semiconductor layer 22 of the thin film transistor and external light at the dirt voltage Ov1 and drain voltage 5V. In this invention, the thickness of the semiconductor layer 22 is, for example, 50 mm.
0, that is, less than o, os microns, and the off-state current can be significantly reduced compared to the conventional case, which required a thickness of at least 0.1 microns, that is, about 100 OX. Therefore, as shown in FIG. 4, the change in drain current with respect to date voltage is as follows:
m, the channel length is 10 microns, the channel width is 100 microns, and when the external light is 0, the drain current is extremely small as shown by the solid line 41, and 10,0
It can be seen that even when the light shielding layer 25 is not provided in the presence of external light of 0.00 lux, the drain current is considerably small as indicated by the dotted line 42, and a sufficient on-off ratio can be obtained. Note that when the external light is 100,000 lux, a light shielding layer is provided and the drain current characteristics are as shown by the dotted line 43.

「発明の効果」 以上述べたようにこの発明の薄膜トランジスタによれば
、ドレインパス１９の厚さを十分厚く、例えば１００Ｏ
Ｘ程度以上にすることもでき、従ってドレインパス１９
の抵抗が小さく、広い面積の表示素子としても輝度・が
傾斜することなく、全面でほぼ一様な輝度が得られる。"Effects of the Invention" As described above, according to the thin film transistor of the present invention, the thickness of the drain path 19 is made sufficiently thick, for example, 100 Ω.
It is also possible to make it more than about X, so the drain path 19
The resistance is small, and even when used as a display element with a large area, there is no slope in brightness and almost uniform brightness can be obtained over the entire surface.

しかもドレイン電極及びソース電極の対向面がテーパ面
となってぃるため半導体層２２の厚さを十分薄くするこ
とができ、遮光層を設けなくても十分なオンオフ比が得
られ、かつ広い面積で半導体層と電極１５ａ。Moreover, since the facing surfaces of the drain electrode and the source electrode are tapered surfaces, the thickness of the semiconductor layer 22 can be made sufficiently thin, a sufficient on-off ratio can be obtained without providing a light shielding layer, and a large area can be obtained. The semiconductor layer and the electrode 15a.

１９ａとをオーミック接触させることができ、オフセッ
トがなく、階調表示を細かくかつ幅広く行うことができ
る。更にドレイン電流も大きく、それだけ高速動作が可
能である。19a can be brought into ohmic contact, there is no offset, and gradation can be displayed finely and over a wide range. Furthermore, the drain current is large, and high-speed operation is possible.

また前述したように電極１５ａ、１９ａとしてリン又は
ホウ素を含むものを用いることによって良好なオーミッ
ク接触層２７．２８をそのための工程を行うことなく、
得ることができる。テーパ面３１．３２を形成するが、
このために工程が増加することなく、電極形成のだめの
エツチングを等方性のドライエツチング、又はウェット
エツチングによればよく、特殊な処理をする必要はない
。Furthermore, as described above, by using electrodes containing phosphorus or boron as the electrodes 15a and 19a, good ohmic contact layers 27 and 28 can be formed without performing any process for that purpose.
Obtainable. Although tapered surfaces 31 and 32 are formed,
Therefore, the number of steps is not increased, and the etching for forming the electrodes can be performed by isotropic dry etching or wet etching, and there is no need for special treatment.

ナオｆ−ｄ’ｉ３１　、３２を形成するがチャネル面積
は従来のものと同一にすることができ、つまりチャネル
長を小さくすることができる。However, the channel area can be the same as that of the conventional one, that is, the channel length can be made smaller.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明による薄膜トランジスタの一例を示す
断面図、第２図は薄膜トランジスタのドレイン電圧、ド
レイン電流特性図、第３図は半導体層の厚さに対するド
レイン電流特性図、第４図はケ゛−ト電圧に対するドレ
イン電流特性図、第５図は液晶表示素子の断面の一部を
示す図、第６図は液晶表示素子の表示電極と薄膜トラン
ジスタとケ゛−トハス、ソースパスの関係を示す回路図
、第７図はその一部の平面図、第８図は第７図のＡＡ線
拡大断面図である。 １１：透明基板、１５ａニドレイン電極、１９ａ：ソー
ス電極、２２：半導体層、２３：ケ゛−ト絶縁膜、２４
：ブート電極、２７　、２８　ニオ−ミック接触層、３
１，３２：テーパ面。FIG. 1 is a cross-sectional view showing an example of a thin film transistor according to the present invention, FIG. 2 is a drain voltage and drain current characteristic diagram of the thin film transistor, FIG. 3 is a drain current characteristic diagram with respect to the thickness of the semiconductor layer, and FIG. 4 is a diagram showing drain current characteristics. FIG. 5 is a diagram showing a part of a cross section of a liquid crystal display element; FIG. 6 is a circuit diagram showing the relationship between the display electrode of the liquid crystal display element, a thin film transistor, a gate path, and a source path; FIG. 7 is a plan view of a part thereof, and FIG. 8 is an enlarged sectional view taken along line AA in FIG. 11: Transparent substrate, 15a Ni-drain electrode, 19a: Source electrode, 22: Semiconductor layer, 23: Kate insulating film, 24
: Boot electrode, 27, 28 Niomic contact layer, 3
1, 32: Tapered surface.

Claims (4)

【特許請求の範囲】[Claims] （１）ドレイン電極とソース電極とが互いに分離されて
設けられ、これらドレイン電極及びソース電極間にわた
つて一部重なつて半導体層が形成され、その半導体層上
にゲート絶縁膜が形成され、そのゲート絶縁膜上にゲー
ト電極が形成された薄膜トランジスタにおいて、 上記ドレイン電極及びソース電極の対向側面はそれぞれ
テーパ面とされ、これらテーパ面の全面にわたつてオー
ミック接触層を介して上記半導体層が形成されているこ
とを特徴とする薄膜トランジスタ。(1) A drain electrode and a source electrode are provided to be separated from each other, a semiconductor layer is formed to partially overlap between the drain electrode and the source electrode, and a gate insulating film is formed on the semiconductor layer, In a thin film transistor in which a gate electrode is formed on the gate insulating film, opposing side surfaces of the drain electrode and the source electrode are respectively tapered surfaces, and the semiconductor layer is formed over the entire surface of these tapered surfaces via an ohmic contact layer. A thin film transistor characterized by: （２）上記ドレイン電極及びソース電極の対向側面のテ
ーパ面は上記ゲート電極側に近ずくに従って互の間隔が
大となるテーパ面であることを特徴とする特許請求の範
囲第１項記載の薄膜トランジスタ。(2) The thin film transistor according to claim 1, wherein the tapered surfaces of the opposite side surfaces of the drain electrode and the source electrode are tapered surfaces such that the distance between them increases as the distance from each other increases as the distance approaches the gate electrode side. . （３）上記ドレイン電極及びソース電極はそれぞれ透明
電極であることを特徴とする特許請求の範囲第１項記載
の薄膜トランジスタ。(3) The thin film transistor according to claim 1, wherein the drain electrode and the source electrode are each transparent electrodes. （４）上記透明電極にリン、ひ素、アンチモン、ビスマ
スなどの５族元素又はホウ素、アルミニウム、ガリウム
などの３族元素を含むことを特徴とする特許請求の範囲
第３項記載の薄膜トランジスタ。(4) The thin film transistor according to claim 3, wherein the transparent electrode contains a Group 5 element such as phosphorus, arsenic, antimony, and bismuth, or a Group 3 element such as boron, aluminum, and gallium.
JP60221667A 1985-10-04 1985-10-04 Thin film transistor Pending JPS6281065A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP60221667A JPS6281065A (en) 1985-10-04 1985-10-04 Thin film transistor
EP86113674A EP0217406B1 (en) 1985-10-04 1986-10-03 Thin-film transistor and method of fabricating the same
DE8686113674T DE3685623T2 (en) 1985-10-04 1986-10-03 THIN FILM TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF.
AT86113674T ATE77177T1 (en) 1985-10-04 1986-10-03 THIN FILM TRANSISTOR AND METHOD FOR ITS MANUFACTURE.
KR1019860008313A KR900000066B1 (en) 1985-10-04 1986-10-04 Manufacturing method of film transistor
US07/222,296 US4864376A (en) 1985-10-04 1988-07-22 Thin-film transistor and method of fabricating the same
US07/399,141 US5061648A (en) 1985-10-04 1989-08-28 Method of fabricating a thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60221667A JPS6281065A (en) 1985-10-04 1985-10-04 Thin film transistor

Publications (1)

Publication Number Publication Date
JPS6281065A true JPS6281065A (en) 1987-04-14

Family

ID=16770376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60221667A Pending JPS6281065A (en) 1985-10-04 1985-10-04 Thin film transistor

Country Status (1)

Country Link
JP (1) JPS6281065A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04505832A (en) * 1990-10-05 1992-10-08 ゼネラル・エレクトリック・カンパニイ Thin film transistor structure with improved source/drain contacts

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721867A (en) * 1980-06-02 1982-02-04 Xerox Corp Planar thin film transistor array and method of producing same
JPS5759355A (en) * 1980-09-26 1982-04-09 Fujitsu Ltd Manufacture of semiconductor device
JPS59181064A (en) * 1983-03-31 1984-10-15 Toshiba Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721867A (en) * 1980-06-02 1982-02-04 Xerox Corp Planar thin film transistor array and method of producing same
JPS5759355A (en) * 1980-09-26 1982-04-09 Fujitsu Ltd Manufacture of semiconductor device
JPS59181064A (en) * 1983-03-31 1984-10-15 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04505832A (en) * 1990-10-05 1992-10-08 ゼネラル・エレクトリック・カンパニイ Thin film transistor structure with improved source/drain contacts

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