JP3252014B2 - Manufacturing method of semiconductor integrated circuit - Google Patents
Manufacturing method of semiconductor integrated circuitInfo
- Publication number
- JP3252014B2 JP3252014B2 JP11406793A JP11406793A JP3252014B2 JP 3252014 B2 JP3252014 B2 JP 3252014B2 JP 11406793 A JP11406793 A JP 11406793A JP 11406793 A JP11406793 A JP 11406793A JP 3252014 B2 JP3252014 B2 JP 3252014B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor integrated
- integrated circuit
- manufacturing
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路の製造
方法、特に任意の配線により形成された段差を軽減する
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for reducing a step formed by an arbitrary wiring.
【０００２】[0002]
【従来の技術】近年、半導体集積回路が微細化、高集積
化するのに伴い、回路の配線層は多層構造化し、表面層
の段差はますます増大する傾向にある。この段差によ
り、次配線層の該段差下部にエッチング残りが生じ、半
導体集積回路の特性劣化や歩留まりの低下を引き起こす
という問題があった。この段差を緩和するために、被覆
率の良いＴＥＯＳ−Ｏ3 系ガスを層間絶縁膜の成膜に適
用する方法（月刊日経マイクロデバイス１９９３年２月
号、Ｐ．４９）がある。2. Description of the Related Art In recent years, as semiconductor integrated circuits have become finer and more highly integrated, the wiring layers of the circuits have become multi-layered, and the steps on the surface layer have tended to increase. Due to this step, there is a problem that etching residue occurs below the step in the next wiring layer, which causes deterioration in characteristics of the semiconductor integrated circuit and a decrease in yield. In order to alleviate this step, there is a method of applying a TEOS-O 3 -based gas having a good coverage to the formation of an interlayer insulating film (Monthly Nikkei Micro Devices, February 1993, p. 49).
【０００３】[0003]
【発明が解決しようとする課題】ＴＥＯＳ−Ｏ3 系ガス
による成膜では、成膜圧力を常圧にすると段差の被覆形
状がリフロー形状となるが、反応が常圧下で行われるた
め、成膜次に生成されるパーティクルを排気する気流制
御が難しく、パーティクル付着による歩留まりの低下を
起こす。一方、減圧下の成膜では、パーティクルの発生
は許容レベル以下にできるが、被覆形状がコンフォーマ
ルとなり、実質的な段差の軽減を達成できない。そのた
め、数μｍの隙間を埋め込むためには、該隙間寸法の１
／２の膜厚の絶縁膜を形成する必要があり、厚膜により
生じる絶縁膜のクラックによる回路の信頼性の低下や、
成膜時間の増大によるスループットの低下という問題点
がある。In the case of film formation using a TEOS-O 3 -based gas, when the film formation pressure is set to normal pressure, the shape of the step becomes a reflow shape, but the reaction is performed under normal pressure. It is difficult to control the airflow for exhausting the particles generated next, and the yield is reduced due to the adhesion of the particles. On the other hand, in the case of film formation under reduced pressure, the generation of particles can be reduced to an allowable level or less, but the coating shape becomes conformal and substantial reduction of the level difference cannot be achieved. Therefore, in order to embed a gap of several μm, it is necessary to set the gap dimension to 1 μm.
It is necessary to form an insulating film having a thickness of / 2, and the reliability of the circuit is reduced due to cracks in the insulating film caused by the thick film.
There is a problem that the throughput is reduced due to an increase in the film formation time.
【０００４】このような従来技術の問題点に鑑み、本発
明の主な目的は、信頼性の低下や、成膜時間の増大によ
るスループットの低下を生じることなく、エッチバック
前の段差角度を軽減できる半導体集積回路の製造方法を
提供することにある。[0004] In view of the problems of the prior art described above, a main object of the present invention is to reduce the step angle before etch back without lowering the reliability or lowering the throughput due to an increase in the deposition time. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit that can be manufactured.
【０００５】[0005]
【課題を解決するための手段】このような目的は、本発
明によれば、配線パターン上に該配線膜厚以上の厚さを
持つ絶縁層を材料ガスにＴＥＯＳとＯ 3 との混合ガスを
用いかつ成膜圧力を６０Ｔｏｒｒ以上７６０Ｔｏｒｒ以
下にして成膜し、続いて該絶縁膜の表面をＡｒガス等を
用いて絶縁膜の膜厚の１／４から１／３の厚さ分だけリ
アクティブイオンエッチングでエッチバックすることに
より達成される。Means for Solving the Problems] Such object is achieved according to the present invention, a mixed gas of TEOS and O 3 insulating layer material gas having a wiring thickness or more thickness on the wiring pattern
Use and a film formation pressure of 60 Torr or more and 760 Torr or less
Formed in the bottom, followed by a surface of the insulating film by the thickness of the third 1/4 of the thickness of the insulating film by using the Ar gas or the like Li
Ru is accomplished by etching back in reactive ion etching.
【０００６】[0006]
【作用】このようにすれば、エッチバック前に配線上の
絶縁膜で形成された表面をＡｒガスを用いてエッチバッ
クする際に、スパッタリング確率の高いテーパ部分のエ
ッチングが他の部分より多く進行するため、エッチバッ
ク前の段差角度を軽減できると共に、成膜が高圧下で行
われるため、成膜時に生成されるパーティクルを排気す
る気流制御が行いやすく、パーティクル付着による歩留
まりの低下の心配もない。In this way, when the surface formed of the insulating film on the wiring is etched back using Ar gas before the etch back, etching of the tapered portion having a high probability of sputtering proceeds more than other portions. Therefore, the step angle before etch back can be reduced , and film formation can be performed under high pressure.
Exhaust particles generated during film formation.
Easy to control air flow, yield by particle adhesion
There is no worry about the ball drop .
【０００７】[0007]
【実施例】以下、本発明の好適実施例を添付の図面を用
いて説明する。Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
【０００８】図１に本発明の実施例による製造方法を示
す。図１（ａ）に示されるように、ウェーハ４上に形成
された０．６μｍの膜厚のＡｌ配線パターン上に、０．
３μｍのプラズマ酸化膜２を成膜する。FIG. 1 shows a manufacturing method according to an embodiment of the present invention. As shown in FIG. 1A, a 0.6 μm thick Al wiring pattern formed on the wafer 4 is
A 3 μm plasma oxide film 2 is formed.
【０００９】次に、図１（ｂ）に示されるように、プラ
ズマ酸化膜２上にＴＥＯＳ−Ｏ３膜３を、ＴＥＯＳ／Ｏ
３流量比１／２０で圧力６０Ｔｏｒｒ、温度４００℃の
雰囲気で気相化学成長により０．６μｍの膜厚だけ形成
する。この反応は高圧下で行われるため、成膜時に生成
されるパーティクルを排気する気流制御が行いやすく、
パーティクル付着による歩留まりの低下の心配もない。
成膜圧力は６０Ｔｏｒｒ以上７６０Ｔｏｒｒ以下であれ
ば良い。Next, as shown in FIG. 1B, a TEOS-O 3 film 3 is formed on the plasma oxide film 2 by a TEOS / O
3 A film thickness of 0.6 μm is formed by vapor phase chemical growth in an atmosphere at a pressure of 60 Torr and a temperature of 400 ° C. at a flow rate of 1/20. Since this reaction is performed under high pressure, it is easy to perform airflow control for exhausting particles generated during film formation,
There is no concern about a decrease in yield due to particle adhesion.
The film formation pressure may be 60 Torr or more and 760 Torr or less.
【００１０】次に、図１（ｃ）に示されるように、ＴＥ
ＯＳ−Ｏ3 膜３の表面を０．１５μｍだけ、Ａｒガス１
００％、圧力１Ｔｏｒｒ、高周波パワー密度０．５Ｗ／
cm2のプラズマを用いて、リアクティブイオンエッチン
グ反応５によりエッチバックする。本実施例では、ＴＥ
ＯＳ−Ｏ3 膜３のエッチバック量を、成膜された膜厚の
１／４としたが、１／４から１／３の厚さ分であれば良
い。また、Ａｒガスを１００％としたが、リアクティブ
イオンエッチングプラズマ中に５０％以上のＡｒガスが
含まれていれば良い。Next, as shown in FIG.
The surface of the OS-O 3 film 3 is 0.15 μm thick, and Ar gas 1
00%, pressure 1 Torr, high frequency power density 0.5 W /
Etchback is performed by reactive ion etching reaction 5 using a plasma of cm 2 . In this embodiment, TE
Although the etch back amount of the OS-O 3 film 3 is set to １ ／ of the formed film thickness, it may be １ ／ to １ ／ of the film thickness. Although the Ar gas is set to 100%, it is sufficient that the reactive ion etching plasma contains 50% or more of the Ar gas.
【００１１】リアクティブイオンエッチング反応ではス
パッタリング確率の高いテーパ部分のエッチングが他の
部分より多く進行するため、図１（ｄ）に示すようにＴ
ＥＯＳ−Ｏ3 膜３の角部が落ち、なだらかになる。In the reactive ion etching reaction, since the etching of the tapered portion having a high probability of sputtering proceeds more than the other portions, as shown in FIG.
The corners of the EOS-O 3 film 3 fall and become smooth.
【００１２】[0012]
【発明の効果】このように本発明によれば、エッチバッ
ク前に配線上の絶縁膜で形成された表面をＡｒガスを用
いてエッチバックする際に、スパッタリング確率の高い
テーパ部分のエッチングが他の部分より多く進行するた
め、厚膜により生じる絶縁膜のクラックによる回路の信
頼性の低下や、成膜時間の増大によるスループットが低
下することなく、エッチバック前の段差角度を軽減でき
ると共に、成膜が高圧下で行われるため、成膜時に生成
されるパーティクルを排気する気流制御が行いやすく、
パーティクル付着による歩留まりの低下の心配もない。As described above, according to the present invention, when the surface formed of the insulating film on the wiring is etched back using Ar gas before the etch back, the etching of the tapered portion having a high probability of sputtering is different. for traveling more than part, the reliability decrease in the circuit due to cracking of the insulating film caused by a thick film, without throughput decreases due to increased deposition time, it is possible to reduce a level difference angle before etchback, formed Generated during film formation because the film is performed under high pressure
Easy to control the air flow to exhaust the particles
There is no concern about a decrease in yield due to particle adhesion .
【図１】（ａ）〜（ｄ）は、Ａｌ配線パターン上に成膜
したプラズマ酸化膜の平坦化に本発明を適用した場合の
各工程に於けるウェーハ断面図を示す。FIGS. 1A to 1D are cross-sectional views of wafers in respective steps when the present invention is applied to flatten a plasma oxide film formed on an Al wiring pattern.
１ Ａｌ配線パターン ２ プラズマ酸化膜 ３ ＴＥＯＳ−Ｏ3 膜 ４ ウェーハ ５ リアクティブイオンエッチング反応Reference Signs List 1 Al wiring pattern 2 Plasma oxide film 3 TEOS-O 3 film 4 Wafer 5 Reactive ion etching reaction
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/3065 H01L 21/316 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/3065 H01L 21/316
Claims (2)
て、 ウェーハ上に形成された配線パターン上に絶縁膜を成膜
する過程と、前記絶縁膜の表面を前記絶縁膜の膜厚の１
／４から１／３の厚さ分だけエッチバックする過程とを
有し、 前記絶縁膜を成膜する際に材料ガスにＴＥＯＳとＯ 3 と
の混合ガスを用いかつ成膜圧力を６０Ｔｏｒｒ以上７６
０Ｔｏｒｒ以下にすると共に、前記エッチバックをリア
クティブイオンエッチングで行う ことを特徴とする半導
体集積回路の製造方法。1. A method of manufacturing a semiconductor integrated circuit, comprising: forming an insulating film on a wiring pattern formed on a wafer;
/ 4 1/3 by the thickness of possess a step of etching back, TEOS and O 3 into the material gas in forming the insulating film
And a film forming pressure of 60 Torr or more and 76
0 Torr or less and the etch back
A method for manufacturing a semiconductor integrated circuit, wherein the method is performed by active ion etching .
プラズマ中のガスがＡｒ１００％であることを特徴とす
る請求項１に記載の半導体集積回路の製造方法。2. The method according to claim 1, wherein the gas in the plasma of the reactive ion etching is 100% Ar .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11406793A JP3252014B2 (en) | 1993-04-16 | 1993-04-16 | Manufacturing method of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11406793A JP3252014B2 (en) | 1993-04-16 | 1993-04-16 | Manufacturing method of semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06302563A JPH06302563A (en) | 1994-10-28 |
| JP3252014B2 true JP3252014B2 (en) | 2002-01-28 |
Family
ID=14628208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11406793A Expired - Lifetime JP3252014B2 (en) | 1993-04-16 | 1993-04-16 | Manufacturing method of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3252014B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100461466B1 (en) * | 2001-11-13 | 2004-12-13 | 엘지.필립스 엘시디 주식회사 | Insulating layer for Metal Line and A Flat display device having the same |
| US20230057446A1 (en) * | 2020-01-08 | 2023-02-23 | Sony Group Corporation | Light emitting element |
-
1993
- 1993-04-16 JP JP11406793A patent/JP3252014B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06302563A (en) | 1994-10-28 |
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