JP3270196B2 - Thin film formation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a chemical vapor deposition (CV) method.
The present invention relates to a method for forming a wiring structure using D method), and particularly to a wiring used for a semiconductor device.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been changed from LSI to VLS.
I and further to the ULSI, the degree of integration has been improved, and accordingly, the miniaturization of the width of wiring and the diameter of connection holes such as via holes has been remarkably advanced. With the increase in the density and the degree of integration of such semiconductor devices, multilayer wiring technology and technology relating to miniaturization of metal wiring are required.

[0003] Such techniques of miniaturization cannot be handled by conventional techniques using the sputtering method.
What has been proposed is a CVD method using an organic metal material such as an Al organic compound. This CVD method is particularly effective as a technique for sufficiently filling the fine holes. The outline of the step of forming a via plug in the via hole by using the CVD method is as follows.

First, a lower metal wiring made of an Al alloy or the like is formed on a base insulating film formed on a Si substrate. Next, after forming an interlayer insulating film on the base insulating film, a via hole is formed in the interlayer insulating film. Next, a metal such as Al is deposited and buried only in the via hole by the CVD method to form a via plug.

Here, prior to depositing a metal such as Al in the via hole, the lower metal wiring exposed on the bottom surface of the via hole is cleaned by plasma etching using a chlorine-based gas. This is because the lower metal wiring exposed at the bottom of the via hole is formed with a metal natural oxide film or the like, so if the via plug is formed without removing the natural oxide film, the lower metal wiring and the via plug This is because adverse effects such as an increase in the contact resistance at the interface of the substrate occur.

[0006]

However, when the cleaning treatment is performed by plasma etching using a chlorine-based gas, chlorine remains on the substrate surface or a compound such as Al chloride is generated, and this is a problem. In some cases, impurities may adhere to the surface, or some of the atoms may be replaced with chlorine atoms on the surface of the insulating film, and impurities such as chlorine and chlorine compounds may be mixed. If such residual chlorine or the compound is large, good selectivity cannot be obtained in the subsequent metal deposition by the CVD method, and the metal cannot be sufficiently buried in the via hole. In addition, these compounds cause an increase in wiring resistance due to an increase in contact resistance between the lower metal wiring and the via plug, and further cause corrosion of Al metal wiring and the like due to residual chlorine, thereby deteriorating the reliability of the metal wiring. Will be.

Accordingly, an object of the present invention is to provide a semiconductor device having a multilayer wiring structure which solves such a problem.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a cleaning method in which a desired area on a substrate on which metal is to be deposited is cleaned by plasma etching using a chlorine-based gas. In a thin film forming method including a chemical treatment step and a metal film deposition step of supplying a source gas and depositing a metal in a desired region by a chemical vapor deposition method to form a metal film, The method further comprises a heat treatment step of heating the substrate.

To solve the above problems, the present invention provides
A cleaning process of cleaning a desired region on which metal on the substrate is to be deposited by plasma etching using a chlorine-based gas; supplying a source gas; and depositing a metal on the desired region by a chemical vapor deposition method. A metal film deposition step of depositing a substrate to form a metal film, further comprising a plasma treatment step of exposing the substrate to plasma discharge in an inert gas atmosphere or a hydrogen gas atmosphere before the cleaning treatment step. It is characterized by having.

[0010]

[0011]

[0012]

According to the first aspect of the present invention, the heat treatment is performed before the substrate is cleaned by plasma etching using a chlorine-based gas, so that moisture and impurities attached to the substrate surface are removed. Can be. Therefore, impurities such as chlorides hardly occur during plasma etching.

According to the above method, the substrate is exposed to plasma discharge in an inert gas or hydrogen gas atmosphere before the substrate is cleaned by plasma etching using a chlorine-based gas. Adhered moisture and impurities can be removed. Therefore, impurities such as chlorides hardly occur during plasma etching.

[0014]

[0015]

[0016]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

A method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 1A, a base insulating film 20 is formed on the surface of a Si substrate 10, and an Al alloy is deposited on the base insulating film 20 by sputtering to a thickness of 300 to 800 nm. An alloy film 31 is formed. Next, the Al alloy film 3
1 is processed into a predetermined wiring pattern to form a lower metal wiring 30. After forming a resist pattern using an exposure apparatus, the wiring pattern is formed by RIE (reactive ion etching) which is plasma etching using a chlorine-based gas. Next, as shown in FIG. 1B, a 1 μm-thick interlayer insulating film 40 is formed on the underlying insulating film 20 on which the lower metal wiring 30 is formed. This interlayer insulating film 40 is made of SiO ₂ by a plasma CVD method.
Is deposited to form a SiO ₂ film, and SOG (Spin
on Glass) to form an SOG film, and heat treatment is performed at a required temperature. Thereafter, SiO ₂ is deposited again by the plasma CVD method to form an SiO ₂ film.

Next, a photomask is set on the interlayer insulating film 40, and a resist pattern is formed using an exposure apparatus, and then, FIG. 1 is obtained by RIE using a fluorine-based gas.
As shown in (c), a via hole 50 is formed in the interlayer insulating film 40. Next, after removing the resist, the Si substrate 10 in which the via holes 50 are formed is heated by applying heat at 400 ° C. for 60 minutes in a vacuum. This heat treatment removes moisture and impurities. This heat treatment may be performed in any of the RIE room, the CVD room, and the transfer room. By removing moisture and impurities in this way, it is possible to suppress the generation of chlorides and the like generated during RIE, and to perform RIE performed thereafter.
Can be stabilized. Although the heat treatment is performed in a vacuum in this embodiment, the heat treatment may be performed in a hydrogen gas atmosphere, a nitrogen gas atmosphere, or an inert gas atmosphere such as an argon gas instead of the vacuum. Also,
At this time, the same effect can be obtained by exposing to plasma discharge performed in an inert gas atmosphere such as Ar or a hydrogen gas atmosphere instead of the heat treatment.

Next, the Si substrate 10 is transferred to the RIE chamber by vacuum so as not to be exposed to the atmosphere. In the RIE chamber, the lower metal wiring 30 (Al alloy film) exposed at the bottom of the via hole 50 is cleaned by RIE using a chlorine-based gas.
At this time, a mixed gas of BCl ₃ and Ar is used as the chlorine-based gas. The conditions for performing RIE are BC
partial pressure ratio of between l ₃ and Ar is a ratio of 1: 1, pressure is the total pressure 100 mTorr, plasma power is 0.05 W / cm
^The time required for the etching is about ³ minutes. Here, it is desirable that the partial pressure of BCl ₃ is not less than 70 mTorr and the partial pressure of Ar is not more than 100 mTorr. Performing RIE under such conditions is important to enable selective deposition by a CVD method performed later. The cleaning process is performed when the fluorine-based RIE performed when the via hole is formed is performed on the surface of the lower metal wiring 30 exposed at the bottom of the via hole 50 and when the RI is formed.
When exposed to the atmosphere after E, deposits and alumina films adhere, and these deposits and alumina films adhere to A in the CVD method.
This is because it is necessary to remove l to inhibit the deposition.

Next, the Si substrate treated as described above was carried in a vacuum and was carried into a CVD chamber. In addition, it is desirable that the vacuum state when transporting the Si substrate is an air pressure of 5 × 10 ⁻⁷ Torr or less. Then, in this CVD chamber, DMAH (AlH (CH ₃ ) ₂ : Dimethyl
By selectively depositing Al from the bottom only in the via hole 50 by a thermal CVD method using l-aluminum-hydride (gas) and hydrogen as raw materials, FIG.
As shown in (d), the via plug 5 is inserted into the via hole 50.
Form one. The conditions for performing the CVD at this time are a hydrogen gas flow rate of 500 sccm and a partial pressure of DMAH of 0.15 To.
rr, bubbling at 50 ° C. Note that the total pressure in the CVD reactor for performing the film formation is 2.0 Torr and the substrate temperature is 210 ° C.

In this manner, all the via holes 50 have A
An Al thin film was deposited until 1 was completely filled. When the surface of the insulating film was inspected thereafter, no Al deposition was observed.

Next, 400 to 1000 n of Al is sputtered on the upper surface of the via plug 51 and the interlayer insulating film 40.
1E, an Al alloy film is formed, and the upper metal wiring 60 is formed as shown in FIG. 1E using the same method as that for forming the lower metal wiring 30 described above. ,
A semiconductor device having a multilayer wiring structure is manufactured.

Until the semiconductor device using the via structure of the present invention is completed, a surface protective film is formed after the via plug 51 is formed, and a heat treatment for removing process damage is performed.

Further, structures necessary for a semiconductor device such as a diffusion layer and a gate electrode are formed inside and on the surface of the Si substrate 10. A contact hole exists at a required position of the base insulating film 20, and a contact structure for connecting the lower metal wiring 30 to a diffusion layer, a gate electrode, or another structure is formed. An antireflection film using W or the like or a barrier metal using TiN or the like is formed between the metal wiring and the like and the insulating film as necessary. Further, one or more new interlayer insulating films 40 and metal wirings can be further laminated on the upper metal wiring 60. Next, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described. First, a base insulating film is formed on the surface of a Si substrate, and an Al alloy is deposited on the base insulating film to a thickness of 300 to 800 nm by a sputtering method to form an Al alloy film. Next, the Al alloy film is processed into a predetermined wiring pattern to form a lower metal wiring. After forming a resist pattern using an exposure apparatus, the wiring pattern is formed by RIE using a chlorine-based gas. Next, a 1 μm thick film is formed on the underlying insulating film on which the lower metal wiring is formed.
Then, an m-th interlayer insulating film is formed. This interlayer insulating film is formed in the same manner as in the first embodiment. Next, a photomask is set on the interlayer insulating film, a resist pattern is formed using an exposure apparatus, and then RI using a fluorine-based gas is performed.
E forms a via hole in the interlayer insulating film. next,
After removing the resist, the Si substrate is vacuum-transferred to the RIE chamber so as not to be exposed to the atmosphere. In the RIE chamber, the lower metal wiring (Al alloy film) exposed at the bottom of the via hole is cleaned by RIE using a chlorine-based gas. At this time, a mixed gas of BCl ₃ and Ar is used as the chlorine-based gas.
The conditions for performing RIE are the same as in the first embodiment. The reason for performing the cleaning process is the same as in the first embodiment.

Next, a hydrogen gas atmosphere (5 × 10 ⁻⁵ Torr)
Heat at 400 ° C. for 30 minutes in r). By this heat treatment, impurities such as chloride generated during RIE are removed by sublimation. This heat treatment is performed in RIE room, CVD
It may be performed in any of the chamber or the transfer chamber. However, since impurities are sublimated by the heat treatment, it is preferable to provide a heat treatment chamber separately from these rooms. By providing the heat treatment chamber in this manner, each room is not contaminated by contaminants such as sublimed residual chlorine. At this time, the temperature at which the heat treatment is performed is desirably 300 ° C. or higher. At this time, the same effect can be obtained by exposing to plasma discharge performed in an atmosphere of an inert gas such as Ar or a hydrogen gas instead of the heat treatment.

Next, the Si substrate treated as described above was transported in a vacuum and carried into a CVD chamber. In addition, it is desirable that the vacuum state when transporting the Si substrate is an air pressure of 5 × 10 ⁻⁷ Torr or less. Then, in this CVD chamber, a thermal CVD using DMAH gas, which is an Al raw material, and hydrogen as raw materials.
A via plug is formed in the via hole by selectively depositing Al from the bottom only in the via hole by the method. The conditions for performing the CVD at this time are the same as those in the first embodiment.

Thus, an Al thin film was deposited until Al was completely filled in all the via holes. When the surface of the insulating film was inspected thereafter, no Al deposition was observed.

Next, Al is deposited to a thickness of 400 to 1000 nm by sputtering on the upper surface of the via plug and on the interlayer insulating film to form an Al alloy film, and a method similar to that for forming the lower metal wiring described above is used. A semiconductor device having a multi-layered wiring structure is manufactured by forming an upper metal wiring using the same.

It is to be noted that the structure necessary for the semiconductor device is formed inside and on the surface of the Si substrate in the same manner as in the first embodiment.

Next, a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described. First, a base insulating film is formed on the surface of a Si substrate, and an Al alloy is deposited on the base insulating film to a thickness of 300 to 800 nm by a sputtering method to form an Al alloy film. Next, the Al alloy film is processed into a predetermined wiring pattern to form a lower metal wiring. After forming a resist pattern using an exposure apparatus, the wiring pattern is formed by RIE using a chlorine-based gas. Next, an interlayer insulating film having a thickness of 1 μm is formed on the underlying insulating film on which the lower metal wiring is formed. This interlayer insulating film is formed in the same manner as in the first embodiment. Next, a photomask is set on the interlayer insulating film, a resist pattern is formed using an exposure apparatus, and via holes are formed in the interlayer insulating film by RIE using a fluorine-based gas. Next, after removing the resist, the Si with the via hole formed is formed.
The substrate is heated by applying 400 ° C. heat in a vacuum for 60 minutes. This heat treatment removes moisture and impurities.
By removing moisture and impurities in this manner, generation of impurities such as chlorides generated during RIE can be suppressed, and RIE performed thereafter can be performed stably. Although the heat treatment is performed in a vacuum in this embodiment, the heat treatment may be performed in a hydrogen gas atmosphere, a nitrogen gas atmosphere, or an inert gas atmosphere such as an argon gas instead of the vacuum. At this time, the same effect can be obtained by exposing to plasma discharge performed in an atmosphere of an inert gas such as Ar or a hydrogen gas instead of the heat treatment.

Next, this Si substrate is vacuum-transferred to the RIE chamber so as not to be exposed to the atmosphere. In the RIE chamber, the lower metal wiring (Al alloy film) exposed at the bottom of the via hole is cleaned by RIE using a chlorine-based gas. At this time, a mixed gas of BCl ₃ and Ar is used as the chlorine-based gas. The conditions for performing RIE are the same as in the first embodiment. Regarding the reason for performing this cleaning process,
This is the same as the first embodiment.

Next, without exposure to the air, heat is applied by applying heat at 400 ° C. for 60 minutes in a hydrogen gas atmosphere (5 × 10 ⁻⁵ Torr). By this heat treatment, impurities such as chloride generated during RIE are removed by sublimation. At this time, the temperature for performing the heat treatment is desirably 300 ° C. or higher. At this time, the same effect can be obtained by exposing to plasma discharge performed in an atmosphere of an inert gas such as Ar or a hydrogen gas instead of the heat treatment.

Next, the Si substrate treated as described above was carried in a vacuum and was carried into a CVD chamber. In addition, it is desirable that the vacuum state when transporting the Si substrate is an air pressure of 5 × 10 ⁻⁷ Torr or less. Then, in this CVD chamber, a thermal CVD using DMAH gas, which is an Al raw material, and hydrogen as raw materials.
A via plug is formed in the via hole by selectively depositing Al from the bottom only in the via hole by the method. The conditions for performing the CVD at this time are the same as those in the first embodiment.

In this way, an Al thin film was deposited until all via holes were completely filled with Al. When the surface of the insulating film was inspected thereafter, no Al deposition was observed.

Next, Al is deposited to a thickness of 400 to 1000 nm by sputtering on the upper surface of the via plug and the interlayer insulating film to form an Al alloy film, and a method similar to that for forming the lower metal wiring described above is used. Then, an upper metal wiring is formed to manufacture a semiconductor device having a multilayer wiring structure.

It is to be noted that a structure required as a semiconductor device is formed inside and on the surface of the Si substrate in the same manner as in the first embodiment.

Next, a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described. First, a base insulating film is formed on the surface of a Si substrate, and an Al alloy is deposited on the base insulating film to a thickness of 300 to 800 nm by a sputtering method to form an Al alloy film. Next, the Al alloy film is processed into a predetermined wiring pattern to form a lower metal wiring. After forming a resist pattern using an exposure apparatus, the wiring pattern is formed by RIE using a chlorine-based gas. Next, an interlayer insulating film having a thickness of 1 μm is formed on the underlying insulating film on which the lower metal wiring is formed. This interlayer insulating film is formed in the same manner as in the first embodiment. Next, a photomask is set on the interlayer insulating film, a resist pattern is formed using an exposure apparatus, and via holes are formed in the interlayer insulating film by RIE using a fluorine-based gas. Next, after removing the resist, the Si with the via hole formed is formed.
The substrate is exposed to a plasma discharge in an argon gas atmosphere.
This plasma treatment may be performed in another inert gas or hydrogen gas atmosphere instead of the argon gas.

Next, the plasma-etched Si substrate is heated by applying heat at 400 ° C. for 60 minutes in a vacuum.
Although the heat treatment is performed in a vacuum in this embodiment, the heat treatment may be performed in a hydrogen gas atmosphere or an inert gas atmosphere such as a nitrogen gas instead of the vacuum. Water and impurities are removed by this plasma treatment and heat treatment. By removing moisture and impurities in this way, RIE
The generation of impurities such as chlorides generated when the RIE is performed can be suppressed, and the RIE performed thereafter can be performed stably.

Next, this Si substrate is vacuum-transferred to the RIE chamber so as not to be exposed to the atmosphere. In the RIE chamber, the lower metal wiring (Al alloy film) exposed at the bottom of the via hole is cleaned by RIE using a chlorine-based gas. At this time, a mixed gas of BCl ₃ and Ar is used as the chlorine-based gas. The conditions for performing RIE are the same as in the first embodiment. Regarding the reason for performing this cleaning process,
This is the same as the first embodiment.

Next, the wafer is exposed to plasma discharge in a hydrogen gas atmosphere without being exposed to the air. In this plasma treatment, an inert gas such as argon may be used instead of the hydrogen gas.

Next, a hydrogen gas atmosphere (5 × 10 ⁻⁵ Torr)
Heat at 400 ° C. for 60 minutes in r). At this time, the temperature for performing the heat treatment is desirably 300 ° C. or higher. Note that when plasma treatment is performed using hydrogen gas, heating at 400 ° C. may be performed at the same time.

By the plasma treatment and the heat treatment, impurities such as chlorides generated by chlorine-based RIE when the via holes are formed are sublimated and removed.

Next, the Si substrate treated as described above was carried in a vacuum and was carried into a CVD chamber. In addition, it is desirable that the vacuum state when transporting the Si substrate is an air pressure of 5 × 10 ⁻⁷ Torr or less. Then, in this CVD chamber, a thermal CVD using DMAH gas, which is an Al raw material, and hydrogen as raw materials.
A via plug is formed in the via hole by selectively depositing Al from the bottom only in the via hole by the method. The conditions for performing the CVD at this time are the same as those in the first embodiment.

In this way, an Al thin film was deposited until all via holes were completely filled with Al. When the surface of the insulating film was inspected thereafter, no Al deposition was observed.

Next, Al is deposited to a thickness of 400 to 1000 nm by sputtering on the upper surface of the via plug and on the interlayer insulating film to form an Al alloy film, and a method similar to that for forming the lower metal wiring described above is used. Then, an upper metal wiring is formed to manufacture a semiconductor device having a multilayer wiring structure.

It should be noted that the structure necessary for the semiconductor device is formed inside and on the surface of the Si substrate in the same manner as in the first embodiment.

As described above, the first to fourth embodiments of the present invention are described.
In each of the semiconductor devices obtained by the methods up to the embodiment, the via resistance of the 0.5 μm diameter via hole has a very low value of 0.3Ω or less, which indicates that the reliability is very low. It can be seen that a high wiring was formed.

Further, in addition to the Al wiring structure shown in the present embodiment, for example, a laminated wiring or an anti-reflection film
It goes without saying that the present invention can also be effectively applied to the case where it is formed on a wiring.

[0049]

As described above in detail, according to the present invention, before the substrate is cleaned by plasma etching using a chlorine-based gas, heat treatment or plasma treatment is performed, so that the substrate surface Adhered moisture and impurities can be removed. Therefore, impurities such as chlorides hardly occur at the time of plasma etching, so that plasma etching for cleaning can be stably performed.

[0050]

Therefore, since there is almost no residual chlorine or impurities, good selectivity can be obtained in the metal deposition by the CVD method performed later, and the metal can be sufficiently buried in the via hole.

Further, since there is almost no residual chlorine, the wiring resistance does not increase, and the residual chlorine does not cause corrosion of the wiring, so that the reliability of the metal wiring is improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing each manufacturing process of a semiconductor device according to a first embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Si board | substrate, 20 ... Under insulation film, 30 ... Lower metal wiring, 40 ... Interlayer insulation film, 50 ... Via hole, 51 ... Via plug, 60 ... Upper metal wiring

──────────────────────────────────────────────────続 き Continuing on the front page (72) Eiichi Kondo, Inventor 1 Kawasaki-cho, Chuo-ku, Chiba-shi, Chiba Kawasaki Steel Engineering Co., Ltd. (72) Inventor Yoshihiro Ota 1 Kawasaki-cho, Chuo-ku, Chiba, Chiba No. Kawasaki Steel Corp. (56) References JP-A-4-286115 (JP, A) JP-A-2-63118 (JP, A) JP-A-5-62957 (JP, A) 6-29264 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3065 H01L 21/285 H01L 21/304 645

Claims (4)

(57) [Claims] A cleaning process for cleaning a desired region on a substrate on which a metal is to be deposited by plasma etching using a chlorine-based gas;
A metal film depositing step of depositing a metal in the desired area by a chemical vapor deposition method to form a metal film, wherein a metal film is deposited in the cleaning step before the cleaning step.
A method of forming a thin film, further comprising a heat treatment step of heating the substrate to suppress generation of chlorides . 2. A cleaning process for cleaning a desired region on a substrate on which a metal is to be deposited by plasma etching using a chlorine-based gas;
A metal film depositing step of depositing a metal in the desired region by a chemical vapor deposition method to form a metal film, wherein the substrate is placed in an inert gas atmosphere or A method for forming a thin film, further comprising a plasma treatment step of exposing to a plasma discharge in a hydrogen gas atmosphere. 3. The thin film forming method according to claim 1, wherein, after the heat treatment step or the plasma treatment step, the cleaning treatment step is performed without exposing the substrate to the atmosphere. Wherein said desired region, claims, characterized in that the surface of the lower metal wiring exposed at the via hole bottom
3. The method for forming a thin film according to 1 or 2 .