JPH05129179A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve an aligning function and its accuracy by removing part of a semiconductor substrate around a protrusion with an aligning protrusion made of an insulating film on the substrate as a mask. CONSTITUTION:An SiO2 field oxide film 3, an SiO2 first interlayer insulating film 5, and a first Al interconnection layer 7 are formed on a silicon substrate. Then, an SiO2 second insulating film 10 is formed, a tapered part 6 is formed at a predetermined position, and then a second Al contact hole 8 is opened. In this case, a second Al alignment mark is simultaneously formed on a scribing area. Then, a resist mask 11 where holes are opened only in the scribing area is formed, and with the mask 11 and the alignment mark as masks the substrate 1 is removed by etching. The roughness of the alignment mark is further increased in this step. Thus, the alignment mark having high aligning accuracy can be formed on the scribing area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a highly accurate alignment mark forming step.

[0002]

2. Description of the Related Art Conventionally, in the case of manufacturing a MOS transistor, for example, after forming a contact hole in an interlayer insulating film to form an aluminum (Al) wiring, a sputtering method such as bias (Bias) sputtering (sputter) or high temperature sputtering is used. Then, an Al film having a good covering property was deposited on the entire surface to fill the contact hole.

FIG. 3 and FIG. 4 are explanatory views of a conventional technique. In each drawing, a contact hole (not shown) is formed in an interlayer insulating film 5a made of, for example, SiO ₂ formed on a silicon (Si) substrate 1. ) And a convex alignment mark 9 (nine places in FIG. 3) are formed, an Al layer with good coverage is formed by bias sputtering, and then a resist is formed to remove Al in the alignment mark portion that becomes the scribe area. The top view which formed the mask 11 and the AA sectional drawing of the top view are shown. Conventionally, from the state shown in FIGS. 3 and 4, Al in the alignment mark portion was removed using the resist mask 11 as a mask to perform the original patterning of Al.

[0004]

However, in this method, since the alignment of the resist mask 11 in the alignment mark portion depends only on the alignment flat alignment precision, the alignment mark is usually placed with only about 20 to 30 .mu.m alignment precision. 2 scribe areas
It was necessary to make the width 0 to 30 μm wider. Therefore, in the conventional alignment mark forming method, the effective shot area in the wafer (Si substrate) is reduced as much as the scribe area is widened.

The present invention provides a method of manufacturing a semiconductor device having a step of forming an alignment mark (positioning mark) with good precision when forming an Al wiring or the like by bias sputtering or the like with good coverage. To aim.

[0006]

According to the present invention, the above-mentioned problem is obtained by forming at least one alignment protrusion formed of an insulating layer on a semiconductor substrate and then using the alignment protrusion as a mask. A method for manufacturing a semiconductor device is characterized by including a step of removing a part of the semiconductor substrate around the portion.

[0007]

According to the present invention, the alignment projection 9 (alignment mark) 9 made of, for example, SiO ₂ formed on the semiconductor substrate 1 such as silicon (Si) is used as a mask to remove the surrounding substrate 1. Since the height of the alignment projection 9 from the surrounding substrate surface is increased, the alignment function and its accuracy can be improved. Further, the present invention has two steps, that is, a step of forming a rough resist mask pattern, and a step of etching away the substrate as a mask and a positioning projection made of the same material as the resist mask and an insulating layer for forming a contact hole. Since it is only added, it is highly compatible with conventional processes.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a process sectional view for explaining a method of forming an alignment mark according to the present invention, and FIG. 2 is a process sectional view inside an IC (integrated circuit) body corresponding to the process of FIG. is there.

First, as shown in FIGS. 1 (a) and 2 (a), according to a normal MOS transistor manufacturing process,
SiO _{2 is formed} on a silicon (Si) substrate 1 which is a semiconductor substrate.
Field oxide film 3, SiO ₂ first interlayer insulating film 5, first
The Al wiring layer 7 is formed. In FIG. 2A, silicon (S
i) Source / drain regions 2 are formed in the substrate 1. In addition, 4 is a polysilicon (poly-Si) gate.

Next, as shown in FIGS. 1B and 2B, a SiO ₂ second interlayer insulating film 10 having a thickness of 500 to 600 nm is formed, and a taper portion 6 is formed at a predetermined position. After forming, a contact hole 8 for the second Al is opened. At the same time, the second Al is placed in the scribe area.
An alignment mark 9 for use is formed. The width of the alignment marks 9 and the distance between the alignment marks 9 are set to about 2
˜3 μm.

The formation of the tapered portion 6 is 40 Ke.
V, 1 × 10 ¹⁴ ions were implanted and plasma etching using CHF ₃ was used.

Next, as shown in FIGS. 1 (c) and 2 (c), a resist mask 11 having holes only in the scribe area.
Then, the silicon substrate 1 is removed by etching to a depth of about 500 nm using the resist mask 11 and the alignment mark 9 made of SiO ₂ as a mask. By this step, the unevenness of the alignment mark 9 becomes even larger.
In this etching process, the alignment accuracy of the resist mask 11 formed outside the scribe area is 2A or less.
Since the alignment mark 9 formed at the time of forming the contact hole 8 for 1 can be used, it is fine (± 0.2 μm).
m) can be performed. However, 2-
Even if misalignment of about 3 μm occurs, it does not affect the IC body. This is because not only the resist mask 11 but also an unnecessary portion of the SiO ₂ film (alignment mark) 9 to be cut later is used as a mask.

Next, as shown in FIGS. 1 (d) and 2 (d), after removing the resist mask 11, the second Al is 500 nm thick over the entire surface by bias sputtering or high temperature sputtering with good coverage. Second Al layer 1 deposited and deposited to ~ 1 μm
Form 2. Since the alignment mark cannot be completely filled even by this Al deposition and deposition, a highly accurate alignment 9a having a clear concavo-convex pattern formed on the surface of the second Al layer 12 is formed. After that, the wiring pattern mask (not shown) is aligned based on the alignment 9a, and the second Al layer 1
2 is patterned to form a second Al wiring layer, and then a normal process of overcoating is performed.
To complete the MOS transistor.

[0015]

As described above, according to the present invention, it is possible to form an alignment mark with high alignment accuracy in the scribe area, so that it is not necessary to make the scribe area large, and the maximum effective shot area can be utilized. You can

[Brief description of drawings]

FIG. 1 is a process sectional view for explaining a method of forming an alignment mark according to the present invention.

FIG. 2 is a process sectional view of the inside of an IC (integrated circuit) body corresponding to the process of FIG.

FIG. 3 is a plan view for explaining a conventional technique.

4 is a cross-sectional view taken along the line AA of FIG.

[Explanation of symbols]

1 Silicon (Si) Substrate (Semiconductor Substrate) 2 Source / Drain Region 3 Field Oxide Film 4 Polysilicon (Poly-Si) Gate 5 First Interlayer Insulating Film (SiO ₂ ) 6 Taper Part 7 First Al Wiring Layer 8 Contact hole 9 Alignment mask 9a Alignment 10 Second interlayer insulating film 11 Resist mask 12 Second Al layer

Claims (1)

[Claims] 1. A step of forming at least one alignment projection formed of an insulating layer on a semiconductor substrate, and then removing a part of the semiconductor substrate around the projection using the alignment projection as a mask. A method of manufacturing a semiconductor device, comprising: