JPH0346346A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize a fine size and a high integration of a semiconductor integrated circuit by a method wherein individual elements of the integrated circuit are isolated by using a U-shaped groove whose groove width is 0.5mum or lower and an insulator is filled into the U-shaped groove. CONSTITUTION:Individual elements are isolated by a U-shaped groove (submicron U-shaped groove) 8 whose groove width is 0.5mum or lower; an insulator is filled into the U-shaped groove. Thereby, the groove width of the U-shaped groove is sufficiently narrow and the insulator can easily be filled; as a result, an isolation structure whose permittivity is low can be formed, and a fine size and a high integration can be realized. In addition, the insulator inside the U-shaped groove can be used as a CVD insulating film; a hollow which is produced on the U-shaped groove in this case is so small as to be negligible and a flattened structure can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device with an improved element isolation structure using U-groove isolation.

[Conventional technology] As one of the element isolation structures of semiconductor integrated circuits.

U-groove isolation, in which a U-groove with a minute width is dug between each element and polysilicon is filled in the U-groove, is an example of the U-groove isolation, published on March 29, 1982, by F Nikkei Electronics, pages 94 to 94. (page 95).

In the above-mentioned conventional technology, as shown in FIG. 11, a U-groove 41a is formed in a semiconductor substrate 4, the inner wall surface of this U-groove 41a is oxidized in advance, and then polysilicon 4 is formed on the semiconductor substrate 41.
2 is deposited, polysilicon 42 is buried in the U-groove, and the polysilicon on the semiconductor substrate 4 is removed by etch-back, leaving polysilicon 42 only in the U-groove 1a. After this process, LOCO5
Element isolation is performed by

[Problems to be Solved by the Invention] However, if the method of filling the U-groove with polysilicon as described above is adopted, the dielectric constant in the UFIlt becomes a large value (~11) due to the filled polysilicon, and the element Parasitic capacitance and wiring capacitance increase, which impedes high-speed operation of the LSI.

In order to prevent such an increase in dielectric constant, it is conceivable to fill the U-groove with a CVD insulating film having a low dielectric constant (3 to 4) instead of polysilicon.

By the way, the bonding (adhesion) between CVD insulating films is weaker than that of polysilicon, and if the CVD@edge film is once deposited and then etched back, as in the case of polysilicon, the interface will be removed from the surface. Etching easily progresses along the interface, resulting in a process failure.

On the other hand, in order to prevent the interface of the CVD insulating film from being exposed on the surface side, it is possible to leave the CVDII film deposited on the semiconductor substrate as it is without etching it back.
In that case, the thickness <CV
D insulation film must be deposited. This is because a dent is created on the center line of the groove, so if this dent is removed, the CV
This is because it is necessary to planarize the D insulating film as well.

However, if such a thick cVD film is deposited, there is a problem in that the time required for the deposition becomes long. Furthermore, if the CVDf, fl edge films are left thick on the semiconductor substrate, there is a risk of poor contact between the wiring layer on the CVD insulating film and the diffusion layer formed within the semiconductor substrate.

In order to eliminate this problem, the groove width of the U-groove can be narrowed to make the dent so small that it can be ignored, but since the U-groove is formed by photolithography in the conventional technology, the groove width is 1 μm. There was a limit to providing a U-groove, and there was also a limit to reducing the thickness of the deposited CVD insulating film.

The present invention was made in view of the above circumstances, and enables a U-groove isolation structure with a low dielectric constant coated with a thin insulating film, thereby improving the degree of integration and further improving the manufacturing process. The main objective is to provide a semiconductor integrated circuit device that can also be simplified.

The above-mentioned and other objects and novel features of the present invention will become clear from the description and appendices of this document.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

The semiconductor integrated circuit device according to the present invention has a U-groove having a groove width of 0.5 μm or less (hereinafter referred to as "submicron U-groove").
Each element is separated by the U-groove, and an insulator is filled in the U-groove.

[Function] According to the above-mentioned means, the groove width of the U groove is 0.5 μm or less, which is sufficiently narrower than that of the conventional groove, and filling with insulating material can be easily performed, so that an isolation structure with a low dielectric constant can be formed. This has been achieved, and furthermore, the miniaturization and high integration of integrated circuits can be achieved. Furthermore, the #@ edge inside the U groove can be made of a CVD insulating film,
At this time, the depressions generated on the U-groove are so small as to be ignored, and flattening is achieved.

[Example] Hereinafter, an example of a semiconductor integrated circuit device according to the present invention will be described based on the drawings.

FIGS. 1(a) to 1(k) are longitudinal cross-sectional views for explaining the manufacturing steps (a) to (l) of the semiconductor integrated circuit device (SEPT transistor) of this embodiment.

As mentioned above, conventionally, U formed on a silicon substrate
The accuracy of the groove corresponds to the accuracy of a photomask to be fitted to the substrate, and it has been difficult to reduce the width of the groove to 1 μm or less. Therefore, in this embodiment, using self-alignment technology, first 0.
A U-groove pattern having a groove width of 5 μm or less is formed (submicronization of the U-groove pattern), and in the following steps (g) and (h), anisotropy is performed based on the submicronization U-groove pattern. Perform etching to create a groove width of 0 in the silicon substrate.
．． A submicron U-groove of 5 μm or less is formed. after that,
The submicron UN is filled with an insulator to perform element isolation of the semiconductor integrated circuit device (steps (i) to (k)).

The manufacturing process will be specifically explained below.

(a) First, a silicon single crystal substrate l consisting of an N- epitaxial/1lla, an N+ buried layer 1b, and a P- substrate 1c.
An oxide film 2 is formed thereon, and a photoresist 3 for forming an element region is further bonded (FIG. 1(a)).

(b) After etching the oxide film 2 using the photoresist 3 as a mask and removing the photoresist 3, etching the silicon substrate 1 using the remaining oxide film 2 as a mask to form a shallow groove IF that will become a field region. Form(
Figure 1(b)).

(c) Remove the oxide film 2 and deposit the CVD insulating film 4 on the silicon substrate l having the shallow groove IF (FIG. 1(C))
).

(d) The U-groove processing photoresist 5 having the information of the 101.0 μm U-groove pattern 20 (see FIG. 6) is
It is bonded onto the VD insulating film 4, and the insulating film 4 is etched using the photoresist 5 as a mask.

A U-groove pattern 4a having a groove width of 1.0 μm corresponding to the U-groove pattern is obtained (FIG. 1(d)).

(e) After removing the photoresist 5, a CVD insulating film 6 is deposited over the entire insulating film 4 to a thickness less than half the width (160 μm) of the U-groove pattern 4a (see drawing (e)).
.

(f) Vertical anisotropic etching is performed on the CVD insulating film 6 to form the U-groove pattern 4 obtained in the step (d).
A side film 6a of a CVD insulating film is formed on the side wall of a, and the substantial groove width of the U groove pattern is set to 0.5 μm or less (submicron U groove pattern 7) (submicronization, FIG. 1(f)). ).

(g) Using the submicron U-groove pattern 7 as a mask, the silicon substrate 1 is etched to a desired depth by anisotropic etching to obtain a submicron U-groove 8. At this time, the U-groove bottom 9 is selectively doped with boron by ion-in plantation or the like to form a channel stopper 98 (FIG. 1(g)).

(H) Completely remove the CVD insulating films 4 and 6 from the silicon substrate (Fig. 1(h)).

(S) The entire silicon substrate 1 on which the U-groove 8 is formed,
If! The thickness is approximately the same as the depth of the shallow groove 1F formed in the step (b) above. Deposit the rim (CVD oxide).

In this embodiment, as a method of depositing an insulator, an oxide film 10 is first formed on the surface of a silicon substrate 1, and then a nitride film 11 is deposited thereon to ensure oxidation resistance in the process. A method of depositing CvDm-containing 12 is used later (FIG. 1(i)).

(J) Resist 13 so as to cover the CVD oxide film ②2.
is applied flatly (Fig. 1 (j)).

(l) Resist 13, CVD oxide film 12, and oxide film 1
0, at the same time and with the same selectivity, including the nitride film 1, at least the element regions Is, , I of the silicon substrate 1
Etch back until S2 is completely exposed to obtain a semiconductor integrated circuit device having a flat isolation structure (
Figure 1(k)).

Next, a process of further forming an active region of a 5EPT transistor in the element region of the semiconductor device formed in steps (a) to (l) as described above will be described.

FIG. 2 is an enlarged view of the element area IS process shown in FIG. 1 and/or FIG. 9, and shows the steps (A) to (
An active region is formed in F). For the sake of brevity, a description of the manufacturing process on the IS2 side where the collector outlet is formed will be omitted.

First, an oxide film (SiO2 film) 36 is formed on the surface of the element region 181.
A nitride film 37 is then deposited on the entire surface of the oxide film 36, and a non-doped polysilicon film 38 is further deposited on the surface of the nitride film 37.
．． Oxide film 39 and nitride film 11! Form J40 sequentially,
A photoresist is applied and a photoresist 41 having emitter/base information is formed by photolithography on a portion that will become an element region. Next, using this photoresist 41 as a mask, the nitride film 40 immediately below it is selectively etched, and boron (B) ions are implanted using the photoresist 41 as a mask. The state that has been completed up to this point is shown in FIG. 2(A).

Thereafter, after removing the photoresist 41, annealing is performed. As a result, the outer portion of the mask becomes boron-doped polysilicon 38a (numeral 38a is used to distinguish it from non-doped polysilicon 38), while the non-doped polysilicon 38 remains under the mask. Next, the surface is coated with a photoresist 4 such that only the oxide film 39 on the region where the graft base is to be formed is exposed.
2, this photoresist 42 and the nitride film 4
Using 0 as a mask, the oxide film 49 below it is etched. At this time, only the oxide film 39 on the area where the graft base is to be formed will be etched, but in that case,
Side etching of the oxide film 39 is performed as shown in FIG. 2(B).

Next, the photoresist 42 and nitride film 40 that served as a mask are removed, and the remaining oxide film 3 located below them is removed.
By etching the non-doped polysilicon 38 with hydrazine or the like using 9 as a mask, the nitride film 3 below the etched non-doped polysilicon 38 is removed.
8 is exposed, resulting in the state shown in FIG. 2(C).

Thereafter, the masked oxide film 39 is removed, and the exposed nitride film 37 is etched using the non-doped polysilicon 38 and the boron-doped polysilicon 38a as a mask.
is removed, resulting in the state shown in FIG. 2(D). In this state, boron ions are implanted into the region where the tether base is to be formed and the region where the graft base is to be formed.

Next, non-doped polysilicon 43 is deposited and annealed. Then, boron-doped polysilicon 38a
Diffusion (oil removal) of the boron implanted into the region where the graft base is to be formed occurs, and the non-doped polysilicon changes to boron-doped polysilicon 43a except the region where the emitter hole is to be formed. Next, after etching the non-doped polysilicon using hydrazine or the like, the boron-doped polysilicon 38a and 43a, which will become the polysilicon base extraction electrode 34 (see FIG. 4(F)), are etched.

After that, boron-doped polysilicon 43 is formed by thermal oxidation.
After oxidizing the surface of a to form an oxide film 44, the nitride film 3 inside the area where the emitter hole is to be opened is formed using this as a mask.
7 and the oxide film 36 are removed by dry etching (
Figure 4(E)).

A 5EPT transistor is obtained by depositing polysilicon as an emitter lead electrode so as to contact the emitter region on the structure formed by the above steps (FIG. 4(F)).

Next, other effects of this embodiment, in which the U-groove width is set to 0.5 μm or less and the dielectric constant is lowered by isolation using a CVD insulating film, will be explained.

First, since the groove width of the U-groove according to the present invention is 0.5 μm or less, the thickness of the CVDM edge film required for embedding the U-groove can be made thinner. The method of embedding a CVD insulating film in the U-groove has a depression, so C
vD#I! ! Although it was necessary to deposit a thick edge film (3 .mu.m), flattening can be achieved even if the deposited film is thin because no dents are created when filling the submicron U-groove according to the present invention as in the conventional method. Also, since the CVD insulating film is thick, the time required for deposition is also significantly reduced.

Now, let us consider the relationship between the flatness d, which represents the degree of concavity of the depression formed on the U-groove, and the groove width W of the U-groove.

FIG. 3 is a diagram in which a CVD insulating film is deposited to the same thickness as the U-groove with a groove width W. If α is the angle between the straight line connecting the groove shoulder M and the deepest part of the recess G of the CVDM edge film formed on the U groove with the perpendicular line N, then the flatness d (from the flat surface of the insulating film to the deepest part K The distance i1) to α2 d = D (1-cos α): D □ =' (
1).

get.

Therefore, it can be seen that the flatness d of the film changes as the square of the groove width W, and if the groove width W is made finer, the flatness will be rapidly improved. Suppose that a submicron U groove (groove width W = 0.2
A CVD insulating film is applied to the substrate (μm).

Considering the case of 0 μm deposition, the flatness d is as shown in (2) above.
From the formula, d:o, 005 μm.

Second, the U-groove according to the present invention does not require etchback, or the width of etchback is small enough, so there is no risk of exposing the cavity formed inside the CVD insulating film (fourth point).
), the cavity can be actively used for stress relaxation.

Thirdly, in a semiconductor integrated circuit device (SEPT transistor) having a shallow trench in the silicon substrate 1 as in this embodiment, the shallow trench and the U-groove can be filled with insulators at the same time, and the manufacturing process of the integrated circuit device is simplified. Simplified.

When the process is simplified in this way, the uniformity of the isolation film thickness within the wafer becomes high.

Specifically, if we consider a case where the variation in the polysilicon deposited film thickness is 5% and the variation in etchback is 5% in conventional U-groove isolation using polysilicon, then The film thickness is 4μ
m, if the etchback amount is 3IIm, then 0.25μm
(=v' (4μmX5%)2+(3μmX5%)2)
This will result in an error. On the other hand, in the U-groove isolation according to the present invention, the CVDM edge film (1 μm)
Since the error due to variations during formation is only 0.05 .mu.m, the uniformity within the wafer is much better than that of the conventional method.

By the way, when a U-groove is formed on a silicon substrate, the groove width at a part of the corner of the U-groove pattern is enlarged. That is, as shown in Fig. 5, the expansion of the groove width in a part of this corner corresponds to the bending angle 0, and the groove width expansion rate Y indicating the degree is expressed as follows using the bending angle θ as a parameter. (The larger Y is, the greater the effect of widening the groove width.-2a Here, The thickness of the side film 6a is (X-2a)
corresponds to the groove width W of the submicron U groove after miniaturization.

As is clear from equation (3), the smaller the bending angle θ of the corner, the smaller the effect of widening the groove width.

Therefore, in this example, in order to prevent the flatness from deteriorating when filling the U-groove due to the groove width expansion effect, the layout of the photoresist for U-groove processing used in the above-mentioned step (d) was bent into an octagonal closed loop with a small angle θ. Made into an isolation pattern.

FIG. 6 shows a plan layout of a U-groove pattern with a low level difference in a closed loop, and shows a bending angle θ of a part of the corner of the U-groove pattern 20.
are all set to 45 degrees, and the effect of enlarging the groove width at a part of the corner of all is equally reduced.

Furthermore, the effect of enlarging the groove width at the T-shaped intersections of the U-groove pattern photomask can be reduced by forming a pattern as shown in FIG.

FIG. 8 is a sectional view showing another embodiment in which isolation according to the present invention is performed on a silicon substrate without shallow grooves.

In this case, the recess on the U groove = 23.24 is negligibly small (when the film thickness is 1 μm and the groove width is 0.2 μm, the flatness is d
is 0°005 μm from the above formula (2)), therefore,
An etch-back process for thinning the film becomes unnecessary.

9 and 10 show an example in which the Um isolation according to the present invention is applied to a silicon substrate-oxide film-silicon substrate (ultra-thin type) SOI substrate. Exactly the same effects as in the respective embodiments can be obtained. As described above, the isolation according to the present invention is particularly effective for semiconductor integrated circuits using SOI substrates or sO8 substrates, which require complicated manufacturing processes.

In FIGS. 9 and 10, 25 represents an oxide film, and 26 represents an ultra-thin silicon substrate.

In this example, a side film was formed on the wall surface of the U-groove pattern with a groove width of 1 μm in order to make the U-groove pattern submicron. A film is deposited, non-doped polysilicon is deposited on this film, boron is implanted into this non-doped polysilicon using a U-groove pattern with a groove width of 1 μm as a mask, and boron in the polysilicon is laterally implanted by annealing. By etching the non-doped polysilicon portion after diffusion, submicron U
A groove pattern may also be formed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, according to the semiconductor integrated circuit device of the present invention, each element of the semiconductor integrated circuit is separated by an elongated groove with a groove width of 0.5 μm or less, and the U-groove is filled with an insulator, so that the semiconductor By reducing the dielectric constant of the isolation of an integrated circuit, it is possible to reduce the capacitance, and by reducing the element separation distance, it is possible to achieve miniaturization and high integration of the integrated circuit.

Further, when filling the U trench by depositing a CVD insulating film, planarization is performed with a thin CVD insulating film, thereby simplifying the manufacturing process. In addition, 5EPT, 5I with shallow grooves
When the present invention is applied to a COS transistor, it is possible to form a U-groove within the shallow groove and bury the shallow groove and the U-groove at the same time, thereby further simplifying the manufacturing process.

[Brief explanation of drawings]

@The engineering drawing is a vertical cross-sectional view for explaining the element isolation process of the semiconductor integrated circuit device according to the present invention, and FIG.
FIG. 3 is a longitudinal sectional view for explaining the manufacturing process for forming the active region of the T transistor; FIG. 3 is a longitudinal sectional view for explaining the relationship between the groove width W of the U groove and the flatness d of the device surface; The figure is a longitudinal cross-sectional view for explaining how the insulator is deposited in the submicron U-groove according to the present invention, and FIG. Plan view for explanation,
FIG. 6 is a plan view showing a submicron U-groove pattern photomask according to the present invention. Figure 7 shows a U that reduces the effect of widening the groove width at the intersection of the T-shape.
FIG. 8 is a plan view showing a groove pattern photomask, and FIG. 8 is a longitudinal sectional view showing an example in which the isolation according to the present invention is applied to a semiconductor integrated circuit having no shallow grooves. Fig. 9 is a vertical cross-sectional view showing an example in which the isolation according to the present invention is applied to a semiconductor integrated circuit using an SOI substrate, and Fig. 1O is a vertical cross-sectional view showing an example in which the isolation according to the present invention is applied to a semiconductor integrated circuit using an SOI substrate without shallow grooves. FIG. 11 is a vertical cross-sectional view showing an example of applying the isolation of the present invention. FIG. 11 is a vertical cross-sectional view showing the structure of a conventional U-groove isolation. 1...Silicon single crystal substrate, 2...Oxide film, 3
...Photoresist for forming element region, 4...C
VD insulating film, 4a...U groove pattern, 5...U
Photoresist for groove processing, 6...CVDN edge film 6a
...Side film, 7...Submicron U groove pattern, 8...Submicron U groove, Machining 0...
Oxide film, 11...Nitride film, Work 2...C
VD oxide film, 2o...submicron U groove pattern. Figure 7 Figure 7

Claims (1)

[Claims] 1. Separation between each element of the semiconductor integrated circuit has a groove width of 0.5 μm
A semiconductor integrated circuit device characterized in that the U-groove is formed by the following U-groove, and the U-groove is filled with an insulator. 2. The semiconductor integrated circuit device according to claim 1, wherein said insulating material is filled by depositing a CVD oxide film. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device has a shallow groove on the substrate, wherein the U-groove is formed within the shallow groove.