JP2007088312A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which keeps bending of a board forming an element to a small extent to offer a highly reliable dielectric isolation structure. <P>SOLUTION: In the semiconductor device, one or more trenches in closed loop patterns are formed on the main surface of the SOI (Silicon on Insulator) board, and polycrystal silicon films are held between insulating films covering the side walls of the trenches. The insulating films and polycrystal silicon films are exposed on the same plane at the openings of the trenches. The trenches dielectrically separate a plurality of semiconductor elements formed on the SOI board. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device that completely separates a semiconductor element formed on an SOI (Silicon on Insulator) substrate using a trench.

In an integrated circuit device (power IC) having a high withstand voltage of several tens to several hundreds of volts between semiconductor elements, a method is known in which each semiconductor element to be integrated is separated by an insulating film (for example, an oxide film: SiO ₂ film). ing. A method of processing a semiconductor silicon single crystal wafer is generally used for manufacturing a dielectric separation substrate. Unlike the PN junction isolation, the dielectric isolation separates the semiconductor elements with an insulating film, so there is no latch-up phenomenon, and the logic circuit and the power switch unit can be made into one chip and have a high breakdown voltage. Currently, products of a class whose power capacity exceeds 100 W have been put into practical use. There exists patent document 1 as a patent regarding such a dielectric separation board.

FIG. 3 is a cross-sectional view of a prior art dielectric isolation substrate, and FIG. 4 is a cross-sectional view illustrating the manufacturing process. First, the main surface of the single crystal silicon 1 is oxidized, and an insulating film 2 (for example, SiO ₂ film) is formed on the entire surface as shown in FIG. Next, after patterning by a photolithographic method (hereinafter abbreviated as photolithography), the insulating film 2 at a predetermined location is removed by a method such as etching. Next, with the remaining insulating film 2 as a mask, the isolation groove 3 having a depth of about 5 μm to 80 μm is formed as shown in FIG. 4B by anisotropic etching using, for example, a mixed solution of potassium hydroxide and isopropyl alcohol. . Next, all of the insulating film 2 used as the mask is removed by etching. Thereafter, the main surface of the single crystal silicon 1 is oxidized again to form an isolation insulating film 21 (for example, SiO ₂ film) having a thickness of 1 μm to 5 μm on the entire surface. The first polycrystalline silicon 4 is deposited on the surface by a high temperature (about 1000 ° C. to 1250 ° C.) vapor phase growth method (CVD method) to fill the separation groove 3 (50 μm to 300 μm). Using the surface of the single crystal silicon 1 as a reference, the large recesses of the first polycrystalline silicon 4 are removed by a method such as grinding, and fine uneven portions on the surface are removed by a method such as CMP. Next, the second polycrystalline silicon 5 is deposited on the smooth surface of the first polycrystalline silicon 4 with a thickness of about 2 μm to 5 μm by a low temperature (about 500 ° C. to 800 ° C.) vapor phase growth method (CVD method). Thereafter, the surface of the formed second polycrystalline silicon 5 is polished by a method such as CMP to form a smooth surface 6 capable of wafer bonding as shown in FIG. Next, the main surface of the single crystal silicon 7 of the support is oxidized to form the insulating film 2 on the entire surface, the surface and the polished surface are bonded together, and two wafers are formed by high-temperature heat treatment (annealing). Join as shown in 4 (d). After the bonded substrate is chamfered at the outer periphery, unnecessary portions are removed by grinding or polishing to form single crystal islands 8 separated by the insulating film 21 to form the dielectric shown in FIG. Complete the separation substrate.

  In the dielectric isolation substrate manufactured by the above method, the semiconductor element 9 is formed in each single crystal island 8 as shown in FIG. 3 by a process similar to the LSI manufacturing process, and the metal thin film is patterned. By wiring between the elements, a semiconductor integrated circuit is manufactured.

Japanese Patent Laid-Open No. 6-151572 (FIG. 1, description from paragraph (0016) to paragraph (0021))

  In the above prior art, when the breakdown voltage of the semiconductor element 9 shown in FIG. 3 is increased, the isolation trench 3 is deepened and the single crystal island 8 is enlarged. In addition, the size of the single crystal island 8 requires a pattern layout with the size of the single crystal island 8 in consideration of the amount of polishing and grinding in the final process of manufacturing the dielectric isolation substrate, and hinders reduction of the chip size. It has become.

  In the experiments by the inventors of the present application, the dimensional shift amount of the single crystal island 8 with respect to the mask design value is as large as −1 μm to −15 μm. Further, due to the difference in thermal expansion coefficient between the single crystal silicon 7 and the first polycrystalline silicon 4 of the support, the substrate is bent or distorted by the high temperature heat treatment during the formation of the semiconductor element 9. According to the measurement by the inventors of the present application, an increase in the substrate bending amount of about 100 μm to 200 μm has been confirmed between the completion of the dielectric separation substrate of the prior art and the completion of the process of forming the semiconductor element 9. Such a change in the amount of bending of the substrate is caused by a decrease in alignment accuracy in the photolithography process for patterning the semiconductor element 9 and a pattern resolution failure due to a change in the distance from the exposure light source to the substrate surface (a change in the depth of focus). This causes the characteristics of the semiconductor element 9 to be affected. In addition, a change in the resistance value of the diffusion layer due to the piezo effect or the like is known, and as a result, there is a problem that variation in electrical characteristics of the semiconductor element 9 increases.

  Furthermore, the position accuracy when bonding the single crystal silicon 1 and the support single crystal silicon 7 is as large as 5 mm to 6 mm, and the position of the auto-alignment target for the photolithography process produced on the single crystal silicon 1 is not constant depending on the substrate. The auto-alignment rate at the time of the photolithography work in the semiconductor element 9 forming process is low, and the work efficiency is poor. In addition, since the first polycrystalline silicon 4 is formed at a high temperature (about 1000 ° C. to 1250 ° C.), thermal etching occurs due to metal contamination or film formation temperature during the film formation, and the insulating film 21 is partially formed. In some cases, a defect occurs such that a desired breakdown voltage between single crystal islands cannot be obtained.

  An object of the present invention is to provide a highly reliable semiconductor device that solves the problems described above.

  The semiconductor device of the present invention has one or more closed-loop pattern trenches formed on the main surface of the SOI substrate, and is embedded in the trench sidewall and trench opening with an insulating film and a polycrystalline silicon film. The semiconductor element formed on the SOI substrate by the trench is completely dielectrically separated.

  The semiconductor device of the present invention has a small amount of bending of the dielectric isolation substrate and high reliability.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory view of a semiconductor device to which the dielectric isolation substrate of this embodiment is applied. FIG. 1A is a cross-sectional view of the semiconductor device of this embodiment, and FIG. 1B is a plan view. As shown in FIG. 1, the semiconductor device of the present embodiment has a semiconductor element 9 formed by an insulating film 22 such as a SiO ₂ film, a trench 10 buried with a second polycrystalline silicon 51, and an insulating film 2. Each of the formed single crystal islands 8 has a structure in which dielectrics are completely separated. In the following description, the semiconductor element 9 is described by taking a power MOSFET as an example, but the same applies to a power semiconductor switching element such as an IGBT or a bipolar transistor.

  First, the manufacturing process of the semiconductor device of this embodiment will be described with reference to FIG. First, as shown in FIG. 2A, the main surface of the single crystal silicon 7 as a support is oxidized to form an insulating film 2, and another single crystal silicon 1 is bonded through the insulating film 2. The two wafers of the single crystal silicon 7 and the single crystal silicon 1 as a support are bonded by heat treatment. After bonding, the surface of the single crystal silicon 1 is ground and polished by the CMP method to a predetermined single crystal island thickness.

Thereafter, the outer peripheral portion of the bonded wafer is chamfered, and an insulating film 2 'is formed on the surface again by oxidation. Next, patterning is performed on the wafer by a photolithography so that the planar shape thereof is a closed loop shape, for example, a quadrilateral such as a square or a rectangle, and the insulating film 2 'is etched by anisotropic dry etching. Next, using this anisotropic dry-etched insulating film 2 'as a mask, the single crystal silicon 1 is further etched by anisotropic dry etching to form a trench 10 shown in FIG. For the anisotropic dry etching, it is common to use a microwave dry etching, an ICP dry etching apparatus or the like. In anisotropic dry etching, Cl ₂ , SF ₆ , HBr, O ₂ or the like is used as an etching gas. Here, for example, when Cl ₂ and O ₂ are used as an etching gas, the selection ratio, which is the ratio between the etching rate of silicon in microwave dry etching and the etching rate of SiO ₂ that is an insulating film, is about 15 to 30. Therefore, when the insulating film 2 at the bonding interface is exposed, the etching rate becomes slower than the etching rate of the single crystal silicon 1, so that the insulating film 2 at the bonding interface serves as an etching stopper and serves as a desired trench 10. Depth can be obtained. After the trench etching, the entire surface of the insulating film 2 'used as a mask is removed using HF solution or the like, and an insulating film 22 covering the surface and the inside of the trench is formed by oxidation as shown in FIG. At this time, if the thickness of the insulating film 22 is too thick with respect to the width of the trench 10, it causes crystal defects and the like due to stress concentration at the bottom of the trench. According to the experiment results of the inventors, when the width of the trench 10 is 2 μm, the maximum film thickness of the insulating film 22 needs to be 1 μm or less. That is, if the trench 10 is completely buried only by oxidation, crystal defects due to stress concentration occur.

  Next, at a low temperature of about 500 ° C. to 800 ° C., the second polycrystalline silicon 51 is deposited by a vapor deposition method (CVD method) with a thickness that allows the trench 10 to be completely filled. For example, when the width of the trench 10 is 2 μm and the total film thickness of the two insulating films 22 inside the trench 10 is 0.8 μm, the second polycrystalline silicon 51 having a thickness of 1.2 μm or more is necessary. Thereafter, the polycrystalline silicon deposited on the surface is removed by grinding and polishing using a method such as CMP. As a result, the second polycrystalline silicon 51 remains inside the trench, and there is no portion that rises or protrudes from the opening of the trench, and all other portions are covered with the insulating film 22 as shown in FIG. Become. That is, the surface of the second polycrystalline silicon 51 embedded in the trench 10 by grinding and polishing of the second polycrystalline silicon 51 deposited on the surface is an insulating film formed on the surface as shown in FIG. The same surface as the film 22 is exposed. Subsequently, the insulating film 22 is removed by patterning and etching at a place other than the trench 10 by photolithography, that is, a place where the semiconductor element 9 is to be formed in a later process, thereby producing a semiconductor element forming region. The dielectric separation substrate is completed through the above manufacturing steps.

  A semiconductor integrated circuit is manufactured by forming a semiconductor element 9 in each single crystal island 8 by a process similar to an LSI manufacturing process from the dielectric isolation substrate manufactured by the above method. In this embodiment, as shown in FIG. 1, a horizontal power semiconductor device in which a gate electrode 13 as a control electrode and a source electrode S and a drain electrode D as main electrodes are arranged on the upper surface of a single crystal island 8. A power MOSFET was created. It goes without saying that a horizontal IGBT can be similarly produced.

  FIG. 5 and FIG. 6 show the experimental results of the inventors' dielectric breakdown voltage between the single crystal islands 8 and the bending amount of the substrate. FIG. 5 shows a single crystal when the width of the trench 10 is 2 μm, the total thickness of the two insulating films 22 is 0.8 μm, the thickness of the second polycrystalline silicon 51 is 1.2 μm, and the depth of the trench 10 is 5 μm. 5 shows the withstand voltage between the islands 8 and the withstand voltage between the single crystal islands 8 formed on the dielectric isolation substrate having the conventional structure shown in FIGS. As shown in FIG. 5, the single crystal island 8 of the dielectric isolation substrate of the present example is an average withstand voltage of 1200 V between the single crystal islands 8 formed on the prior art dielectric isolation substrate shown in FIGS. In contrast, the dielectric strength characteristics equivalent to 1250V were exhibited.

  As shown in FIG. 6, the substrate bending amount at the time of completion of the dielectric separation substrate was about 100 μm to 200 μm in the conventional structure shown in FIGS. Improved. Further, the dimensional shift amount of the semiconductor element 9 formed on the single crystal island 8 with respect to the mask design value is greatly improved to -0.5 .mu.m to 1.5 .mu.m in this embodiment, compared to -1 .mu.m to -15 .mu.m of the prior art. . Further, in the method for manufacturing a dielectric separation substrate in this embodiment, since the first photolithography is after the wafer bonding process, the photolithography target position accuracy is improved, and in the conventional dielectric separation substrate, the photolithography target is improved. Whereas the positional accuracy varied from about 1 mm to 3 mm, in this example, it was greatly improved to about 100 μm to 300 μm. Further, the film forming process of the first polycrystalline silicon 4 at 1000 ° C. to 1300 ° C. which is the manufacturing process of the prior art shown in FIG. 4 is not required, and the manufacturing process is very simple.

FIG. 7 shows a semiconductor device of this example. In this embodiment, when the dielectric separation substrate is manufactured, a high concentration (1 × 10 ¹⁸ cm ⁻³ to 10 ²⁰ cm ^{− is applied} to the main surface of the single crystal silicon 1 on the side bonded to the single crystal silicon 7 of the support by ion implantation. The diffusion layer of ³ ) was formed, bonded to the single crystal silicon 7 of the support that was previously oxidized to form the insulating film 2, and the two wafers were bonded by heat treatment. After that, after forming the trench 10 by the same method as in the first embodiment, as shown in FIG. 7, the high concentration diffusion layer 11 is formed at the bottom of the single crystal island 8 and the portion where the single crystal island 8 is in contact with the sidewall of the trench 10. Form. If the high-concentration diffusion layer 11 to be formed is a high-concentration n ⁺ layer, antimony or phosphorus is diffused, and if it is a high-concentration p ⁺ layer, boron diffusion or the like is performed to form the high-concentration diffusion layer 11. After the high concentration diffusion layer 11 is formed, the substrate is completed by the same manufacturing method as in the first embodiment.

  In this example, as in Example 1, good dielectric strength voltage, substrate bending amount, dimensional shift amount of the semiconductor element 9 and photolithography target position accuracy were shown.

  FIG. 8 shows a semiconductor device of this example. The semiconductor device of this example is a LOCOS oxide film formed by a LOCOS method (Local Oxidation of Silicon method) in an element region isolated as shown in FIG. 8 on the dielectric isolation substrate manufactured in Example 1. 14, a gate oxide film 12, a gate electrode 13, and an insulating film 2 are sequentially provided, and the electrode electrode 16 is connected to the gate electrode 13 from the silicon of the single crystal island 8 on the surface of the SOI substrate through the contact hole 15. It has become.

  The semiconductor device of this embodiment is different from the semiconductor device of FIGS. 1 and 7 in that the LOCOS oxide film 14 covers the insulating film 22 and the second polycrystalline silicon 51 inside the trench as shown in FIG. To do. In the present embodiment as well, similar to the first and second embodiments, good withstand voltage, substrate bending amount, dimensional shift amount of the semiconductor element 9 and photolithography target position accuracy were shown.

  FIG. 9 shows a semiconductor device of this example. In the present embodiment, the LOCOS oxide film 14 formed by the LOCOS method, the gate oxide film 12, and the gate are formed in the isolated element region on the dielectric isolation substrate manufactured in the first embodiment as shown in FIG. The electrode 13 and the insulating film 2 were sequentially provided, and the electrode wiring 16 was taken out through the contact hole 15 from the gate electrode 13 and the single crystal silicon 1 on the SOI substrate surface.

  Further, as shown in FIG. 9, the semiconductor device of the present embodiment includes a three-layer electrode wiring instead of the electrode wiring 16 of the third embodiment, and the first electrode and the third electrode of the TiW electrode 19 are provided. The electrode has a sandwich structure in which the second electrode of the AlSiCu electrode 20 is sandwiched from above and below. In the semiconductor device of this embodiment, TiW having a high melting point is used as the wiring material, so that the reliability of the electrode wiring with respect to the assembly heat treatment (450 ° C. to 600 ° C.) can be improved. In the present embodiment as well, similar to the first and second embodiments, good withstand voltage, substrate bending amount, dimensional shift amount of the semiconductor element 9 and photolithography target position accuracy were shown.

  FIG. 10 shows a semiconductor device of this example. In the present embodiment, a LOCOS oxide film 14, a gate oxide film 12, a gate electrode 13, and an insulating film formed by the LOCOS method in the isolated element region on the dielectric isolation substrate manufactured in the first embodiment. 2 and as shown in FIG. In the semiconductor device of this embodiment, the LOCOS oxide film 14 has a structure including an insulating film step 18 having a taper angle of 10 ° to 30 ° with respect to the silicon surface of the single crystal island 8. As shown in FIG. 10, the insulating film step 18 is disposed above the silicon on the single crystal island 8 inside the insulating film 22 formed in the trench. In the insulating film step 18, the insulating film 22 The LOCOS oxide film 14 becomes thinner from the side toward the inside of the single crystal island 8.

  The insulating film step 18 having a taper angle of 10 ° to 30 ° of the semiconductor device of the present embodiment is a photolithography process in which a portion where a semiconductor element is formed in the final step of manufacturing the dielectric isolation substrate is formed by patterning and etching. Then, the resist can be formed by using a positive resist and performing wet etching using HF liquid or the like. When dry etching is used in place of this wet etching, the taper angle of the step portion becomes 70 ° to 90 °. Therefore, disconnection at the step portion is likely to occur in the wiring formation process of the gate electrode 13 later.

  In this embodiment, the insulating film step portion 18 having a gentle taper is formed by the combination of the positive resist and the wet etching, and the disconnection of the electrode wiring 16 in the step portion is prevented, thereby improving the reliability of the semiconductor device.

  FIG. 11 shows a semiconductor device of this example. In the present embodiment, the LOCOS oxide film 14, the gate oxide film 12, the gate electrode 13, and the insulating film 2 formed by the LOCOS method are illustrated in the isolated element region on the dielectric isolation substrate manufactured in the first embodiment. As shown in FIG. 11, the LOCOS oxide film 14 on the second polycrystalline silicon 51 is provided with a step portion 23 having a height of 0.3 μm to 0.7 μm.

  In the dielectric isolation substrate fabricated in Example 1, the upper part of the trench is exposed on the surface of the second polycrystalline silicon 51 substrate. In the LOCOS oxidation process, which is the stage of forming the semiconductor element, the second polycrystalline silicon 51 is formed. The oxidation rate is higher than that of the surrounding insulating film 2 region, and therefore a step 23 is formed on the second polycrystalline silicon 51. With this structure, the LOCOS oxide film 14 on the second polycrystalline silicon 51 becomes thicker, in other words, the insulation distance between the LOCOS oxide films 14 on the second polycrystalline silicon 51 becomes longer, The insulation performance of the gate electrode on the LOCOS oxide film 14 from the electrode wiring 16 can be improved.

  In this embodiment, when the height of the stepped portion 23 is lower than 0.3 μm, the effect of improving the insulating performance is reduced. In addition, if the height of the step portion 23 is higher than 0.7 μm, the surface of the insulating film 2 may not be flat but may be uneven, and the electrode wiring 16 of the gate electrode 13 may be disconnected.

  FIG. 12 shows a semiconductor device of this example. FIG. 12A is an explanatory view of a cross section of the semiconductor device of this embodiment, and FIG. 12B is an explanatory view of a plane of the semiconductor device of the embodiment. The semiconductor device of this example was formed on the dielectric isolation substrate manufactured in Example 1. As shown in FIG. 12B, in the semiconductor device of the present embodiment, the planar shape of the corner portion 17 continuing from the straight portion in the quadrilateral trench pattern is not all right, unlike FIG. It has an arc shape. When the corner portion 17 intersects at a right angle, when the inside of the trench 10 is oxidized, the corner portion 17 is subjected to stress, which may cause crystal defects and the like. A semiconductor device having an effect and higher reliability can be manufactured. The radius of the corner portion 17 of the trench pattern may be at least twice the width of the second polycrystalline silicon 51 shown in FIG. 12B, and preferably from 2 to 20 times. If the corner radius is less than twice, the stress relaxation becomes insufficient, and if it is more than 20 times, the shape of the substrate plane of the substantially rectangular single crystal island 8 cannot be maintained, and the density of the single crystal island 8 formed on the substrate surface It becomes difficult to raise.

1 is an explanatory diagram of a semiconductor device of Example 1. FIG. FIG. 10 is an explanatory diagram of a manufacturing process of the semiconductor device of Example 1; Sectional drawing of the semiconductor device of a prior art. Explanatory drawing of the manufacturing process of the semiconductor device of a prior art. Explanatory drawing of the withstand voltage of the dielectric isolation structure of Example 1 and a prior art. Explanatory drawing of the board | substrate curvature amount of the dielectric material separation structure of Example 1, and a prior art. FIG. 6 is a cross-sectional view of the semiconductor device of Example 2. FIG. 10 is a cross-sectional view of the semiconductor device of Example 3; FIG. 10 is a cross-sectional view of the semiconductor device of Example 4; FIG. 10 is a cross-sectional view of the semiconductor device of Example 5; Sectional drawing of the semiconductor device of Example 6. FIG. FIG. 10 is an explanatory diagram of a semiconductor device of Example 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 7 ... Single crystal silicon, 2, 2 ', 21, 22 ... Insulating film, 3 ... Separation groove, 4 ... 1st polycrystalline silicon, 5, 51 ... 2nd polycrystalline silicon, 6 ... Smooth surface, DESCRIPTION OF SYMBOLS 8 ... Single crystal island, 9 ... Semiconductor element, 10 ... Trench, 11 ... High concentration diffusion layer, 12 ... Gate oxide film, 13 ... Gate electrode, 14 ... LOCOS oxide film, 15 ... Contact hole, 16 ... Electrode wiring, 17 ... corner part, 18 ... insulating film step part, 19 ... TiW electrode, 20 ... AlSiCu electrode, 23 ... step part.

Claims (14)

In a semiconductor device in which a power semiconductor element is formed on an SOI substrate (Silicon on Insulator) in which a plurality of single crystal islands are arranged via an insulating film on a support substrate,
The plurality of single crystal islands are surrounded by trenches in a closed loop pattern,
A semiconductor device characterized in that the inside of the trench is filled with an insulating film covering an inner wall of the trench and a polycrystalline silicon film sandwiched between the insulating films.   2. The semiconductor device according to claim 1, wherein a portion of the single crystal island in which the power semiconductor element is formed is in contact with an insulating film covering the inner wall of the trench and a portion of the supporting substrate in contact with the insulating film is highly concentrated. A semiconductor device, wherein a diffusion layer is formed.   2. The semiconductor device according to claim 1, wherein a LOCOS oxide film, a gate oxide film, a gate electrode disposed on the gate oxide film, and the gate electrode are formed on the single crystal island which is an isolated element region. And an insulating film covering the LOCOS oxide film, and electrode wiring is taken out from the gate electrode and the S single crystal island through a contact hole formed in the insulating film.   4. The semiconductor device according to claim 3, wherein the electrode wiring taken out from the gate electrode and the S single crystal island through the contact hole formed in the insulating film is formed by sandwiching the AlSiCu electrode wiring from above and below with the TiW electrode wiring. A semiconductor device having a structure.   4. The semiconductor device according to claim 3, wherein the LOCOS oxide film has a step portion having a taper angle of 10 ° to 30 ° with respect to the silicon surface of the single crystal island, and the step portion is provided. apparatus.   4. The semiconductor device according to claim 3, wherein the LOCOS oxide film has a step portion having a height of 0.3 [mu] m to 0.7 [mu] m above the polycrystalline silicon buried in the trench.   4. The semiconductor device according to claim 3, wherein the power semiconductor element formed on the single crystal island is a power MOSFET.   4. The semiconductor device according to claim 3, wherein the power semiconductor element formed on the single crystal island is an IGBT.   2. The semiconductor device according to claim 1, wherein the closed loop pattern of the trench formed on the surface of the SOI substrate has a corner portion continuing from the straight portion in an arc shape. In a semiconductor device in which a power semiconductor element is formed on an SOI substrate (Silicon on Insulator) in which a plurality of silicon single crystal islands are arranged via an insulating film on a silicon substrate of a support,
The plurality of single crystal islands are surrounded by a quadrilateral closed-loop planar trench,
The interior of the trench, and the SiO ₂ insulating film covering the opposing inner wall of the trench, respectively, are embedded by a polycrystalline silicon film sandwiched between the SiO ₂ insulating film, the SiO ₂ insulating the opening of the trench A semiconductor device characterized in that the film and the polycrystalline silicon film are exposed on the same plane. The semiconductor device according to claim 10, the semiconductor device characterized by top of the SiO ₂ insulating film and the polycrystalline silicon film exposed in the trench opening is covered by the LOCOS oxide film. In a semiconductor device in which a power semiconductor element is formed on an SOI substrate (Silicon on Insulator) in which a plurality of single crystal islands are arranged via an insulating film on a support substrate,
The plurality of single crystal islands are surrounded by trenches in a closed loop pattern,
The inside of the trench is buried with an insulating film covering the inner wall of the trench, and a polycrystalline silicon film sandwiched between the insulating films,
A semiconductor device, wherein a control electrode, a first main electrode, and a second main electrode of the power semiconductor element are formed on an upper surface of the single crystal island.   13. The semiconductor device according to claim 12, wherein the power semiconductor element formed on the single crystal island is a power MOSFET. 13. The semiconductor device according to claim 12, wherein the power semiconductor element formed on the single crystal island is an IGBT.

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