JPH01103851A - High withstand voltage semiconductor element - Google Patents

High withstand voltage semiconductor element

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Publication number
JPH01103851A
JPH01103851A JP62293456A JP29345687A JPH01103851A JP H01103851 A JPH01103851 A JP H01103851A JP 62293456 A JP62293456 A JP 62293456A JP 29345687 A JP29345687 A JP 29345687A JP H01103851 A JPH01103851 A JP H01103851A
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Japan
Prior art keywords
layer
semiconductor layer
type layer
type
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62293456A
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Japanese (ja)
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JP2896141B2 (en
Inventor
Akio Nakagawa
明夫 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Publication of JP2896141B2 publication Critical patent/JP2896141B2/en
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Abstract

PURPOSE:To obtain sufficient high withstand voltage characteristics even through a first semiconductor layer is a thin one by a method wherein a fifth semiconductor layer having a low-impurity concentration is provided on a part adjacent to an insulator film under the bottom part of an element and part of an inverse bias applying voltage to the element is borne by a dielectric isolation film by a third semiconductor layer. CONSTITUTION:When a reverse bias is applied between first electrodes 11 and a second electrode 12, a depletion layer first spreads from an n<+> layer 6 in the center of the surface of an element into a high-resistance Si layer 4 in the longitudinal direction. If the thickness of the layer 4 and the impurity concentration of a p<-> layer 10 are each ready-set at a proper value, the largest electric field of the layer 4 is obtained at a value or less, at which an avalanche breakdown is generated, even though the layer 4 is depleted completely and the layer 10 under the bottom part of the layer 4 is depleted soon. If the layer 10 is depleted, the potentials of the electrodes 11 do not transmit up to right under the electrode 12. That is, a potential difference is generated in the depleted layer 10 in the lateral direction, the voltages between the electrodes 11 and 12 is finally divided into two components, one in the thickness direction of the layer 4 and one in the lateral direction of the layer 10, and high withstand voltage characteristics are shown even though the layer 4 is not thick.

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、誘電体分離を用いた高耐圧半導体素子に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a high voltage semiconductor device using dielectric isolation.

（従来の技術） 高耐圧半導体素子を分離する有力な方法として、誘電体
分離法がよく知られている。(Prior Art) A dielectric isolation method is well known as an effective method for isolating high-voltage semiconductor elements.

第１７図は、その様な誘電体分離を施した従来の高耐圧
ダイオードの例である。７１はｐ＋型ｓｉ基板であり、
直接接着技術によってこれとｐ−型Ｓｉ基板を接着した
基板ウェー八を用いている。FIG. 17 shows an example of a conventional high voltage diode with such dielectric isolation. 71 is a p+ type Si substrate;
A substrate wafer is used, to which a p-type Si substrate is bonded using direct bonding technology.

７３は接着界面であり、７２はこの接着界面部の酸化膜
である。この接着基板ウェーへのｐ−型基板側を接着界
面７３に達する深さにエツチングして溝を掘ることによ
り島状のｐ−型層７４を形成し、溝の側面に酸化膜７５
を形成して、この溝には多結晶シリコン膜７６を埋め込
む。こうして酸化膜７２．７５により他の領域から分離
された島状ｐ−型層７４の中央表面部にｎ＋型層７８、
更にその周辺にｎ−型層７９を形成して、ダイオードが
構成されている。ｐ−型層７４の周辺部にはアノード電
極を取出すためのｐ＋型層８ｏが形成されている。また
、大電流を流せるようにするために、島状ρ−型層７４
の周囲を取囲むように酸化膜７２．７５に沿ってｐ＋型
層７７が設けられている。73 is an adhesive interface, and 72 is an oxide film at this adhesive interface. An island-shaped p-type layer 74 is formed by etching the p-type substrate side of the bonded substrate wafer to a depth that reaches the bonding interface 73, and an oxide film 75 is formed on the side surface of the groove.
A polycrystalline silicon film 76 is filled in this groove. In this way, an n+ type layer 78,
Further, an n-type layer 79 is formed around it to form a diode. A p+ type layer 8o is formed around the p- type layer 74 to take out the anode electrode. In addition, in order to allow a large current to flow, the island-like ρ-type layer 74
A p+ type layer 77 is provided along the oxide films 72 and 75 so as to surround the periphery of the oxide film 72 and 75.

このダイオードは、アノード・カソード間に逆バイアス
を印加した時、空乏層はｎ＋型層７８からｐ−型層７４
側に伸びる。空乏層先端がｐ＋型層７７に達するまで逆
バイアスを大ぎくすると、パンチスルーを生じる。従っ
てこのダイオードの耐圧を十分高いものとするためには
、ｎ＋型層７８とｐ＋型層７７間の距離ｄを十分大きく
とることが必要である。具体的に例えば、６００Ｖの耐
圧を得るためには、およそｄ＝４５μｍが必要である。In this diode, when a reverse bias is applied between the anode and the cathode, the depletion layer changes from the n+ type layer 78 to the p- type layer 74.
Extends to the side. If the reverse bias is increased until the tip of the depletion layer reaches the p+ type layer 77, punch-through occurs. Therefore, in order to make the breakdown voltage of this diode sufficiently high, it is necessary to make the distance d between the n+ type layer 78 and the p+ type layer 77 sufficiently large. Specifically, for example, in order to obtain a breakdown voltage of 600V, approximately d=45 μm is required.

このようにｐ−型層７４の厚みを大きくすると、素子分
離のための溝もそれだけ深くすることが必要になり、特
に横方向の誘電体分離を行うことが困難になる。When the thickness of the p-type layer 74 is increased in this manner, the groove for element isolation also needs to be made deeper, making it particularly difficult to perform dielectric isolation in the lateral direction.

第１８図は、第１７図の構造において、ｐ＋型層７７を
省略したものである。このようにすれば電流容量が小さ
くなるが、耐圧は第１７図のものに比べて少し高くなる
。しかしこの構造でも、ｐ−型層７４の厚みが十分大ぎ
くなげればやはり十分な高耐圧は得られない。何故なら
、カソード・アノード間に逆バイアスが印加されて空乏
層がｐ−型Ｈ７４の底部酸化膜７２に達すると、それ以
上空乏層は伸びられない。基板７１は通常ＯＶであるか
ら、カソード・アノード間電圧はｐ−型層７４に生じた
空乏層と酸化膜７２にかかるが、酸化膜７２はｐ−型層
７４に比べると薄くしかも誘電率が高いので、殆どの電
圧は空乏層にかかる。従って第１７図と同じ耐圧を得る
ためには、ｐ−型層７４は第１１図の場合とほぼ同じ厚
みを必要とするのである。またｐ−型層７４が完全に空
乏化した時に表面のｎ”型層７９が空乏化せずに残る状
態があると、この表面部でｎ−型層７９とｐ＋型層８０
の間で容易にパンチスルーを生じる。FIG. 18 shows the structure of FIG. 17 with the p+ type layer 77 omitted. If this is done, the current capacity will be reduced, but the withstand voltage will be slightly higher than that of FIG. 17. However, even with this structure, if the thickness of the p-type layer 74 is reduced sufficiently, a sufficiently high breakdown voltage cannot be obtained. This is because when a reverse bias is applied between the cathode and the anode and the depletion layer reaches the bottom oxide film 72 of the p-type H74, the depletion layer cannot be extended any further. Since the substrate 71 is normally OV, the cathode-anode voltage is applied to the depletion layer generated in the p-type layer 74 and the oxide film 72, but the oxide film 72 is thinner than the p-type layer 74 and has a dielectric constant. Since it is high, most of the voltage is applied to the depletion layer. Therefore, in order to obtain the same breakdown voltage as in FIG. 17, the p-type layer 74 needs to have approximately the same thickness as in the case of FIG. 11. Furthermore, if the n'' type layer 79 on the surface remains undepleted when the p- type layer 74 is completely depleted, the n- type layer 79 and the p+ type layer 8
Punch-through easily occurs between the two.

（発明が解決しようとする問題点） 以上のように従来の誘電体分離構造の半導体素子では、
十分な高耐圧化を図るためには空乏層が伸びる高抵抗半
導体層を十分に厚くすることが必要となり、そうすると
素子分離が技術的に難しくなる、という問題があった。(Problems to be Solved by the Invention) As described above, in the conventional semiconductor element with the dielectric isolation structure,
In order to achieve a sufficiently high breakdown voltage, it is necessary to make the high-resistance semiconductor layer in which the depletion layer extends sufficiently thick, which poses a problem in that element isolation becomes technically difficult.

本発明は、この様な問題を解決した、誘電体分離構造の
高耐圧半導体素子を提供することを目的とする。An object of the present invention is to provide a high-voltage semiconductor element with a dielectric isolation structure that solves these problems.

［発明の構成］ （問題点を解決するための手段） 本発明は、絶縁体膜で下地半導体基板から分離された高
抵抗の第１の半導体層の表面に第１導電型で高不純物濃
度の第２の半導体層が形成され、この第２の半導体層の
周囲に連続してまたは近接して第１導電型で低不純物濃
度の第３の半導体層が形成され、この第３の半導体層か
ら所定路１ｌＩＩ１１れてこれを取囲むように第２導電
型で高不純物濃度の第４の半導体層が形成された素子に
おいて、前記第１の半導体層の底部に低不純物濃度の第
５の半導体層を設けたことを特徴とする。[Structure of the Invention] (Means for Solving the Problems) The present invention provides a first conductivity type high impurity concentration layer on the surface of a high resistance first semiconductor layer separated from a base semiconductor substrate by an insulating film. A second semiconductor layer is formed, a third semiconductor layer of the first conductivity type and a low impurity concentration is formed continuously or in close proximity to the second semiconductor layer, and from the third semiconductor layer In the device in which a fourth semiconductor layer of a second conductivity type and a high impurity concentration is formed to surround a predetermined path 1lII11, a fifth semiconductor layer of a low impurity concentration is formed at the bottom of the first semiconductor layer. It is characterized by having the following.

（作用） 本発明の素子では、第２．第４の半導体層間に逆バイア
ス電圧を印加した時、第１の半導体層と第３および第５
の半導体層に空乏層が伸びる。(Function) In the element of the present invention, the second. When a reverse bias voltage is applied between the fourth semiconductor layer and the third and fifth semiconductor layers,
A depletion layer extends into the semiconductor layer.

素子の上から見て第３の半導体層と第５の半導体層が重
なる領域についてそれぞれの単位面積当りの不純物総量
を路間−とし、その値が例えば３×１０１２／ｃｔｔｒ
２以下となるようにそれぞれの不純物濃度を設定してお
けば、この第３の半導体層および第５の半導体層は同時
に空乏化する。そしてこのとき第２の半導体層と第４の
半導体層間に印加した電圧は完全空乏化した第１．第３
および第５の半導体層によって縦方向および横方向に分
担される。従って、第１の半導体層の厚み方向に印加電
圧のほぼ全てがかかる従来構造の場合と異なり、第１の
半導体層が薄い場合であっても最大電界をアバランシェ
・ブレークダウンが起こらない値以下に抑えることがで
きる。The total amount of impurities per unit area in the region where the third semiconductor layer and the fifth semiconductor layer overlap when viewed from the top of the device is defined as -, and the value is, for example, 3 x 1012/cttr.
If the respective impurity concentrations are set to be 2 or less, the third semiconductor layer and the fifth semiconductor layer are depleted at the same time. At this time, the voltage applied between the second semiconductor layer and the fourth semiconductor layer is applied to the fully depleted first semiconductor layer. Third
and a fifth semiconductor layer in the vertical and horizontal directions. Therefore, unlike the conventional structure in which almost all of the applied voltage is applied in the thickness direction of the first semiconductor layer, even when the first semiconductor layer is thin, the maximum electric field is kept below a value that does not cause avalanche breakdown. It can be suppressed.

もし、第１．第３の半導体層が完全に空乏化しても、第
５の半導体層が完全に空乏しないと、従来の第１７図の
素子と本質的に変わらないことになる。また、第１．第
５の半導体層が完全に空乏化しても第３の半導体層が完
全に空乏化しない場合には、従来の第１８図の素子と本
質的に変わらないことになる。従って本発明は、上述の
ように逆バイアスした時に第３に半導体層と第５の半導
体層が同時に空乏化するような低濃度の第５の半導体層
を第１の半導体層の底部に挿入したものと云うことがで
きる。これにより本発明では、誘電体分離構造の素子の
高耐圧化が図られる。また従来と同程度の耐圧で良い場
合に、第１の半導体層の厚みを薄くすることができ、従
って素子分離が容易になる。If 1st. Even if the third semiconductor layer is completely depleted, unless the fifth semiconductor layer is completely depleted, the device is essentially the same as the conventional device shown in FIG. 17. Also, 1st. If the fifth semiconductor layer is completely depleted but the third semiconductor layer is not completely depleted, the device is essentially the same as the conventional device shown in FIG. 18. Therefore, in the present invention, a low concentration fifth semiconductor layer is inserted at the bottom of the first semiconductor layer so that the third semiconductor layer and the fifth semiconductor layer are simultaneously depleted when reverse biased as described above. It can be said that it is a thing. As a result, in the present invention, it is possible to increase the breakdown voltage of an element having a dielectric isolation structure. Furthermore, if the same level of breakdown voltage as the conventional one is sufficient, the thickness of the first semiconductor layer can be made thinner, and element isolation becomes easier.

（実施例） 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.

第１図は一実施例の高耐圧ダイオードである。FIG. 1 shows an example of a high voltage diode.

１はｎ＋型３ｉ基板であり、この上に酸化膜２により基
板１から分離され、酸化膜３により横方向に他の素子領
域から分離された島状の高抵抗シリコン層４（第１の半
導体層）が形成されている。Reference numeral 1 designates an n+ type 3i substrate, on which an island-shaped high-resistance silicon layer 4 (first semiconductor layer) is formed.

この高抵抗シリコン層４は、不純物濃度が十分に低いｐ
−一型またはｎ−一型である。素子分離領域には多結晶
シリコン膜５が埋め込まれている。This high resistance silicon layer 4 has a sufficiently low impurity concentration.
-type 1 or n-type. A polycrystalline silicon film 5 is embedded in the element isolation region.

高抵抗シリコン層４の表面中央部にカソード領域となる
高不純物濃度のｎ＋型層６（第２の半導体層）が形成さ
れている。ｎ＋型層６の周囲にはこれと連続的に、エツ
ジ・ブレークダウンを防止するためのガードリングとな
るｎ−型層７（第３の半導体層）が拡散形成されている
。ｐ−型層４の周辺部には、アノード電極を取り出すた
めの高不純物濃度のｐ＋型層８．９（第４の半導体層）
が拡散形成されている。高抵抗シリコン層４の底部には
酸化膜２に接して低不純物濃度のｐ−型層１０（第５の
半導体層）が薄く形成されている。At the center of the surface of the high-resistance silicon layer 4, an n+ type layer 6 (second semiconductor layer) with a high impurity concentration and serving as a cathode region is formed. Continuously surrounding the n+ type layer 6, an n- type layer 7 (third semiconductor layer) serving as a guard ring for preventing edge breakdown is formed by diffusion. A p+ type layer 8.9 (fourth semiconductor layer) with a high impurity concentration is formed around the p- type layer 4 to take out the anode electrode.
is formed by diffusion. At the bottom of the high-resistance silicon layer 4, a thin p-type layer 10 (fifth semiconductor layer) with a low impurity concentration is formed in contact with the oxide film 2.

ｐ−型層１０およびｎ−型層７はその単位面積当たりの
不純物総量が好ましくは０．１〜３×１０１２／ｃ＃＋
２に設定されている。ｐ＋型層８には第１の電極１１が
、ｎ４″型層６には第２の電極１２がそれぞれ形成され
ている。The p-type layer 10 and the n-type layer 7 preferably have a total amount of impurities per unit area of 0.1 to 3×10 12 /c#+
It is set to 2. A first electrode 11 is formed on the p+ type layer 8, and a second electrode 12 is formed on the n4'' type layer 6.

このダイオードを製造するには先ず、ｎ＋型シリコン基
板１と高抵抗シリコン層４に対応する高抵抗シリコン基
板とを直接接着技術を用いて貼り合わせる。即ち２枚の
基板を鏡面研磨しておき、その研磨面同士を清浄な雰囲
気下で密着させ、所定の熱処理を加えることにより一体
化する。この際、高抵抗シリコン基板の接着面には予め
ｐ−型層１０を形成しておき、また少なくとも一方の基
板の接着面に予め酸化膜２を形成しておくことにより、
図のように基板１と電気的に分離され、底部にｎ−型層
１０が形成された高抵抗シリコン層４が得られる。次に
フォトエツチングにより素子分離溝を形成し、島状に分
離されたｐ−型層４の側面にｐ＋型層９を拡散形成し、
また酸化膜３を形成する。そして分離溝内に多結晶シリ
コン膜５を埋め込んだ後、ｎ＋型層６、ｎ−型層７およ
びｐ＋型層８を拡散形成し、電極１１．１２を形成する
。To manufacture this diode, first, an n+ type silicon substrate 1 and a high resistance silicon substrate corresponding to the high resistance silicon layer 4 are bonded together using a direct bonding technique. That is, two substrates are mirror-polished, the polished surfaces are brought into close contact with each other in a clean atmosphere, and a predetermined heat treatment is applied to integrate them. At this time, a p-type layer 10 is formed in advance on the bonding surface of the high-resistance silicon substrate, and an oxide film 2 is formed in advance on the bonding surface of at least one of the substrates.
As shown in the figure, a high-resistance silicon layer 4 is obtained which is electrically isolated from the substrate 1 and has an n-type layer 10 formed at its bottom. Next, an element isolation trench is formed by photoetching, and a p+ type layer 9 is diffused and formed on the side surface of the island-shaped p- type layer 4.
Further, an oxide film 3 is formed. After burying a polycrystalline silicon film 5 in the isolation trench, an n+ type layer 6, an n- type layer 7, and a p+ type layer 8 are formed by diffusion to form electrodes 11 and 12.

このように構成されたダイオードにおいて、第１の電極
１１と第２の電極１２間に逆バイアスを印加すると、ま
ず素子表面中央のｎ＋型層６から高抵抗シリコン層４内
に縦方向に空乏層が拡がる。In the diode configured in this way, when a reverse bias is applied between the first electrode 11 and the second electrode 12, a depletion layer is first formed in the vertical direction from the n+ type layer 6 at the center of the element surface into the high resistance silicon layer 4. expands.

高抵抗シリコン層４の厚みおよびｐ−型層１０の不純物
濃度が適当な値に設定されていれば、シリコン層４が完
全空乏化してもその最大電界がアバランシェ・ブレーク
ダウンを生じる値以下に収まり、やがて底部のｐ−型層
１０が空乏化する。そしてｐ−型層１０が空乏化すると
、電極１１の電位が電極１２の直下までは伝わらなくな
る。即ち空乏化したｐ−型層１０内に横方向に電位差が
生じ、結局電極１１．１２間の電圧が高抵抗シリコン層
４の厚み方向とρ−型層１０の横方向に分担される。こ
のことは換言すれば、素子の印加電圧の一部が分離用酸
化膜２により有効に分担されるものと言える。これによ
りこのダイオードは、シリコン層４がそれ程厚いもので
なくても十分な高耐圧特性を示す。また高抵抗シリコン
層４を薄くし°Ｃ１図のような誘電体分離構造の形成工
程を容易にすることができる。If the thickness of the high-resistance silicon layer 4 and the impurity concentration of the p-type layer 10 are set to appropriate values, even if the silicon layer 4 is completely depleted, its maximum electric field will remain below the value that causes avalanche breakdown. , the bottom p-type layer 10 eventually becomes depleted. When the p-type layer 10 is depleted, the potential of the electrode 11 is no longer transmitted directly below the electrode 12. That is, a potential difference is generated in the lateral direction in the depleted p-type layer 10, and the voltage between the electrodes 11 and 12 is eventually shared in the thickness direction of the high-resistance silicon layer 4 and in the lateral direction of the ρ-type layer 10. In other words, it can be said that a part of the voltage applied to the element is effectively shared by the isolation oxide film 2. As a result, this diode exhibits sufficiently high breakdown voltage characteristics even if the silicon layer 4 is not very thick. Furthermore, by making the high-resistance silicon layer 4 thinner, the process of forming a dielectric isolation structure as shown in FIG. 1 can be facilitated.

第２図は、第１図の素子部の導電型を第１図とは逆にし
た例である。酸化膜２．３により分離された高抵抗シリ
コン層２１の表面中央部にｐ＋型層２２が形成され、そ
の周囲にｐ−型層２３が形成され、周辺部にｎ＋型［１
２４，２５が形成されている。ｎ＋型層２４には第１の
電極２６が、ｐ＋型層２２には第２の電極２７がそれぞ
れ形成されてダイオードが構成されている。そして高抵
抗シリコン層２１の底部の酸化膜２に接する部分にｎ−
型層２８が形成されている。この実施例のダイオードも
先の実施例と全く同様に高耐圧特性を示す。FIG. 2 is an example in which the conductivity type of the element portion in FIG. 1 is reversed from that in FIG. A p+ type layer 22 is formed at the center of the surface of the high-resistance silicon layer 21 separated by an oxide film 2.3, a p- type layer 23 is formed around it, and an n+ type [1
24 and 25 are formed. A first electrode 26 is formed on the n+ type layer 24, and a second electrode 27 is formed on the p+ type layer 22, forming a diode. Then, the n-
A mold layer 28 is formed. The diode of this embodiment also exhibits high breakdown voltage characteristics, just like the previous embodiment.

第３図は、他の誘電体分離構造による実施例のダイオー
ドである。この実施例では多結晶シリコン層３１の表面
部に酸化膜３２により分離された構造のｎ”−型または
ｐ−一部の高抵抗シリコン層３３が形成され、このシリ
コン層３３表面中央部にｐ＋型層３４が形成され、その
周囲にｐ−型層３５が形成されてダイオードが構成され
ている。FIG. 3 shows an example diode with another dielectric isolation structure. In this embodiment, an n''-type or p-part high resistance silicon layer 33 having a structure separated by an oxide film 32 is formed on the surface of a polycrystalline silicon layer 31, and a p+ A type layer 34 is formed, and a p-type layer 35 is formed around it to constitute a diode.

ｎ−型層３３の周辺部にｎ＋型層３６を設けてこれに第
１の電極３９が、またｐ＋型層３４に第２の電極３８が
それぞれ形成されている。そして高抵抗シリコン層３３
の底部および側部の酸化膜３２に接する部分にｎ−型層
３７が形成されている。An n + -type layer 36 is provided around the n - -type layer 33 and a first electrode 39 is formed thereon, and a second electrode 38 is formed on the p + -type layer 34 . and high resistance silicon layer 33
An n-type layer 37 is formed on the bottom and side portions of the oxide film 32 in contact with the oxide film 32 .

この実施例の場合も、ｎ−型層３７を設けたことにより
、高耐圧化が図られる。In this embodiment as well, by providing the n-type layer 37, high breakdown voltage can be achieved.

第４図は、本発明をＭＯＳトランジスタに適用した実施
例である。３ｉ基板４１に酸化膜４２゜４３により分離
された島状のｎ−一型高抵抗シリコン層４４（第１の半
導体層）が形成され、分離領域の溝には多結晶シリコン
膜５４が埋め込まれている。この素子分離構造は第１図
のそれと同じである。高抵抗シリコン層４４の表面中央
部にドレイン領域となるｐ＋型層４５（第２の半導体層
）およびｐ−型層４６が形成され、その周囲にチャネル
領域となるｎ型層４７（第４の半導体層）が形成され、
このｎ型層４７内にソース領域となるｐ＋型層４８が形
成されている。周辺部のｐ＋型層４８およびｎ型層４７
にはソース電極である第１の電極５２が、中央部のｐ＋
型層４５にはドレイン電極である第２の電極５３がそれ
ぞれ形成されている。ｐ１型層４８とｐ−型層４６の間
のｎ型層４７表面部にゲート絶縁膜５０を介してグー、
ト電極５１が形成されている。高抵抗シリコン層４４の
底部の酸化膜４２と接する部分にｎ−型層４９（第５の
半導体層）が形成されている。FIG. 4 shows an embodiment in which the present invention is applied to a MOS transistor. An island-shaped n-1 type high-resistance silicon layer 44 (first semiconductor layer) separated by oxide films 42 and 43 is formed on a 3i substrate 41, and a polycrystalline silicon film 54 is embedded in the trench of the isolation region. ing. This element isolation structure is the same as that shown in FIG. A p+ type layer 45 (second semiconductor layer) and a p- type layer 46, which will become a drain region, are formed in the center of the surface of the high-resistance silicon layer 44, and an n-type layer 47 (fourth semiconductor layer), which will become a channel region, is formed around them. semiconductor layer) is formed,
A p+ type layer 48 serving as a source region is formed within this n type layer 47. P+ type layer 48 and n type layer 47 in the peripheral area
The first electrode 52, which is a source electrode, is connected to the p+
A second electrode 53 serving as a drain electrode is formed on each of the mold layers 45 . A goo is formed on the surface of the n-type layer 47 between the p1-type layer 48 and the p-type layer 46 via the gate insulating film 50.
A top electrode 51 is formed. An n − type layer 49 (fifth semiconductor layer) is formed at the bottom of the high-resistance silicon layer 44 in a portion that is in contact with the oxide film 42 .

この実施例のＭＯＳトランジスタにおいて、ドレイン電
極である第２の電極５３にソース電極である第１の電極
５２よりも低い電圧が印加された時、その電圧は、素子
中央部のｐ＋型層４５から高抵抗シリコン層４４内に伸
びる空乏層および完全空乏化するｎ−型層４９により分
担される。この結果この実施例でも、やはり高耐圧化が
図られる。In the MOS transistor of this embodiment, when a lower voltage is applied to the second electrode 53, which is the drain electrode, than to the first electrode 52, which is the source electrode, the voltage is applied from the p+ type layer 45 at the center of the element. It is shared by a depletion layer extending into the high resistance silicon layer 44 and a fully depleted n-type layer 49. As a result, this embodiment also achieves high breakdown voltage.

第５図は、本発明をｎチャネルＭｏＳトランジスタに適
用した実施例である。第４図の実施例と同様の素子分離
構造を持つｎ−一型高抵抗シリコン層４４（第１の半導
体層）を用いている。このシリコン層４４の中央部にチ
ャネル領域となるｎ型層５６（第２の半導体層）が形成
され、このｎ型層５６内にソース領域となるｎ＋型層５
７が形成されている。ｎ型層５６のｎ＋型層５７とシリ
コン層４４の間にゲート絶縁膜５０を介してゲート電極
５１が形成されている。ｎ型層５６から僅かな距離離れ
てゲート電極５１下のシリコン層４４表面にｐ−型層５
８（第３の半導体層）が形成されている。シリコン層４
４の周辺部にはドレイン領域となるｎ＋型層５９．６０
（第４の半導体層）が形成されている。ｎ＋型層５９に
はドレイン電極である第１の電極６１が、ｐ型層５６お
よびｎ＋型層５７にはソース電極となる第２の電極６２
が、それぞれ形成されている。そして高抵抗シリコン層
４４の底部の酸化膜４２に接する領域に先の実施例と同
様、ｎ−型層４９（第５の半導体層）が形成されている
。FIG. 5 shows an embodiment in which the present invention is applied to an n-channel MoS transistor. An n-1 type high resistance silicon layer 44 (first semiconductor layer) having an element isolation structure similar to that of the embodiment shown in FIG. 4 is used. An n-type layer 56 (second semiconductor layer) that becomes a channel region is formed in the center of this silicon layer 44, and an n+-type layer 5 that becomes a source region is formed within this n-type layer 56.
7 is formed. A gate electrode 51 is formed between the n+ type layer 57 of the n type layer 56 and the silicon layer 44 with a gate insulating film 50 interposed therebetween. A p-type layer 5 is formed on the surface of the silicon layer 44 under the gate electrode 51 at a short distance from the n-type layer 56.
8 (third semiconductor layer) is formed. silicon layer 4
4, there is an n+ type layer 59.60 which becomes the drain region.
(fourth semiconductor layer) is formed. A first electrode 61 serving as a drain electrode is provided on the n+ type layer 59, and a second electrode 62 serving as a source electrode is provided on the p type layer 56 and n+ type layer 57.
are formed respectively. As in the previous embodiment, an n-type layer 49 (fifth semiconductor layer) is formed in the region at the bottom of the high-resistance silicon layer 44 in contact with the oxide film 42.

このＭＯＳトランジスタは、第１の電極６１に、第２の
電極６２に対して正となるドレイン電圧を印加して動作
させる。ゲート電圧が零または正でｐ型層５６にチャネ
ルが形成されないオフ状態では、ｐ型層５６から伸びる
空乏層は容易にｐ−型層５８に達する。即ちｐ−型層５
８はｐ型層５６に直接接していないが、先の各実施例の
ガードリングと同様のガードリングとして働く。そして
トレイン・ソース間の電圧は空乏化したシリコン層４４
．５８およびｎ−型層４９により縦方向と横方向に分担
されるため、高耐圧特性が得られる。This MOS transistor is operated by applying a drain voltage that is positive with respect to the second electrode 62 to the first electrode 61. In an off state where the gate voltage is zero or positive and no channel is formed in the p-type layer 56, the depletion layer extending from the p-type layer 56 easily reaches the p-type layer 58. That is, p-type layer 5
8 is not in direct contact with the p-type layer 56, but serves as a guard ring similar to the guard ring in each of the previous embodiments. And the voltage between the train and source is the depleted silicon layer 44.
．． 58 and the n-type layer 49 in the vertical and horizontal directions, high breakdown voltage characteristics can be obtained.

第６図は、第１図を僅かに変形した実施例であり、第１
図の構造におけるｐ−型層１０と酸化膜２の界面に高抵
抗膜７０、例えば１０８Ω・ｃｍ以上の高抵抗膜例えば
多結晶シリコン膜 （ＳＩＰＯ８）を配置している。第７図は同様に第２図
の構造においてｎ−型層２８と酸化膜２の界面に高抵抗
膜７０を配置したものである。この様な構成とすれば、
基板１の電位の影響が低減される。即ち高抵抗膜に高電
位側から低電位側に微小な電流が流れて電位勾配が形成
され、外部電界がしゃ断できる。また酸化膜２と基板１
と高抵抗膜７０がキャパシタを構成するため、酸化膜２
に高電圧を分担させることができる。FIG. 6 is a slightly modified embodiment of FIG.
A high resistance film 70, for example, a high resistance film of 10 8 Ω·cm or more, such as a polycrystalline silicon film (SIPO 8), is disposed at the interface between the p − type layer 10 and the oxide film 2 in the structure shown in the figure. Similarly, FIG. 7 shows a structure in which a high resistance film 70 is disposed at the interface between the n-type layer 28 and the oxide film 2 in the structure shown in FIG. With this kind of configuration,
The influence of the potential of the substrate 1 is reduced. That is, a minute current flows through the high-resistance film from the high-potential side to the low-potential side, forming a potential gradient and cutting off the external electric field. In addition, the oxide film 2 and the substrate 1
Since the oxide film 2 and the high resistance film 70 constitute a capacitor, the oxide film 2
can share the high voltage.

第８図は、第２図の実施例において横方向の素子分離を
ｐｎ接合分離構造とした実施例である。FIG. 8 shows an embodiment in which the lateral element isolation in the embodiment of FIG. 2 is made into a pn junction isolation structure.

高抵抗シリコン層２１がｐ−一型層の場合、図示のよう
に表面から酸化膜２に達する深さのｎ＋型層２５により
横方向の素子分離が行われる。第９図は高抵抗シリコン
層２１をｒＭ−型とした場合の横方向のｐｎ接合分離構
造である。図示のように素子間に分離用のｐ＋型層９１
が必要である。When the high-resistance silicon layer 21 is a p-type layer, lateral element isolation is performed by the n+-type layer 25 having a depth from the surface to the oxide film 2 as shown in the figure. FIG. 9 shows a lateral pn junction isolation structure when the high-resistance silicon layer 21 is of rM-type. As shown in the figure, a p+ type layer 91 for isolation between elements.
is necessary.

ｐ＋型層の周囲には高電界がかからないようにするため
ｐ−型層９２が形成されている。第９図において、酸化
膜２に達するｎ＋型層２５は必ずしも必要ではない。第
１図その他の実施例についても、横方向についてはｐｎ
接合分離造とすることができ、その場合も本発明は有効
である。A p- type layer 92 is formed around the p+ type layer to prevent a high electric field from being applied. In FIG. 9, the n+ type layer 25 reaching the oxide film 2 is not necessarily necessary. Regarding the other embodiments in FIG. 1, the horizontal direction is pn.
The present invention is also effective in this case.

第１０図は、第２図の構造を基本とし、そのアノード部
分を複数個に分割配置した実施例である。FIG. 10 shows an embodiment based on the structure shown in FIG. 2, in which the anode portion is divided into a plurality of parts.

この構造は、素子面積が大きい場合に、アノード電流を
均一に分散させ上で有効である。この実施例においても
、第２図の実施例と同様、ｎ−型層２８を設けることに
より高耐圧化が図られる。This structure is effective in uniformly distributing the anode current when the device area is large. In this embodiment as well, as in the embodiment shown in FIG. 2, high breakdown voltage can be achieved by providing the n-type layer 28.

以上の実施例では全て、第３の半導体層と第５の半導体
層を逆導電型とした。これに対し、第５の半導体層を第
３の半導体層と同じ導電型とすることも可能である。そ
の様な実施例を以下に示す。In all of the above embodiments, the third semiconductor layer and the fifth semiconductor layer were of opposite conductivity type. On the other hand, it is also possible to make the fifth semiconductor layer the same conductivity type as the third semiconductor layer. Such an example is shown below.

第１１図は、第１図の構造において、高抵抗シリコン層
４をｐ−一型とし、その底部に設ける低濃度層をｎ−型
層１０′とした実施例である。この構造においても、ｎ
−型層１０′の不純物総量は０、１〜３Ｘ　１０”　２
／ｒ、第２に設定される。FIG. 11 shows an embodiment in which, in the structure of FIG. 1, the high-resistance silicon layer 4 is of p-type, and the low concentration layer provided at the bottom thereof is an n-type layer 10'. Also in this structure, n
- The total amount of impurities in the type layer 10' is 0.1 to 3X 10''2
/r, set second.

この実施例によっても、高耐圧化が図られる。This embodiment also achieves high breakdown voltage.

この素子構造の場合、耐圧向上の理由を次のように説明
することもできる。この構造では、アノード・カソード
間に、ｐ＋型層８．９−ｎ−型層ｉｏ’−ｐ−−型高抵
抗シリコン層４−ｎ＋型層６というｐｎｐｎ構造が形成
される。この素子に逆バイアスを与えると、中央のｎ＋
型層６から高抵抗シリコン層４内に縦方向に空乏層が伸
びると同時に、周辺のｐ＋型層８からｎ−型層１０′な
いに横方向に空乏層が伸びる。その結果として第１図の
実施例と同様に、アノード・カソード間電圧はシリコン
層４に伸びる空乏層とｎ−型層１０′に伸びる空乏層に
より分担され、シリコン層４にのみ高電界がかかるのが
防止される。In the case of this element structure, the reason for the improvement in breakdown voltage can also be explained as follows. In this structure, a pnpn structure including a p+ type layer 8, 9, an n- type layer io', a p-- type high resistance silicon layer 4, and an n+ type layer 6 is formed between the anode and the cathode. When a reverse bias is applied to this element, the central n+
A depletion layer extends vertically from the type layer 6 into the high-resistance silicon layer 4, and at the same time, a depletion layer extends laterally from the peripheral p+ type layer 8 to the n- type layer 10'. As a result, similar to the embodiment shown in FIG. 1, the anode-cathode voltage is shared between the depletion layer extending to the silicon layer 4 and the depletion layer extending to the n-type layer 10', and a high electric field is applied only to the silicon layer 4. is prevented.

第１２図は、第２図の構造において、シリコン層２１を
ｎ−一型とし、その底部の低濃度層をｐ−型層２８′と
した実施例である。第１３図は、第３図の構造における
ｎ−型層３７をｐ−型層３７′とした実施例である。第
１４図は、第４図の構造におけるｎ−型層４９をｐ−型
層４９′とした実施例である。第１５図は、第１４図の
構造を若干変更し、ドレイン・ソース間にｐｎｐｎ構造
を導入して導電変調型ＭＯ８ＦＥＴを構成した実施例で
ある。FIG. 12 shows an embodiment in which, in the structure of FIG. 2, the silicon layer 21 is of n-type and the low concentration layer at the bottom thereof is a p-type layer 28'. FIG. 13 shows an embodiment in which the n-type layer 37 in the structure of FIG. 3 is replaced with a p-type layer 37'. FIG. 14 shows an embodiment in which the n-type layer 49 in the structure of FIG. 4 is replaced with a p-type layer 49'. FIG. 15 shows an embodiment in which the structure of FIG. 14 is slightly modified and a pnpn structure is introduced between the drain and the source to form a conductivity modulation type MO8FET.

第１６図は、第５図の構造におけるｎ−型層４９をｐ−
型層４９′とした実施例である。これら第１２図〜第１
６図の実施例によっても同様に高耐圧化が図られている
。FIG. 16 shows that the n-type layer 49 in the structure of FIG.
This is an embodiment in which a mold layer 49' is used. These Figures 12-1
The embodiment shown in FIG. 6 also achieves high voltage resistance.

［発明の効果］ 以上述べたように本発明によれば、絶縁体膜で分離され
た十分に不純物濃度が低い高抵抗の第１の半導体層の表
面に第１導電型の第２の半導体層を有し、その周囲に第
１導電型で低濃度の第３の半導体層を有し、更にその外
側に第２ｓ電型で高濃度の第４の半導体層を有する誘電
体分離構造の半導体素子において、素子底部の絶縁体膜
に隣接する部分に低不純物濃度の第５の半導体層を設け
て、この第３の半導体層により素子の逆バイアス印加電
圧の一部を分離絶縁膜に負担させることにより、第１の
半導体層が薄いものであっても十分な高耐圧特性を得る
ことが可能になる。また第１の半導体層が薄くてもよい
結果、誘電体分離構造の形成が容易になる。[Effects of the Invention] As described above, according to the present invention, the second semiconductor layer of the first conductivity type is formed on the surface of the first semiconductor layer of high resistance with sufficiently low impurity concentration separated by an insulating film. A semiconductor element having a dielectric separation structure, having a third semiconductor layer of a first conductivity type and a low concentration around it, and further having a fourth semiconductor layer of a second conductivity type and a high concentration outside the third semiconductor layer. In this method, a fifth semiconductor layer with a low impurity concentration is provided at a portion adjacent to the insulating film at the bottom of the element, and this third semiconductor layer causes the isolation insulating film to bear part of the reverse bias voltage applied to the element. This makes it possible to obtain sufficiently high breakdown voltage characteristics even if the first semiconductor layer is thin. Furthermore, since the first semiconductor layer may be thin, the dielectric isolation structure can be easily formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例のダイオードを示す図、第２
図は各部の導電型を逆にした他の実施例のダイオードを
示す図、第３図は他の誘電体分離構造を用いた実施例の
ダイオードを示す図、第４図はｎチャネルＭＯＳトラン
ジスタに適用した実施例を示す図、第５図はｎチャネル
ＭＯＳトランジスタに適用した実施例を示す図、第６図
および第７図はそれぞれ第１図および第２図の実施例を
変形した実施例を示す図、第８図および第９図は横方向
素子分離をｐｎ接合分離とした実施例のダイオードを示
す図、第１０図は分割アノード構造の実施例のダイオー
ドを示す図、第１１図は第１図の構成を変形した実施例
を示す図、第１２図は第２図の構成を変形した実施例を
示す図、第１３図は第３図の構成を変形した実施例を示
す図、第１４図は第４図の構成を変形した実施例を示す
図、第１５図は第１４図の構成を変形した導電変調型Ｍ
Ｏ８ＦＥＴの実施例を示す図、第１６図は第５図の構成
を変形した実施例を示す図、第１７図および第１８図は
従来の誘電体分離構造のダイオードを示す図である。 １・・・基板、２．３・・・酸化膜、４・・・高抵抗シ
リコン層（第１の半導体層）、５・・・多結晶シリコン
膜、６・・・ｎ＋型層（第２の半導体層）、７・・・ｎ
−型層（第３の半導体層）、８・・・ｐ＋型層（第４の
半導体層）、９・・・ｐ＋型層、１０・・・ｎ−型層（
第５の半導体層）、１１・・・第１の電極（アノード電
極）、１２・・・第２の電極（カソード電極）、２１・
・・高抵抗シリコン層（第１の半導体層）、２２・・・
ｐ＋型層（第２の半導体層）、２３・・・ｐ−型層（第
３の半導体層）、２４・・・ｎ＋型層（第４の半導体層
）、２５・・・ｎ＋型層、２６・・・第１の電極（カソ
ード電極）、２７・・・第２の電極（アノード電極）、
２８・・・ｐ−型層（第５の半導体層）、３１・・・多
結晶シリコン層、３２・・・酸化膜、３３・・・高抵抗
シリコン層（第１の半導体層）、３４・・・ｐ＋型層（
第２の半導体層）、３５・・・ｐ−型層（第３の半導体
層）、３６・・・ｎ＋型層（第４の半導体層）、３７・
・・ｐ−型層（第５の半導体層）、３８・・・第１の電
極（カソード電極）、３９・・・第２の電極（アノード
電極）、４１・・・基板、４２．４３・・・酸化膜、４
４・・・高抵抗シリコン層（第１の半導体層）、４５・
・・ｐ＋型層（第２の半導体層）、４６・・・ｐ−型層
（第３の半導体層）、４７・・・ｎ型層（チャネル領域
、第４の半導体層）、４８・・・ｐ＋型層、４９・・・
ｎ−型層（第５の半導体１）、５０・・・ゲート絶縁膜
、５１・・・ゲート電極、５２・・・第１の電極（ソー
ス電極）、５３・・・第２の電極（ドレイン電極）、５
４・・・多結晶シリコン膜、５５・・・ｎ＋型層、５６
・・・ｐ型層（第２の半導体層）、５７・・・ｎ＋型層
、５８・・・ｐ−型層（第３の半導体層）、５９・・・
ｎ＋型層（第４の半導体層）、６０・・・ｎ＋型層、６
１・・・・・・第１の電極（ドレイン電極）、６２・・
・第２の電極（ソース電極）。 出願人代理人　弁理士　鈴江武彦Figure 1 shows a diode according to an embodiment of the present invention, Figure 2 shows a diode according to an embodiment of the present invention.
The figure shows a diode of another embodiment in which the conductivity type of each part is reversed, Figure 3 shows a diode of an embodiment using another dielectric isolation structure, and Figure 4 shows an n-channel MOS transistor. 5 shows an example applied to an n-channel MOS transistor, and FIGS. 6 and 7 show an example modified from the example shown in FIGS. 1 and 2, respectively. 8 and 9 are diagrams showing a diode of an embodiment in which lateral element isolation is pn junction isolation, FIG. 10 is a diagram showing a diode of an embodiment with a split anode structure, and FIG. 12 is a diagram showing an embodiment in which the configuration of FIG. 2 is modified; FIG. 13 is a diagram showing an embodiment in which the configuration in FIG. 3 is modified; FIG. 14 is a diagram showing an embodiment in which the configuration of FIG. 4 is modified, and FIG. 15 is a diagram showing a conductive modulation type M in which the configuration of FIG. 14 is modified.
FIG. 16 is a diagram showing an embodiment of an O8FET, FIG. 16 is a diagram showing an embodiment modified from the configuration of FIG. 5, and FIGS. 17 and 18 are diagrams showing a diode having a conventional dielectric isolation structure. DESCRIPTION OF SYMBOLS 1...Substrate, 2.3...Oxide film, 4...High resistance silicon layer (first semiconductor layer), 5...Polycrystalline silicon film, 6...N+ type layer (second ), 7...n
- type layer (third semiconductor layer), 8...p+ type layer (fourth semiconductor layer), 9...p+ type layer, 10...n- type layer (
5th semiconductor layer), 11... first electrode (anode electrode), 12... second electrode (cathode electrode), 21...
...High resistance silicon layer (first semiconductor layer), 22...
p+ type layer (second semiconductor layer), 23... p- type layer (third semiconductor layer), 24... n+ type layer (fourth semiconductor layer), 25... n+ type layer, 26... first electrode (cathode electrode), 27... second electrode (anode electrode),
28...p-type layer (fifth semiconductor layer), 31...polycrystalline silicon layer, 32...oxide film, 33...high resistance silicon layer (first semiconductor layer), 34... ...p+ type layer (
35... p- type layer (third semiconductor layer), 36... n+ type layer (fourth semiconductor layer), 37...
...p-type layer (fifth semiconductor layer), 38... first electrode (cathode electrode), 39... second electrode (anode electrode), 41... substrate, 42.43. ...Oxide film, 4
4... High resistance silicon layer (first semiconductor layer), 45.
...p+ type layer (second semiconductor layer), 46...p- type layer (third semiconductor layer), 47...n type layer (channel region, fourth semiconductor layer), 48...・p+ type layer, 49...
n-type layer (fifth semiconductor 1), 50... gate insulating film, 51... gate electrode, 52... first electrode (source electrode), 53... second electrode (drain electrode), 5
4... Polycrystalline silicon film, 55... n+ type layer, 56
...p type layer (second semiconductor layer), 57...n+ type layer, 58...p− type layer (third semiconductor layer), 59...
n+ type layer (fourth semiconductor layer), 60... n+ type layer, 6
1...First electrode (drain electrode), 62...
- Second electrode (source electrode). Applicant's agent Patent attorney Takehiko Suzue

Claims (6)

【特許請求の範囲】[Claims] （１）絶縁体膜により下地半導体基板から分離された高
抵抗の第１の半導体層と、この第１の半導体層の表面に
選択的に形成された第１導電型で高不純物濃度の第２の
半導体層と、前記第１の半導体層表面の前記第２の半導
体層の周辺部に形成された第１導電型で低不純物濃度の
第３の半導体層と、前記第１の半導体層の前記第３の半
導体層から所定距離離れた位置に形成された第２導電型
で高不純物濃度の第４の半導体層とを有する高耐圧半導
体素子において、前記第１の半導体層の底部に低不純物
濃度の第５の半導体層を設けたことを特徴とする高耐圧
半導体素子。(1) A first semiconductor layer of high resistance separated from the base semiconductor substrate by an insulating film, and a second semiconductor layer of a first conductivity type and high impurity concentration selectively formed on the surface of this first semiconductor layer. a third semiconductor layer of a first conductivity type and a low impurity concentration formed in a peripheral portion of the second semiconductor layer on the surface of the first semiconductor layer; In a high voltage semiconductor element having a fourth semiconductor layer of a second conductivity type and a high impurity concentration formed at a predetermined distance from the third semiconductor layer, the bottom of the first semiconductor layer is doped with a low impurity concentration. A high breakdown voltage semiconductor device, characterized in that it is provided with a fifth semiconductor layer. （２）前記第１の半導体層が第１導電型または第２導電
型であり、前記第５の半導体層が第２導電型である特許
請求の範囲第１項記載の高耐圧半導体素子。(2) The high voltage semiconductor device according to claim 1, wherein the first semiconductor layer is of the first conductivity type or the second conductivity type, and the fifth semiconductor layer is of the second conductivity type. （３）前記第１の半導体層が第２導電型であり、前記第
５の半導体層が第１導電型である特許請求の範囲第１項
記載の高耐圧半導体素子。(3) The high voltage semiconductor device according to claim 1, wherein the first semiconductor layer is of the second conductivity type, and the fifth semiconductor layer is of the first conductivity type. （４）前記第３および第５の半導体層は単位面積当たり
の不純物総量が０．１〜３×１０＾１＾２／ｃｍ＾２で
ある特許請求の範囲第１項記載の高耐圧半導体素子。(4) The high voltage semiconductor device according to claim 1, wherein the third and fifth semiconductor layers have a total amount of impurities per unit area of 0.1 to 3×10^1^2/cm^2. . （５）前記第１の半導体層の周辺に素子分離絶縁体膜を
有する特許請求の範囲第１項記載の高耐圧半導体素子。(5) The high voltage semiconductor device according to claim 1, further comprising an element isolation insulating film around the first semiconductor layer. （６）前記第１の半導体層の周辺に素子分離ｐｎ接合を
有する特許請求の範囲第１項記載の高耐圧半導体素子。(6) The high voltage semiconductor device according to claim 1, which has an element isolation pn junction around the first semiconductor layer.
JP62293456A 1987-02-26 1987-11-20 High voltage semiconductor device Expired - Lifetime JP2896141B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP62-43564 1987-02-26
JP4356487 1987-02-26
JP18942087 1987-07-29
JP62-189420 1987-07-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP9012727A Division JP2860089B2 (en) 1987-02-26 1997-01-27 High voltage semiconductor device

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JPH01103851A true JPH01103851A (en) 1989-04-20
JP2896141B2 JP2896141B2 (en) 1999-05-31

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JP (1) JP2896141B2 (en)
DE (1) DE3806164A1 (en)
IT (1) IT1216464B (en)

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US5777365A (en) * 1995-09-28 1998-07-07 Nippondenso Co., Ltd. Semiconductor device having a silicon-on-insulator structure
JP2002543626A (en) * 1999-05-03 2002-12-17 − ハカン エクルンド、クラス Semiconductor element
US6531738B1 (en) 1999-08-31 2003-03-11 Matsushita Electricindustrial Co., Ltd. High voltage SOI semiconductor device
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US5374843A (en) * 1991-05-06 1994-12-20 Silinconix, Inc. Lightly-doped drain MOSFET with improved breakdown characteristics
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DE4233773C2 (en) * 1992-10-07 1996-09-19 Daimler Benz Ag Semiconductor structure for semiconductor devices with high breakdown voltage
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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994025989A1 (en) * 1993-04-28 1994-11-10 Harris Corporation An integrated circuit with improved reverse bias breakdown
JPH08139295A (en) * 1994-11-07 1996-05-31 Nec Corp Soi substrate
US5777365A (en) * 1995-09-28 1998-07-07 Nippondenso Co., Ltd. Semiconductor device having a silicon-on-insulator structure
JP2002543626A (en) * 1999-05-03 2002-12-17 − ハカン エクルンド、クラス Semiconductor element
USRE41368E1 (en) 1999-08-31 2010-06-08 Panasonic Corporation High voltage SOI semiconductor device
US6531738B1 (en) 1999-08-31 2003-03-11 Matsushita Electricindustrial Co., Ltd. High voltage SOI semiconductor device
JP2004207418A (en) * 2002-12-25 2004-07-22 Nippon Inter Electronics Corp Semiconductor device and its manufacturing method
JP2007088312A (en) * 2005-09-26 2007-04-05 Hitachi Ltd Semiconductor device
JP2008147690A (en) * 2008-01-15 2008-06-26 Mitsubishi Electric Corp High withstand voltage semiconductor device
JP2012191235A (en) * 2012-06-07 2012-10-04 Rohm Co Ltd Semiconductor device
JP2014086723A (en) * 2012-10-19 2014-05-12 Freescale Semiconductor Inc High voltage diode
WO2021085437A1 (en) * 2019-11-01 2021-05-06 株式会社東海理化電機製作所 Semiconductor integrated circuit
JP2021072426A (en) * 2019-11-01 2021-05-06 株式会社東海理化電機製作所 Semiconductor integrated circuit
US11973146B2 (en) 2019-11-01 2024-04-30 Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho Semiconductor integrated circuit
WO2021192800A1 (en) * 2020-03-23 2021-09-30 株式会社東海理化電機製作所 Semiconductor integrated circuit

Also Published As

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IT1216464B (en) 1990-03-08
IT8819563A0 (en) 1988-02-26
JP2896141B2 (en) 1999-05-31
DE3806164A1 (en) 1988-09-08
DE3806164C2 (en) 1991-03-14

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