JPS6038831A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6038831A
JPS6038831A JP14632783A JP14632783A JPS6038831A JP S6038831 A JPS6038831 A JP S6038831A JP 14632783 A JP14632783 A JP 14632783A JP 14632783 A JP14632783 A JP 14632783A JP S6038831 A JPS6038831 A JP S6038831A
Authority
JP
Japan
Prior art keywords
formed
surface
silicon
region
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14632783A
Inventor
Katsuhiko Ito
Kazuo Nojiri
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14632783A priority Critical patent/JPS6038831A/en
Publication of JPS6038831A publication Critical patent/JPS6038831A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Abstract

PURPOSE:To further upgrade a higher integration of the IC by a method wherein an isolation region in a grooved isolation structure, wherein no bird's beak is generated, is formed at a part, where high integration is needed, and a thick oxide film is formed at a wide region other than the isolation region in such a way as to interposed between the grooved isolation structures. CONSTITUTION:A silicon dioxide film 2 is formed on the surface of a P type silicon semiconductor substrate 1, and after a silicon nitriding film 3 was formed thereon, grooves 4 are formed and the surface is partitioned into numerous regions. In addition to an element forming region 5, a region 6, where no element is formed, is also included. After an embedding material 9 consisting of such an insulator as a silicon dioxide, etc., was deposited on the whole surface of the substrate 1, the surface of the substrate 1 is flattened. After an oxidation-resistant silicon nitriding film 10 was deposited on the whole surface, a part corresponding to the region 6, where no element is formed, is selectively removed and a thick oxide film 11 is formed on the surface. The silicon nitriding film 10 and the silicon dioxide film 2 are removed, the silicon surface of the surface 1 is made to expose and an etching is performed on a part of the embedding material 9, where is appearing upwards from the substrate 1. As a result, the substrate 1 is completely flattened.
JP14632783A 1983-08-12 1983-08-12 Semiconductor device and manufacture thereof Pending JPS6038831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14632783A JPS6038831A (en) 1983-08-12 1983-08-12 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14632783A JPS6038831A (en) 1983-08-12 1983-08-12 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6038831A true JPS6038831A (en) 1985-02-28

Family

ID=15405164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14632783A Pending JPS6038831A (en) 1983-08-12 1983-08-12 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6038831A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639948A (en) * 1986-06-30 1988-01-16 Nec Corp Semiconductor device
US4980311A (en) * 1987-05-05 1990-12-25 Seiko Epson Corporation Method of fabricating a semiconductor device
US5141888A (en) * 1982-09-29 1992-08-25 Hitachi, Ltd. Process of manufacturing semiconductor integrated circuit device having trench and field isolation regions
US5899727A (en) * 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
US5915191A (en) * 1994-11-03 1999-06-22 Lg Semicon Co., Ltd. Method for fabricating a semiconductor device with improved device integration and field-region insulation
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5981357A (en) * 1996-04-10 1999-11-09 Advanced Micro Devices, Inc. Semiconductor trench isolation with improved planarization methodology

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5141888A (en) * 1982-09-29 1992-08-25 Hitachi, Ltd. Process of manufacturing semiconductor integrated circuit device having trench and field isolation regions
JPS639948A (en) * 1986-06-30 1988-01-16 Nec Corp Semiconductor device
US4980311A (en) * 1987-05-05 1990-12-25 Seiko Epson Corporation Method of fabricating a semiconductor device
US5915191A (en) * 1994-11-03 1999-06-22 Lg Semicon Co., Ltd. Method for fabricating a semiconductor device with improved device integration and field-region insulation
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
US5981357A (en) * 1996-04-10 1999-11-09 Advanced Micro Devices, Inc. Semiconductor trench isolation with improved planarization methodology
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5899727A (en) * 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US6353253B2 (en) 1996-05-02 2002-03-05 Advanced Micro Devices, Inc. Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

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